NEC V850ES/DJ2 User Manual

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User’s Manual

V850ES/DJ2

32-bit System in Package Microcontroller Hardware

µPD70F3325

Document No. U17763EE1V1UD00 Date Published September 2005  NEC Electronics 2005 Printed in Germany

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User’s Manual U17763EE1V1UD00

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NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V

IH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

IL (MAX) and VIH (MIN) due to noise, etc., the device may

IL (MAX) and

DD or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

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The information in this document is current as of September, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

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NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative

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purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

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While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.

"Standard":

"Special":

"Specific":

Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note) (1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

M8E 02 . 11-1

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All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office.

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Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

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Ordering information

Product release schedule

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Availability of related technical literature

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Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

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In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics America Inc.

Santa Clara, California

el: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

el: 0211-65 03 1101

Fax: 0211-65 03 1327

Sucursal en España

Madrid, Spain Tel: 091- 504 27 87 Fax: 091- 504 28 60

Succursale Française

Vélizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99

Filiale Italiana

Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99

Branch The Netherlands

Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80

Branch Sweden

Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388

United Kingdom Branch

Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290

NEC Electronics Hong Kong Ltd.

Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

Singapore Tel: 65-6253-8311 Fax: 65-6250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951

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Preface

Readers This manual is intented for users who want to understand the functions of the

V850ES/DJ2.

Purpose This manual presents the hardware manual of the V850ES/DJ2.

This User’s Manual is an extension of the F_Line User’s Manual. F_Line Items: For all of the items regarding the FG2 please refer to the F_Line User’s

Manual/Data sheet (U17215EJ2V0UD00 (2nd edition) and further releases). MTRC of D_Line: In this User’s Manual/Data Sheet all of the MTRC relevant items and the

internal connection or pinout of the D_Line device are regarded.

Organization This system specification describes the following sections:

• Pin function

• Port function

• Internal peripheral function

• Electrical target specification

Legend Symbols and notation are used as follows:

Weight in data notation : Left is high-order column, right is low order column Active low notation : xxx

(pin or signal name is over-scored) or

/xxx (slash before signal name)

Memory map address: : High order at high stage and low order at low stage

Note : Explanation of (Note) in the text Caution : Item deserving extra attention Remark : Supplementary explanation to the text

Numeric notation : Binary . . . Decimal . . .

XXXX or XXXB

XXXX

Hexadecimal . . . XXXXH or 0x XXXX Prefixes representing powers of 2 (address space, memory capacity)

K (kilo): 2 M (mega): 2 G (giga): 2

= 1024

= 10242 = 1,048,576

= 10243 = 1,073,741,824

User’s Manual U17763EE 1V 1UD00

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User’s Manual U17763EE1V1UD00

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Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2 Features (V850ES/D_Line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3 About the Subject of this User’s Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4 Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4.1 System in Package (SiP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5 Communication Between the FG2 and MTRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.1 Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5.2 Internal or external communication via CSIB1 . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.6 Pinout of DJ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.7 Overview of MTRC Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.8 Peripheral I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Chapter 2 V850ES/FG2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2.2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

2.3 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.4 Clock Generation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.5 16-bit Timer/event Counter P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.6 16-bit Timer/event Counter Q. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.7 16-bit Interval Timer M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.8 Watch Timer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.9 Functions of Watchdog Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.10 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.11 Asynchronous Serial Interface A (UARTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.12 3-Wire Serial Interface (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.13 CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.14 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2.15 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.16 Key Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.17 Standby Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.18 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

2.19 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2.20 Low-voltage Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.21 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.22 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

2.23 ROM Mask Options Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.24 On-chip Debug Unit (Flash Memory Versions only). . . . . . . . . . . . . . . . . . . . . . . . . . 64

Chapter 3 Pin Function of MTRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.1 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.2 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.3 Pin I/O Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.1 Type A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.2 Type B-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.3 Type B-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.3.4 Type D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.3.5 Type D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.3.6 Type D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.3.7 Type D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.3.8 Type CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.3.9 Type MTCS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.3.10 Type SCK

3.3.11 Type SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.3.12 Type SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Chapter 4 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.1 Setting Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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4.2 Port MT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.2.1 Port MT0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2.2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3 Port MT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.3.1 Port MT1 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.3.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.4 Port SM1/SM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.4.1 Port SM1/SM2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.5 Port MT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.5.1 Port MT2 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.5.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.6 Port MT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

4.6.1 Port MT3 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.6.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.7 Port MT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

4.7.1 Port MT4 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Chapter 5 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1.1 Autocalibration function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1.2 Ring Oscillator states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.2 Ring Oscillator Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.2.1 RingOSC Control Register (MRCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

5.2.2 RingOSC Calibration Register (MRCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

5.3 Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.4 MTRESET Release of the MTRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.5 Standby Mode Release of the Ring Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.6 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Chapter 6 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.1 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6.2 Command Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

6.2.1 Command Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

6.2.2 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.3 Serial I/F Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3.1 Read from MTRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3.2 Timing of MTRC Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

6.3.3 MTRC Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

6.3.4 Timing of MTRC Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.4 External CSIB1 Function (EXCSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.5 Internal CSIB1 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.5.1 Operation of Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Chapter 7 Meter Controller Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.1 Meter Controller Driver Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

7.2 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

7.2.1 Free Running Counter m (MCNTm, m = 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . .115

7.2.2 Sin Compare Register n0 (MCMPn0, n = 1 to 6) . . . . . . . . . . . . . . . . . . . . . . . 116

7.2.3 Cos Compare Register n1 (MCMPn1, n = 1 to 6). . . . . . . . . . . . . . . . . . . . . . . 117

7.2.4 Compare Control Register (MCMPCn, n = 1 to 6) . . . . . . . . . . . . . . . . . . . . . . 118

7.2.5 Timer Mode Control Register (MCNTm) (m = 0, 1) . . . . . . . . . . . . . . . . . . . . . 120

7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 22

7.3.1 Count timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.3.2 Operation of 1-bit addition circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

7.3.3 PWM output with 1 clock shifted operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .124

7.4 Method of Using. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.4.1 Macro Standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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Chapter 8 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.1 Separated Reset Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.2 External Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.2.1 External reset circuitry with pull-down resistor . . . . . . . . . . . . . . . . . . . . . . . . . 128

8.2.2 External reset circuitry with pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Chapter 9 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

9.1 Absolute Maximum Ratings (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

9.2 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.3 Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9.4 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.4.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . 133

9.4.2 Sub System Clock Oscillation Circuit Characteristics. . . . . . . . . . . . . . . . . . . . 134

9.4.3 MTRC Ring Oscillator Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . 135

9.4.4 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.4.5 Ring-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.5 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.6.2 Pin Leak Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

9.6.3 Specific Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

9.6.4 Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

9.7 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

9.7.1 EXCLO output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

9.7.2 RESET

9.7.3 Key Return timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.7.4 Timer Input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

9.7.5 CSI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

9.7.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

9.7.7 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

9.7.8 AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

9.7.9 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

9.7.10 RAM retention flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

9.7.11 Flash Memory Programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 150

, Interrupt, FLMD0 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 10 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 11 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Appendix A Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

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Page 13

Figure 1-1: D_Line SiP .................................................................................................................. 18

Figure 1-2: CS Functionality .......................................................................................................... 20

Figure 1-3: Pinout of DJ2............................................................................................................... 21

Figure 1-4: Block Diagram of the MTRC........................................................................................ 22

Figure 2-1: Block Diagram............................................................................................................. 27

Figure 2-2: Pin I/O Circuit Types (1/2)...........................................................................................35

Figure 2-3: Figure 2-1. Pin I/O Circuit Types (2/2)........................................................................ 36

Figure 2-4: Port Configuration ....................................................................................................... 37

Figure 2-5: Clock Generator .......................................................................................................... 40

Figure 2-6: Figure 6-1. Block Diagram of Timer P........................................................................ 42

Figure 2-7: Figure 7-1. Block Diagram of Timer Q........................................................................ 44

Figure 2-8: Block Diagram of Timer M........................................................................................... 45

Figure 2-9: Block Diagram of Watch Timer.................................................................................... 46

Figure 2-10: Block Diagram of Prescaler 3......................................................................................47

Figure 2-11: Block Diagram of Watchdog Timer 2........................................................................... 48

Figure 2-12: Block Diagram of A/D Converter ................................................................................. 49

Figure 2-13: Block Diagram of Asynchronous Serial Interface A..................................................... 51

Figure 2-14: Block Diagram of 3-Wire Serial Interface .................................................................... 52

Figure 2-15: Block Diagram of CAN Module.................................................................................... 53

Figure 2-16: Block Diagram of DMA Controller................................................................................ 55

Figure 2-17: Key Return Block Diagram.......................................................................................... 56

Figure 2-18: CLM Block Diagram ....................................................................................................59

Figure 2-19: Block Diagram of Low-Voltage Detector ..................................................................... 60

Figure 2-20: Regulator.....................................................................................................................61

Figure 2-21: Connection of REGC Pin (REGC = Capacitance)....................................................... 61

Figure 3-1: Pinout of MTRC........................................................................................................... 66

Figure 3-2: Type A-1...................................................................................................................... 71

Figure 3-3: Type B-1...................................................................................................................... 71

Figure 3-4: Type B-2...................................................................................................................... 72

Figure 3-5: Type D-1...................................................................................................................... 72

Figure 3-6: Type D-2...................................................................................................................... 73

Figure 3-7: Type D-3...................................................................................................................... 73

Figure 3-8: Type D-4...................................................................................................................... 74

Figure 3-9: Type CLK .................................................................................................................... 74

Figure 3-10: Type MTCS................................................................................................................. 74

Figure 3-11: Type SCK

Figure 3-12: Type SI........................................................................................................................ 75

Figure 3-13: Type SO...................................................................................................................... 75

Figure 4-1: Port Register 0 (PMT0) Format .................................................................................. 79

Figure 4-2: Port MT0 Mode Register 0 (PMMT0) Format ............................................................. 79

Figure 4-3: Port Register 1 (PMT1) Format .................................................................................. 81

Figure 4-4: Port Mode Register 1 (PMMT1) Format .....................................................................81

Figure 4-5: Port Mode Control Register 1 (PMCMT1) Format ...................................................... 82

Figure 4-6: SM1SM2 Mode Control Register (SM12MC) Format ................................................. 83

Figure 4-7: Port Register 2 (PMT2) Format .................................................................................. 85

Figure 4-8: Port Mode Register 2 (PMMT2) Format .....................................................................85

Figure 4-9: Port Mode Control Register 2 (PMCMT2) Format ...................................................... 86

Figure 4-10: Port Register 3 (PMT3) Format .................................................................................. 88

Figure 4-11: Port Mode Control Register 3 (PMMT3) Format ......................................................... 88

Figure 4-12: Port Register 4 (PMT4) Format .................................................................................. 90

Figure 4-13: Port Mode Register 4 (PMMT4) Format ..................................................................... 90

Figure 4-14: Port Mode Control Register 4 (PMCMT4) Format ...................................................... 91

Figure 5-1: RingOSC Control Register (MRCTL) Format (1/2) ..................................................... 93

Figure 5-2: RingOSC Calibration Register (MRCAL) Format ....................................................... 95

Figure 5-3: Flowchart for Frequency Calibration ...........................................................................96

Figure 5-4: Timing Diagram for Frequency Calibration.................................................................. 97

Figure 5-5: Flowchart for MTRESET Release ............................................................................... 98

Figure 5-6: Timing for MTRES Release......................................................................................... 99

.................................................................................................................... 75

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Page 14

Figure 5-7: Flowchart for Standby Mode Release ....................................................................... 100

Figure 5-8: Timing Diagram for Standby Mode Release.............................................................. 101

Figure 6-1: MTRC Operation Flow on Reading ...........................................................................106

Figure 6-2: MTRC Read Operation (Auto=0)...............................................................................107

Figure 6-3: MTRC Read Operation (Auto bit = 1)........................................................................ 107

Figure 6-4: Operation Flow on MTRC Writing..............................................................................108

Figure 6-5: MTRC Write Operation (Auto bit = 0)........................................................................ 109

Figure 6-6: MTRC Write Operation (Auto bit = 1)........................................................................ 109

Figure 6-7: Basic Operation......................................................................................................... 112

Figure 6-8: Continuous Data Transfer ......................................................................................... 112

Figure 7-1: Meter Controller Driver Block Diagram...................................................................... 114

Figure 7-2: Free Running Counter MCNTm Format ...................................................................115

Figure 7-3: Sin Compare Register MCMPn0 Format .................................................................. 116

Figure 7-4: Cos Compare Register MCMPn1 Format ................................................................. 117

Figure 7-5: Compare Control Register MCMPCn Format (1/2) .................................................. 118

Figure 7-6: Timer Mode Control Register (MCNTm) Format (1/2) .............................................. 120

Figure 7-7: Restart Timing after Counting Operation Stopped ....................................................122

Figure 7-8: Operation of 1-bit Addition......................................................................................... 123

Figure 7-9: Output Timing of SM11 to SM44 ...............................................................................124

Figure 7-10: Output Timing of SM51 to SM64............................................................................... 124

Figure 7-11: Using of the SM......................................................................................................... 125

Figure 7-12: SM Standby Operation.............................................................................................. 126

Figure 8-1: External Reset Circuitry with Pull-Down Resistor...................................................... 128

Figure 8-2: External Reset Circuitry with Pull-Up Resistor ..........................................................129

Figure 10-1: V850ES/DJ2..............................................................................................................152

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Table 1-1: Features (V850ES/D_Line) ............................................................................................ 17

Table 1-2: Overview of MTRC Functions......................................................................................... 22

Table 1-3: Peripheral I/O Registers ................................................................................................. 23

Table 2-1: Pin I/O Buffer Power Supplies (V850ES/FG2................................................................. 28

Table 2-2: Pin List (Port Pins).......................................................................................................... 28

Table 2-3: Pin List (Non-Port Pins).................................................................................................. 30

Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins.......................... 33

Table 2-5: Assignment of Key Return Detection Pins...................................................................... 56

Table 2-6: Standby Modes............................................................................................................... 57

Table 2-7: Mask Options.................................................................................................................. 63

Table 3-1: List of Pin Functions ....................................................................................................... 67

Table 3-2: List of Pin Functions ....................................................................................................... 69

Table 4-1: Alternate Pin Functions .................................................................................................. 76

Table 4-2: Port MT0 Functions........................................................................................................ 78

Table 4-3: Port MT1 Functions........................................................................................................ 80

Table 4-4: Port MT2 Functions........................................................................................................ 83

Table 4-5: Port MT2 Functions........................................................................................................ 84

Table 4-6: Port MT3 Functions........................................................................................................ 87

Table 4-7: Port MT4 Functions........................................................................................................ 89

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Chapter 1 Introduction

The V850ES/DJ2 is a product of the NEC’s V850 D_Line Series of single-chip microcontroller designed for application with up to 6 stepper motor channels. It provides low-power operation for real-time control ap plications especial for automotive Da shboard applications.

1.1 General

The V850ES/DJ2 is a 32-bit System in Package (SiP) microcontroller that includes a V850ES CPU core device of the F_Line (V850ES/FG2) and a Meter Controller/Driver (MTRC) in one package.

The F_Line includes peri pheral f unctions such as ROM/RA M, a timer /count er, serial interfaces, and an A/D converter. In addition to high real- time r espo nse char acte rist ics and 1-c lock-p itch bas ic i nstruct ion s, the V850E S/ FG2 features multiply instructions, satu rated operation ins tructions, bit manip ulation instructi ons, etc., realised by a h ardware multi plier, as optimum i nstruc tions for di gital se rvo c ontrol a pplic ations. More over, as a real-time control system, the V850ES/FG2 enables extremely high cost-performance for applications that require a low power consumption, such as automotive applications. For an overview of the V850ES/FG3 refer to “V850ES/FG2 Introduction” on page 25.

The integrated MTRC sup plies a meter co ntroller driv er macro for up to 6 st epper motor channels and GPIOs. Via the dedicated interface the controlling will be handled with a dedicated protocol. For this in ter n al in te r f ac e t he 3-wire serial int e r face CSIB1 of the F G2 d ev ice is used for the se ri al communication and the PCM0 port of the FG2 device is used as the CS function for the MTRC.

1.2 Features (V850ES/D_Line)

Table 1-1: Features (V850ES/D_Line)

Part Number Name FG2 device Pin

µPD70F3325 V850ES/DJ2 µPD70F3235(A)/FG2 144 256 12 2 6

Internal Memory

Flash (KB) RAM (KB)

CAN SM

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Chapter 1 Introduction

1.3 About the Subject of this User’s Manual

This User’s Manual is an extension of the F_Line User’s Manual. F_Line Items:

For all of the items regarding the FG2 please refer to the F_Line User’s Manual/Data Sheet (U17215EJ2V0UD00 (2 nd edit ion ) and furthe r relea se s).

MTRC of D_Line: In this User ’s Manual/Data Sh eet all of t he MTRC rel evant item s and the i nternal con nection or p inout of the D_Line device are regarded.

1.4 Internal Connection

The following pins of the FG2 device are connected to the MTRC:

• CSI I/F: SIB1, SOB1, SCKB1

• Chip select: PCM0 as CS

1.4.1 System in Package (SiP)

Figure 1-1: D_Line SiP

1 chip

FG2 Device MTRC

CPU

CSI

CLKOUT

PCM0

SCKB1

SIB1

SOB1

CLK CS

SCK SO SI

CSI

RegCTL

Macro

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Chapter 1 Introduction

1.5 Communication Between the FG2 and MTRC

The clocked synchr onous ser ial interface CSIB1 o f the FG 2 devi ce is used for the co mmunic ation with the MTRC.

The communication I/F of the MTRC is fixed to the following settings:

• I/F: CSI

• Mode: Slave mode

• Data length: 8-bits

(support continuous data transfer, therefore the FG2 CSIB1can use 16-bit data

length)

• Transfer: MSB first

• Transmission: transmission/reception mode

1.5.1 Communication

The software for the comm unicatio n betwe en the FG2 d evice and the MT RC has to ma nage th e I/F of the CSIB1 and the PCM0 pin as chip select signal.

The CSI1B of the FG2 device has been set to master mode, because the MTRC CSI is always in slave mode. Therefore it is ne cessary, that the CSIB1 send s dummy data if the FG2 device wants to r ead data from the MTRC.

The MTRC CSI is always in 8-bit mode but is capa ble of con tinuou s data tra nsfer. Therefore the 16-bit mode of the CSIB1 can be used for faster communication for example.

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Chapter 1 Introduction

1.5.2 Internal or external communication via CSIB1

Via the PCM0/CS signal the output functionality of the PMT4 port will be controlled, too.

Figure 1-2: CS Functionality

V850ES/FG2

CLKOUT

SIB1

SOB1

SCKB1

PCM0

MTRC

CLK

SO SI SCK

Last byte

control

PMT43/EXCLO

Macro

PMT40/EXSI1

PMT41/EXSO1

PMT42/EXSCK1

DJ2 pins

EXCSI1

MTCS

If the PMT4 port is configured for periphe ral mode the PCM0/CS signal controls the out put function of the external CSIB1 (EX CSI1) functionality. The EXCSIB1 provide the FG 2 CSIB1 communication for external components, too. This function can b e u se d, if ther e’s no i nte rn al c omm uni ca tio n b etwe en the FG2 device and the MTRC. With special regard to the las t byte transfer of the inte rnal commu nicat ion proto col a s witch control will delay the switching until the last byte was transferred between FG2 and the MTRC.

PCM0/CS

and

EX_CSIB1 signals

MTCS

1 EX_CSIB1 signals are in inactive state regardless to the communication of the CSIB1 0 EX_CSIB1 signals are active, dependent of the communication of the CSIB1

If PMT4 is in port mode the signal of PMT4 depends only on the settings of the PMT4 SFRs.

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1.6 Pinout of DJ2

Chapter 1 Introduction

Figure 1-3: Pinout of DJ2

P74/ANI4 P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

AVREF0

AVSS

P10/INTP9

P11/INTP10

P00/TIP31/TOP31

P01/TIP30/TOP30

FLMD0

REGC

RESET

XT1

XT2

P02/NMI

P03/INTP0/ADTRG

P04/INTP1

P05/INTP2/DRST

P06/INTP3

P40/SIB0

P41/SOB0 P42/SCKB0 P30/TXDA0

P32/ASCKA0/TOP01/TIP00/TOP00

P31/RXDA0/INTP7

P33/TIP01/TOP01/CTXD0

P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11

P36/CTXD1

PDL2

122

PDL1

121

PDL0

120

PCT6

PCT4

BVDD

118

117

119

116

P78/ANI8

P79/ANI9

P710/ANI10

P711/ANI11

P712/ANI12

P713/ANI13

P714/ANI14

PDL13

PDL12

PDL11

138

137

136

P715/ANI15

135

134

133

132

131

V850ES/DJ2

PDL10

130

P76/ANI6

P75/ANI5

P77/ANI7

144

143

142

141

140 1 2 3 4 5 6

7 8 9

X1 X2

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33 34 35 36

37383940414243444546474849505152535455

139

PDL9

129

PDL8

128

PDL7

127

PDL6

126

PDL5/FLMD1

125

PDL4

123

124

575859606162636465

PDL3

PCT1

PCT0

PCM3

115

114

113

6768697071

PCM2

112

DD2

MTV

111

PCS1

110

PCS0

109

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79

78 77 76 75 74 73

PMT43/EXCLO PMT33 PMT32 PMT31 PMT30

SS3

SMV SMVDD3 PMT27/SM64 PMT26/SM63 PMT25/SM62 PMT24/SM61 PMT23/SM54 PMT22/SM53 PMT21/SM52 PMT20/SM51 SMV

SS2

SMVDD2 PMT17/SM44 PMT16/DM43 PMT15/SM42 PMT14/SM41 PMT13/SM34 PMT12/SM33 PMT11/SM32 PMT10/SM31 SM24 SM23 SM22 SM21 SM14 SM13 SM12 SM11 SMVDD1 SMVSS1 PMT03

P910

P911

EVSS

EVDD

P37/CRXD1

P38/TXDA2

P39/RXDA2/INTP8

P50/KR0/TIQ01/TOQ01

P51/KR1/TIQ02/TOQ02

P52/KR2/TIQ03/TOQ03/DDI

P54/KR4/DCK

P55/KR5/DMS

P90/KR6/TXDA1

P91/KR7/RXDA1

P92/TIQ11/TOQ11

P94/TIQ13/TOQ13

P93/TIQ12/TOQ12

P53/KR3/TIQ00/TOQ00/DDO

P912

P96/TIP21/TOP21

P95/TIQ10/TOQ10

User’s Manual U17763EE 1V 1UD00

MTCS

P914/INTP5

P915/INTP6

PMT40/EXSI1

P913/INTP4/PCL

DD1

MTVSS1

MTV

PMT41/EXSO1

PMT42/EXSCK1

PMT01

PMT00

MTRESET

MTRC pins

PMT02

Page 22

Chapter 1 Introduction

1.7 Overview of MTRC Functions

Table 1-2: Overview of MTRC Functions

Operating Frequency Max. 16 MHz (typ. 8 MHz) Meter Driver 360° × 6 channels

Ports

Connection between FG2 device and MTRC

Power Supply voltage range 4.0 V to 5.5 V

I/O 16 O16

3-Wire Serial Interface (CSI) slave mode, 8-bit, single/continuous mode

Figure 1-4: Block Diagram of the MTRC

PMT00 - PMT03

PMT10 - PMT17

PMT20 - PMT27

PMT30 - PMT37

PMT40 - PMT43

EXCLO

EXSI1

EXSCK1

EXSO1

Note

PMT0

PMT1

PMT2

PMT3

PMT4

Serial

Reg. CTL

SCK CS

MTRC

SM11 - SM14

SM21 - SM24 SM31 - SM34 SM41 - SM44 SM51 - SM54 SM61 - SM64

MTRESET MTVDD1, MTVDD2

SMVDD1, SMVDD2, SMVDD3

MTVSS SMVSS1, SMVSS2, SMVSS3

Note: I/O ports of PMT3 are used in the V850ES/DJ2 as follows:

• V850ES/DJ2, 144-pin: PMT30-PMT33

User’s Manual U17763EE1V1UD00

Page 23

1.8 Peripheral I/O Registers

Chapter 1 Introduction

Table 1-3: Peripheral I/O Registers

Address Register Name Symbol

00H Compare Register 10 MCMP10 00H × R/W 01H Compare Register 11 MCMP11 00H × R/W 02H Compare Control Register 1 MCMPC1 00H × R/W 03H Compare Register 20 MCMP20 00H × R/W 04H Compare Register 21 MCMP21 00H × R/W 05H Compare Control Register 2 MCMPC2 00H × R/W 06H Compare Register 30 MCMP30 00H × R/W 07H Compare Register 31 MCMP31 00H × R/W 08H Compare Control Register 3 MCMPC3 00H × R/W 09H Compare Register 40 MCMP40 00H × R/W 0AH Compare Register 41 MCMP41 00H × R/W 0BH Compare Control Register 4 MCMPC4 00H × R/W 0CH Compare Register 50 MCMP50 00H × R/W 0DH Compare Register 51 MCMP51 00H × R/W 0EH Compare Control Register 5 MCMPC5 00H × R/W 0FH Compare Register 60 MCMP60 00H × R/W 10H Compare Register 61 MCMP61 00H × R/W

11H Compare Control Register 6 MCMPC6 00H × R/W 12H Timer Mode Control Register 0 MCNTC0 00H × R/W 13H Timer Mode Control Register 1 MCNTC1 00H × R/W 20H Port MT0 PMT0 Undefined × R/W 21H Port MT1 PMT1 Undefined × R/W 22H Port MT2 PMT2 Undefined × R/W 23H Port MT3 PMT3 Undefined × R/W 24H Port MT4 PMT4 Undefined × R/W 25H Port MT0 Mode Register PMMT0 FFH × R/W 26H Port MT1 Mode Register PMMT1 FFH × R/W 27H Port MT2 Mode Register PMMT2 FFH × R/W 28H Port MT3 Mode Register PMMT3 FFH × R/W 29H Port MT4 Mode Register PMMT4 FFH × R/W 2AH Port MT1 Mode Control Register PMCMT1 00H × R/W 2BH Port MT2 Mode Control Register PMCMT2 00H × R/W 2CH Port MT4 Mode Control Register PMCMT4 00H × R/W 2DH SM1SM2 Mode Control Register SM12MC 00H × R/W 2EH Ring Oscillator Control Register MRCTL 50H × R/W 31H Calibration Register MRCAL 10H × R/W

Initial Value After Reset

Access

1-bit 8-bit 16-bit

R/W

User’s Manual U17763EE 1V 1UD00

Page 24

[MEMO]

User’s Manual U17763EE1V1UD00

Page 25

Chapter 2 V850ES/FG2 Introduction

The V850ES/FG2 is o ne of the products of NE C Electronics’ V85 0 Series of single-ch ip microcontrollers for real-time control.

The V850ES/FG2 is a 32-bit si ngle-chip mi crocontroller that includes the V850ES CPU core and integrate peripheral functi ons such as ROM/RA M, DMA controller, and timers/counte rs. These microco ntrollers also incorporate a CAN (Controller Area Network) as an automotive LAN.

In addition to highly real-time responsive, 1-clock-pitch basic instructions, this microcontroller have instructions ideal for digital servo applications, such as multiplication instructions using a hardware multiplier, sum-of-products ope ration instructions, and bi t manipulation instructio ns. This microcontroller can also realize a real-ti me control system that is highly cost effective and can be used in automotive instrumentation fields.

• Number of instructions: 83

• Minimum instruction execution time:50 ns (main clock (f

• General-purpose registers: 32 bits × 32

• Instruction set

• Power-on clear function

• Low-voltage detection function

• Ring-OSC: 200 kHz (TYP.)

• Interrupts/exceptions

Non-maskable interrupts Maskable interrup ts

• I/O lines I/O ports: 84

• Timer/counters

16-bit interval timer M (TMM): 1 ch 16-bit timer/event counter P (TMP): 4 ch 16-bit timer/event counte r Q (TM Q): 2 ch

• Watch timer: 1 ch

XX) = 20 MHz)

• Watchdog timer 2: 1 ch

• Serial interface (SIO)

Asynchronous serial interface A (UART) 3-wire variable-length serial interface B (CSIB)

• CAN controller: 2 ch

• A/D converter 10-bit resolution: 16 ch

• Clock generator

Main clock/subclock operation CPU clock in seven steps (f Clock-through mode/PLL mode selectable

Preliminary User’s Manual U17763EE1V1UD00

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

Page 26

• Power save function

-HALT

-IDLE1

-IDLE2

- software STOP

- subclock

- sub-IDLE modes

Pin identification

Chapter 2 V850ES/FG2 Introduction

ADTRG: ANI0 to ANI15: ASCKA0:

REF0:

SS:

DD:

SS:

BV CLKOUT: CRXD0, CRXD1: CTXD0, CTXD1: DCK: DDI: DDO: DMS: DRST:

DD:

SS:

EV FLMD0, FLMD1: INTP0 to INTP10: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P70 to P715: P90 to P915: PCL:

A/D trigger input Analog input Asynchronous seri al clock Analog reference voltage Analog V

Power supply for bus interface Ground for bus interface Clock output Receive data for controller area network Transmit data for controller area network Debug clock Debug data input Debug data output Debug mode select Debug reset Power supply for port Ground for port Flash programming mode Interrupt request from peripherals Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 7 Port 9 Programmable clock output

PCM0 to PCM3: PCS0, PCS1: PCT0, PCT1, PCT4, PCT6: PDL0 to PDL13: REGC: RESET: RXDA0 to RXDA2: SCKB0, SCKB1: SIB0, SIB1: SOB0, SOB1: TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13: TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31, TOQ01 to TOQ03, TOQ11 to TOQ13: TXDA0 to TXDA2:

DD:

SS:

V X1, X2: XT1, XT2:

Port CM Port CS

Port CT Port DL Regulator control Reset Receive data Serial clock Serial input Serial output Timer i nput

Timer output

Transmit data Power supply Ground Crystal for main clock Crystal for subclock

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Page 27

Chapter 2 V850ES/FG2 Introduction

Figure 2-1: Block Diagram

NMI

INTP0 to INTP10

TIQ00 to TIQ10 TIQ01 to TIQ11 TIQ02 to TIQ12 TIQ03 to TIQ13

TOQ00 to TOQ10

TOQ01 to TOQ11

TOQ02 to TOQ12

TOQ03 to TOQ13

TIP00 to TIP30 TIP01 to TIP31

TOP00 to TOP30 TOP01 to TOP31

SOB0, SOB1

SIB0, SIB1

SCKB0, SCKB1

TXDA0 to TXDA2

RXDA0 to RXDA2

ASCKA0

CTXD0, CTXD1

CRXD0, CRXD1

ANI0 to ANI15

AVREF0

ADTRG

KR0 to KR7

INTC

16-bit timer/

counter Q:

2 ch

16-bit timer/

Flash Memory

256 KB, 384 KB

Mask Rom

128 KB,

256 KB

RAM

6 KB , 12 KB,

16 KB

DMAC

32-bit barrel shifter

System

registers

Generalpurpose register 32 bits × 32

CPU

Multiplier 16 × 16 → 32

ALU

Instruction queue

BCU

counter P:

4 ch

16-bit

interval

timer M:

1 ch

CSIB: 2 ch

UARTA: 3 ch

Ports

PCS0, PCS1

P90 to P915

PCM0 to PCM3

PDL0 to PDL13

P10, P11

P50 to P55

P40 to P42

P30 to P39

P70 to P715

P00 to P06

PLL

PCL CLKOUT XT1 XT2

X1 X2

RESET

FLMD0

FLMD0 FLMD1

PCT0, PCT1, PCT4, PCT6

CAN: 2 ch

BVDD BVSS EVDD EVSS

A/D

converter

Key return

function

Watchdog

timer 2

RCU

RSU

ROMC

DRST DMS DDO DCK DDI

On chip debug

Regulator

CLM

POC/LVI

VDD VSS REGC

Watch timer

Preliminary User’s Manual U17763EE1V1UD00

Page 28

Chapter 2 V850ES/FG2 Introduction

2.1 Pin Functions

This section explains the names and functions of the pins of the V850ES/FG2. Three I/O buffer power supplies, AV

REF0, BVDD and EVDD, are availa ble. The rela tionship between the

power supplies and the pins is shown below.

Table 2-1: Pin I/O Buffer Power Supplies (V850ES/FG2

Power Supply Corresponding Pin AV EV BV

REF0

Port 7 Port 0, Port 1, Port 3, Port 4, Port 5, Port 9, RESET Port CM, Port CS, Port CT, Port DL

Table 2-2: Pin List (Port Pins)

Pin Name I/O Function P00 P01 TIP30/TOP30 P02 NMI P03 INTP0/ADTRG

I/O

P04 INTP1

Port 0 7-bit I/O port Input/output can be specified in 1-bit units.

P05 INTP2/DRST P06 INTP3 P10

I/O

P11 INTP10

Port 1 2-bit I/O port Input/output can be specified in 1-bit units.

Alternate Function TIP31/TOP31

INTP9

P30

TXDA0

P31 RXDA0/INTP7 P32 P33 TIP01/TOP01/CTXD0

P34 TIP10/TOP10/CRXD0

I/O

P35 TIP11/TOP11

Port 3 10-bit I/O port Input/output can be specified in 1-bit units.

ASCKA0/TIP00/TOP00/ TOP01

P36 CTXD1 P37 CRXD1 P38 TXDA2 P39 RXDA2/INTP8 P40 P41 SOB0

I/O

P42 SCKB0

Port 4 3-bit I/O port Input/output can be specified in 1-bit units.

SIB0

Preliminary User’s Manual U17763EE1V1UD00

Page 29

Chapter 2 V850ES/FG2 Introduction

Table 2-2: Pin List (Port Pins) (Continued)

Pin Name I/O Function P50 P51 KR1/TIQ02/TOQ02 P52 KR2/TIQ03/TOQ03/DDI P53 KR3/TIQ00/TOQ00/DDO P54 KR4/DCK P55 KR5/DMS

P70 to P715 I/O

P90 P91 KR7/RXDA1 P92 TIQ11/TOQ11 P93 TIQ12/TOQ12 P94 TIQ13/TOQ13 P95 TIQ10/TOQ10 P96 TIP21/TOP21 P97 SIB1/TIP20/TOP20 P98 SOB1 P99 SCKB1 P910 P911 P912 P913 INTP4/PCL P914 INTP5 P915 INTP6 PCM0 PCM1 CLKOUT PCM2, PCM3 -

PCS0, PCS1 I/O

PCT0, PCT1, PCT4, PCT6

PDL0 to PDL4 PDL5 FLMD1 PDL6 to

PDL13

I/O

Port 5 6-bit I/O port Input/output can be specified in 1-bit units.

Port 7 16-bit I/O port Input/output can be specified in 1-bit units.

Port 9 16-bit I/O port Input/output can be specified in 1-bit units.

Port CM 4-bit I/O port Input/output can be specified in 1-bit units.

Port CS 2-bit I/O port Input/output can be specified in 1-bit units.

Port CT 4-bit I/O port Input/output can be specified in 1-bit units.

Port DL 14-bit I/O port Input/output can be specified in 1-bit units.

Alternate Function KR0/TIQ01/TOQ01

ANI0 to ANI15

KR6/TXDA1

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Page 30

Chapter 2 V850ES/FG2 Introduction

Table 2-3: Pin List (Non-Port Pins)

)

Pin Name I/O NMI Input INTP0

Function External interrupt input

(non-maskable, with analog noise eliminated)

Alternate Function P02

P03/ADTRG INTP1 P04 INTP2 P05/DRST INTP3 P06 INTP4 P913/PCL INTP5 P914

Input

External interrupt request input (maskable, with analog noise eliminated)

INTP6 P915 INTP7 P31/RXDA0 INTP8 P39/RXDA2 INTP9 P10 INTP10 P11

TIP00

External event/clock input (TMP00)

P32/ASCKA0/TOP00/

TOP01 TIP01 External event/clock input (TMP01) P33/TOP01/CTXD0 TIP10 External event/clock input (TMP10) P34/TOP10/CRXD0 TIP11 External event/clock input (TMP11) P35/TOP11

Input

TIP20 External event/clock input (TMP20) P97/SIB1/TOP20 TIP21 External event/clock input (TMP21) P96/TOP21 TIP30 External event/clock input (TMP30) P01/TOP30 TIP31 External event/clock input (TMP31) P00/TOP31 TOP00

Timer output (TMP00) P32/ASCKA0/TIP00/TOP01

P32/ASCKA0/TIP00/TOP00 TOP01 Timer output (TMP01)

P33/TIP01/CTXD0 TOP10 Timer output (TMP10) P34/TIP10/CRXD0 TOP11 Timer output (TMP11) P35/TIP11

Output TOP20 Timer output (TMP20) P97/SIB1/TIP20 TOP21 Timer output (TMP21) P96/TIP21 TOP30 Timer output (TMP30) P01/TIP30 TOP31 Timer output (TMP31) P00/TIP31 TIQ00

External event/clock input (TMQ00) P53/KR3/TOQ00/DDO TIQ01 External event input (TMQ01) P50/KR0/TOQ01 TIQ02 External event input (TMQ02) P51/KR1/TOQ02 TIQ03 External event input (TM Q 03) P52/KR2/TOQ03/DDI TIQ10 External event input (TMQ10) P95/TOQ10

Input

TIQ11 External event input (TMQ11) P92/TOQ11 TIQ12 External event input (TMQ12) P93/TOQ12 TIQ13 External event input (TMQ13) P94/TOQ13

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Page 31

Chapter 2 V850ES/FG2 Introduction

Table 2-3: Pin List (Non-Port Pins) (Continued)

Pin Name I/O TOQ00

Function Timer output (TMQ00) P53/KR3/TIQ00/DDO

Alternate Function

TOQ01 Timer output (TMQ01) P50/KR0/TIQ01 TOQ02 Timer output (TMQ02) P51/KR1/TIQ02 TOQ03 Timer output (TMQ03) P52/KR2/TIQ03/DDI TOQ10 Timer output (TMQ10) P95/TIQ10

Output

TOQ11 Timer output (TMQ11) P92/TIQ11 TOQ12 Timer output (TMQ12) P93/TIQ12 TOQ13 Timer output (TMQ13) P94/TIQ13 SIB0

Input

Serial receive data input (CSIB0) P40 SIB1 Serial receive data input (CSIB1) P97/TIP20/TOP20 SOB0

Serial transmit data output (CSIB0) P41

Output

SOB1 Serial transmit data output (CSIB1) P98 SCKB0 SCKB1 Serial clock I/O (CSIB1) P99

I/O

RXDA0 RXDA1 Serial receive data input (UARTA1) P91/KR7

Input

Serial clock I/O (CSIB0) P42

Serial receive data input (UARTA0) P31/INTP7

RXDA2 Serial receive data input (UARTA2) P39/INTP8 TXDA0 TXDA1 Serial transmit data output (UARTA1) P90/KR6

Output

Serial transmit data output (UARTA0) P30

TXDA2 Serial transmit data output (UARTA2) P38 ASCKA0 Input Baud rate clock input to UARTA0 P32/TIP00/TOP00/TOP01 CRXD0 CRXD1 CAN receive data input (CAN1) P37 CTXD0

Input

Output

CAN receive data input (CAN0) P34/TIP10/TOP10

CAN transmit data output (CAN0) P33/TIP01/TOP01 CTXD1 CAN transmit data output (CAN1) P36 ANI0 to ANI15 Input Analog voltage input to A/D converter P70 to P715

REF0

Input

–

Reference voltage input to A/D converter (same

potential as VDD)

Ground potential for A/D and D/A converters (same

potential as V

)

–

ADTRG Input A/D converter external trigger input P03/INTP0 KR0

P50/TIQ01/TOQ01 KR1 P51/TIQ02/TOQ02 KR2 P52/TIQ03/TOQ03/DDI KR3 P53/TIQ00/TOQ00/DDO KR4 P54/DCK

Input Key interrupt input

KR5 P55/DMS KR6 P90/TXDA1 KR7 P91/RXDA1 DMS Input Debug mode select P55/KR5 DDI Input Debug data input P52/KR2/TIQ03/TOQ03 DDO Output Debug data output P53/KR3/TIQ00/TOQ00

Preliminary User’s Manual U17763EE1V1UD00

Page 32

Chapter 2 V850ES/FG2 Introduction

Table 2-3: Pin List (Non-Port Pins) (Continued)

Pin Name I/O

Function

Alternate Function DCK Input Debug clock input P54/KR4 DRST Input Debug reset input P05/INTP2 FLMD0

Input Flash programming mode setting pins

FLMD1 PDL5 CLKOUT Output Internal system clock output PCM1

PCL Output

Clock output (timing out put of X1 input clock and subclock)

P913/INTP4

REGC - Regulator output stabilizing capacitor connection RESET Input System reset input X1 Input

Main clock resonator connection

X2 - XT1 Input XT2 - V V

- Positive power supply pin for internal circuitry -

- Ground potential for internal circuitry -

Subclock resonator connection

Positive power supply pin for external circuitry (same potential as V

)

Ground potential for external circuitry (same potential

)

as V

Positive power supply pin for external circuitry (same potential as V

)

Ground potential for external circuitry (same potential

)

as V

Preliminary User’s Manual U17763EE1V1UD00

Page 33

Chapter 2 V850ES/FG2 Introduction

Table 2-4: Pin I/O Circuit Types a nd Recommended Connection of Unused Pins

I/O Cir-

cuit Type P00/TIP31/TOP31 P01/TIP30/TOP30 P02/NMI

5-W P03/INTP0/ADTRG P04/INTP1

P05/INTP2/DRST 5-AF

P06/INTP3 5-W

P10/INTP9

5-W P11/INTP10

P30/TXDA0 5-A P31/RXDA0/INTP7 P32/ASCKA0/TIP00/TOP00/

TOP01 P33/TIP01/TOP01/CTXD0

5-W P34/TIP10/TOP10/CRXD0

P35/TIP11/TOP11 P36/CTXD1 5-A P37/CRXD1 5-W P38/TXDA2 5-A P39/RXDA2/INTP8 5-W P40/SIB0 5-W P41/SOB0 5-A P42/SCKB0 P50/KR0/TIQ01/TOQ01 P51/KR1/TIQ02/TOQ02 P52/KR2/TIQ03/TOQ03/DDI

5-W P53/KR3/TIQ00/TOQ00/DDO P54/KR4/DCK P55/KR5/DMS P70/ANI0 to P71 1/ANI11

11-G P712/ANI12 to P715/ANI15

P90/KR6/TXDA1 P91/KR7/RXDA1 P92/TIQ11/TOQ11

5-W P93/TIQ12/TOQ12

P94/TIQ13/TOQ13 P95/TIQ10/TOQ10

Recommended Connection

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to EVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

Input: Independently connect to AVREF0 or AVSS via a resistor

Output: Leave open

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

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Page 34

Chapter 2 V850ES/FG2 Introduction

Table 2-4: Pin I/O Circuit Types and Recommended Connection of Unused Pins (Continued)

P96/TIP21/TOP21

5-W

P97/SIB1/TIP20/TOP20 P98/SOB1 5-A P99/SCKB1 5-W P910

5-AP911

Input: Independently connect to EVDD or EVSS via a resistor

Output: Leave open

P912 P913/INTP4/PCL

5-WP914/INTP5 P915/INTP6 PCM0 PCM1/CLKOUT

Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

PCM2, PCM3 PCS0, PCS1 5

PCT0, PCT1, PCT4, PCT6 5

Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open

Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open PDL0 to PDL4 PDL5/ FLMD1

Input: Independently connect to BVDD or BVSS via a resistor

Output: Leave open PDL6 to AD13

REF0

FLMD0

- Directly connect to V

REGC - RESET 2 X1 - X2 - XT1 16 Connect to VSS via a resistor XT2 16 Leave open V V BV BV EV EV

a. If noise that exceeds the noise elimination width is input to th e RESET pin durin g self pro gram m ing , the fl ash

on-board mode may b e entered de pending o n the capa citance c harge end timing whe n a capac itor is co nnected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.

Preliminary User’s Manual U17763EE1V1UD00

Page 35

Chapter 2 V850ES/FG2 Introduction

Figure 2-2: Pin I/O Circuit Types (1/2)

Type 2 Type 5-AF

Pullup enable

Input enable

Schmitt-triggered input with hysteresis characteristics

Type 5 Type 11-G

Pulldown enable

Data

Output disable

REF0

P-ch

-ch

P-ch

-ch

IN/OUT

Data

Output

disable

Input

enable

P-ch

N-ch

IN/OUT

Data

Output disable

Comparator

+ _

REF

(Threshold voltage)

Input enable

AVSS

P-ch

N-ch

P-ch

IN/OU

N-ch

AVSS

Preliminary User’s Manual U17763EE1V1UD00

Page 36

Chapter 2 V850ES/FG2 Introduction

Figure 2-3: Figure 2-1. Pin I/O Circuit Types (2/2)

Type 5-A

Pullup

enable

Data

Output

disable

Input

enable

Type 5-W

Pullup enable

Data

Output disable

P-ch

N-ch

P-ch

-ch

VDD

P-ch

Type 16

Feedback cut-off

P-ch

IN/OUT

XT1 XT2

IN/OUT

Input enable

Preliminary User’s Manual U17763EE1V1UD00

Page 37

Chapter 2 V850ES/FG2 Introduction

2.2 Port Functions

Features

• I/O ports: 84

• Port pins function alternately as other peripheral-function I/O pins

• Can be set in input or output mode in 1-bit units.

The V850ES/FG2 has a total of 84 I/O ports, ports 0, 1, 3 to 5, 7, 9, CM, CS, CT, and DL. The port configuration is shown below.

Figure 2-4: Port Configuration

Port 0

Port 1

Port 3

Port 4

Port 5

Port 7

P00 P06 P10

P11 P30 P39 P40 P42 P50 P55 P70 P715

P90

P915 PCM0 PCM3

PCS0 PCS1

PCT0 PCT1 PCT4 PCT6

PDL0

PDL13

Port 9

Port CM

Port CS

Port CT

Port DL

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Chapter 2 V850ES/FG2 Introduction

2.3 CPU Functions

Based on the RISC ar ch ite ct ure, the CPU of the V850ES/FG 2 exe cu tes most of the instruction s in o ne clock under control of a five-stage pipeline.

Features

• Minimum instruction execution time: 50 ns (at 20 MHz operation)

• Memory space

- Program space: 64 MB, linear

- Data space: 4 GB, linear

• General-purpose registers: 32 bits × 32

• Internal 32-bit architecture

• Five-stage pipeline control

• Multiplication/division instructions

• Saturation operation inst ru ction s

• 32-bit shift instructions: 1 clock

• Load/store instructions with long/short format

• Four types of bit manipulation instructions

-SET1

-CLR1

-NOT1

-TST1

Preliminary User’s Manual U17763EE1V1UD00

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Chapter 2 V850ES/FG2 Introduction

2.4 Clock Generation Function

The following clock generation functions are available.

• Main clock oscillator

• In clock-through mode

X = 4 to 5 MHz (fXX = 4 to 5 MHz)

• In PLL (Phase Locked Loop) mode f

X = 4 to 5 MHz (fXX = 16 to 20 MHz)

• Subclock oscillator (sub-resonator)

• 32.768 kHz

• 20 kHz (RCR = 390 kΩ, C = 47 pF)

• Multiply (×4) function via PLL (Phase Locked Loop)

• Clock-trough mode/PLL mode selectable

• Ring OSC

R = 100 to 400 kHz

• f

• Internal system clock generation

• 7 steps (f

XX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)

• Peripheral clock generation

• Clock output function

• Programmable clock output (PCL) function

Preliminary User’s Manual U17763EE1V1UD00

Page 40

XT1 XT2

FRC bit

Subclock oscillator

MFRC bit

Main clock

oscillator

Main clock

oscillator

stop control

Software STOP mode

Xtal

1/2 divider

PLLON

bit

PCK1,

PCK0 bit

Chapter 2 V850ES/FG2 Introduction

Figure 2-5: Clock Generator

PLL

Select

oscillator

IDLE mode0, 1

Selector

SELPLL bit

Selector

IDLE

control

IDLE control

IDLE mode 0, 1

Prescaler 3

Prescaler 2

CK2 to CK0 bits

/32

/16

Selector

/2 to fX/2

CK3 bit

Selector

Watch timer clock

Watch timer (WT) clock, CSIB0 clock

Main clock oscillator stop detection

HALT mode

HALT

control

Selector

CPU

CLK

CPU clock

Internal system clock

PCL

CLKOUT

Port CM

Ring-OSC

RSTOP bit

Selector

Prescaler 1

Prescaler 4

1/8 divider

fXX to fXX/1024

X-fX

/1024

Watchdog timer 2 (WDT2) clock

Peripheral clock

Watchdog timer 2 (WDT2)

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2.5 16-bit Ti mer /event Counter P

The V850ES/FG2 includes 16-bit timer/event counter P (TMP0 to TMP3).

Features

Timer P (TMP) is a 16-bit timer/event counter that can be used in various ways. TMP can perform the following operations.

• PWM output

• Interval timer

• External event counter (operation disabled when clock is stopped)

• One-shot pulse output

• Pulse width measurement function

• Timer synchronized operation function

• Free-running function

• External trigger pulse output function

Functional Outline

• Capture trigger input signal × 2

• External trigger input signal × 1

• Clock selection × 8

• External event count input × 1

• Readable counter × 1

• Capture/compare reload regis ter × 2

• Capture/compare match interru pt × 2

• Timer output (TOPn0, TOPn1) × 2

Remark: n = 0 to 3

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Figure 2-6: Figure 6-1. Block Diagram of Timer P

TPnCTL0

TPnCE TPnCKS2 TPnCKS1 TPnCKS0

TPnCE

fXX fXX/2 f

XX/4

XX/8

XX/16 XX/32

fXX/128

XX/64

Note 1 Note 2

Selector

Edge

detector

Chapter 2 V850ES/FG2 Introduction

Internal bus

TPnIOC2

TPnEES1 TPnEES0 TPnETS1 TPnETS0

TPnCCR0

TPnCNT0

Counter control

16-bit counter

CCR0 buffer

Load

Clear

INTTPnCC0

SelectorSelector

TPnCE

INTTPnOV

Edge

detector

TIPn0

Note 3

TIPn1

Note 4

SELCNT0 ISEL04 to ISEL02,

ISEL00

TPnIS3 to TPnIS0 TPnIOC1

detector

Selector Selector

Edge

TPnCTL1

Notes: 1. TMP0, TMP2

2. TMP1, TMP3 (when main clock is stopped, count operation by subclock cannot be per-

formed.)

3. TSOUT signal of CAN0 block (TMP0) RXDA0 pin (TMP1)

Trigger control

TPnSYE TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0

Internal bus

CCR1 buffer

TPnCCR1

Capture/compare selection function

TPnCCS1 TPnCCS0 TPnOVF

TPnOPT0

Load

Output

controller

TPnOL1 TPnOE1 TPnOL0 TPnOE0

TPnIOC0

INTTPnCC1

TOPn0 TOPn1

4. INTTM0EQ0 interrupt of TMM block or TSOUT signal of CAN1 block (TMP0) RXDA1 pin (TMP1)

Remark: n = 0 to 3

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2.6 16-bit Ti mer /event Counter Q

The V850ES/FG2 includes 16- bit tim er /ev ent counte r Q (TMQ0, TMQ1) .

Features

Timer Q (TMQ) is a 16-bit timer/event counter that can be used in various ways. TMQ can perform the following operations.

• PWM output

• Interval timer

• External event counter (operation disabled when clock is stopped)

• One-shot pulse output

• Pulse width measurement function

• Triangular wave PWM output

• Timer synchronized operation function

Functional Outline

• Capture trigger input signal × 4

• External trigger input signal × 1

• Clock selection × 8

• External event count input × 1

• Readable counter × 1

• Capture/compare reload register × 4

• Capture/compare match interrupt × 4

• Timer output (TOQn0 to TOQn3) × 4

Remark: n = 0, 1

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TQnCTL0

TQnCE TQnCKS2 TQnCKS1 TQnCKS0

TQnCE

fXX fXX/2 f

XX/4

XX/8

XX/16 XX/32

XX/64

XX/128

Selector

Chapter 2 V850ES/FG2 Introduction

Figure 2-7: Figure 7-1. Block Diagram of Timer Q

Internal bus

TQnIOC2 TQnEES1 TQnEES0 TQnETS1 TQnETS0

TQnCCR0

TQnCNT0

CCR0 buffer

Load

INTTQnCC0

SelectorSelector

detector

TIQn0

TIQn1

TIQn2

TIQn3

detector

TQnIS7 to TQnIS0

TQnIOC1

Edge

Counter control

Trigger

control

Edge

TQnSYE TQnEST TQnEEE TQnMD2 TQnMD1 TQnMD0

TQnCTL1

Internal bus

16-bit counter

CCR1 buffer

TQnCCR1

16-bit counter

CCR2 buffer

TQnCCR2

16-bit counter

CCR3 buffer

TQnCCR3

Capture/compare selection function

TQnCCS3 to TQnCCS0 TQnOVF

INTTQnOV

TQnCUF

TQnOPT0

Clear

TQnCE

INTTQnOV

Load

INTTQnCC1

INTTQnCC2

Selector

Load

INTTQnCC3

Selector

Output

controller

TOQn0 TOQn1 TOQn2 TOQn3

TQnOL3 to TQnOL0 TQnOE3 to TQnOE0

TQnIOC0

Remark: n = 0, 1

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2.7 16-bit Interval Timer M

The V850ES/FG2 includes 16-bit interval timer M (TMM0).

Features

Timer M (TMM) supports only a cle ar & start mode. It does not support a fre e-running mode . To use timer M in a manner equivalent to in the free-running mode, set the compare register to FFFFH and start the 16-bit counter. A match interrupt will occur when the timer overflows.

• Interval function

• Clock selection × 8

• Simple counter × 1

(The simple counter is a counter that does not use a counter read buffer. This counter cannot be read during timer count operation.)

• Simple compare × 1 (The simple compare register is a register that does not use a compare write buffer. No data can be written to this compare register during timer count operation.)

• Compare match interrupt × 1

TM0CTL0

TM0CE

Figure 2-8: Block Diagram of Timer M

TM0CKS2 TM0CKS1 TM0CKS0

fXX

fXX/2

XX/4

XX/64

XX/512

INTWT

R/8

Selector

Controller

Internal bus

TM0CMP0

16-bit counter

INTTM0EQ0

Clear

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2.8 Watch Timer Functions

Features

The watch timer has the following functions.

• Watch timer

• Interval timer

The watch timer and interval timer functions can be used at the same time.

Figure 2-9: Block Diagram of Watch Timer

Reset

Prescaler

Note

fXT

BRG

Clear

Selector

11-bit prescaler

fW/24fW/25fW/26fW/27fW/28fW/210fW/211fW/2

Selector

Watch timer operation mode register (WTM)

Internal bus

5-bit counter

Clear

Note: For details of prescaler 3, see Figure 2-10 “Block Diagram of Prescaler 3”. Remarks: 1. f

BRG:Prescaler 3 output frequency

2. f

X:Oscillation frequency

INTWT

Selector

INTWTI

WTM0WTM1WTM2WTM3WTM4WTM5WTM6WTM7

3. f

XT:Sub cl oc k freque nc y

4. f

W:Watch timer clock frequency

5. INTWT:Watch timer interrupt

6. INTWTI:Interval timer interrupt

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Figure 2-10: Block Diagram of Prescaler 3

3-bit prescaler

fX/8 f

X/4

X/2 X

fBGCS

Selector

8-bit counter

Match

Output control

fBRG

Remark: f

BGCS00BGCS01BGCE0

BGCS:Prescaler 3 count clock frequency

1. f

BRG:Prescaler 3 output frequency

2. f

X:Oscillation frequency

Prescaler compare register0 (PRSCM0)

Prescaler mode register 0 (PRSM0)

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2.9 Functions of Watchdog T imer 2

Features

Watchdog timer 2 has the following functions.

• Default-start watchdog timer

- →Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal)

- →Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)

• Input selectable from main clock and Ring-OSC as the source clock

Note: Restoring using the RETI instruction follo wing non-maskable interr upt servicing due to a non-

maskable interrupt r equest signal (INTWDT2) is not p ossible. Ther efore, following completion of interrupt servicing, perform a system reset.

Figure 2-11: Block Diagram of Watchdog Timer 2

Note

Watchdog timer enable register (WDTE)

Remarks: 1. f

2. f

3. INTWDT2: Non-maskable interrupt request signal from watchdog timer 2

4. WDT2RES: Watchdog timer 2 reset signal

fX/2

fR/2

X: Oscillation frequency R: Ring-OSC clock frequency

RUN2

Clock

input

controller

16-bit

counter

Clear

WDM21 WDM20

Watchdog timer mode register 2 (WDTM2)

Internal bus

fX/216 to fXX/223,

12 to

fR/2

R/2

Selector

WDCS22

Output

controller

WDCS21WDCS20WDCS23WDCS24

INTWDT2 WDT2RES

(internal reset signal)

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2.10 A/D Converter

Features

The A/D converter converts anal og in put sig nal s in to dig ita l va lue s, has a r eso lu tion of 10 bits, and can handle 16 analog input signal channels (ANI0 to ANI15). The A/D converter has the following features.

• 10-bit reso lu ti o n

• 16 channels

• Successive approximation method

• Operating voltage: AV

• Analog input voltage: 0 V to AV

REF0 = 4.0 to 5.5 V

REF0

• The following functions are provided as operation modes.

• Continuous select mode

• Continuous scan mode

• One-shot scan mode

• The following functions are provided as trigger modes.

• Software trigger mode

• External trigger mode (external, 1)

• Timer trigger mode

• Power-fail monitor function (conversion result compare function)

Figure 2-12: Block Diagram of A/D Converter

ANI0 ANI1 ANI2

: :

ANI13 ANI14 ANI15

Selector

Sample & hold circuit

ADA0CE

bit

SAR

ADA0CE bit

Voltage comparator

D/A converter

REF0

AVSS

INTTP2CC0 INTTP2CC1

ADTRG

ADA0ETS0 bit ADA0ETS1 bit

ADA0CR0

Edge

detection

Controller

ADA0M1 ADA0M2 ADA0S

ADA0M0

Internal bus

ADA0CR1 ADA0CR2

•

ADA0CR13 ADA0CR14 ADA0CR15

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2.1 1 Asynchronous Serial Interface A (UARTA)

The V850ES/FG2 includes asynchronous serial interface A (UARTA).

Features

• Transfer rate: 300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated

baud rate generator)

• Full-duplex communication

- UARTA receive data register n (UAnRX)

- UARTA transmit data register n (UAnTX)

• 2-pin configurationTXDAn:

- Output pin of transmit data

- RXDAn: Input pin of receive data

• Reception error detection function

- Parity error

- Framing er ror

- Overrun error

• Interrupt sources: 2 types

- Reception complete interrupt (INTUAnR): An interrupt is generated in the reception enabled status by ORing three types of reception errors. It is also generated when receive data is transferred from the shift register to receive buffer register n after completion of serial transfer.

- Transmission enable interrupt (INTUAnT): Generated when transmit data is transferred from the transmit buffer register to the shift register in the transmission enabled status.

• Character length of transmit/receive data is specified by the UAnCTL0 register.

• Character length: 7 or 8 bits

• Parity function: Odd, even, 0, none

• Transmission stop bit: 1 or 2 bits

• Dedicated baud rate generator

• MSB/LSB first transfer selectable

• Transmit/receive data reversible

• 13 to 20 bits selectable for SBF (Sync Break Field) transmission in LIN (Local Interconnect

Network) communication format

• 11 or more bits recognizable for SBF reception in LIN communication format

• SBF reception flag

Remark: n = 0 to 2

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INTUAnT

INTUAnR

Chapter 2 V850ES/FG2 Introduction

Figure 2-13: Block Diagram of Asynchronous Serial Interface A

Internal bus

XX to fXX/2

ASCKA0

Clock

Remark: n = 0 to 2

UAnRX

Receive shift

Filter

Selector

selector

UAnCTL1 UAnCTL2

Reception unit Transmission unit

Reception controller

Baud rate generator

Internal bus

Transmission

controller

Baud rate

generator

UAnTX

Transmit

shift register

Selector

UAnOTP0UAnCTL0 UAnSTR

TXDAn

RXDAn

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2.12 3-Wire Serial Interface (CSIB)

The V850ES/FG2 includes a 3-wire serial interface (CSIB).

Features

• Master mode and slave mode selectable

• 3-wire serial interface for 8-bit to 16-bit transfer

• Interrupt request signals (INTCBnT and INTCBnR)

• Serial clock and data phase selectable

• Transfer data length selectable from 8 to 16 bits in 1-bit units

• Data transfer with MSB- or LSB-first selectable

• 3-wireSOBn:

- Serial data output

- SIBn:Serial data input

- SCKBn:Serial clock I/O

• Transmission mode, reception mode, and transmission/reception mode selectable

Remark: n = 0, 1

fXX/2 f

XX/4 XX/8

XX/16 XX/32

XX/64

fBRG (n = 0)

TOP01 (n = 1)

SCKBn

SIBn

Figure 2-14: Block Diagram of 3-Wire Serial Interface

Internal bus

CBnCTL1

Selector

CBnSTR

Controller

Phase control

CBnTX

Shift register

CBnCTL2CBnCTL0

SO latch

Phase

control

INTCBnT INTCBnR

SOBn

Remark: n = 0, 1

CBnRX

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2.13 CAN Controller

This product features an on-chip 2-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The number of channels varies dependin g on the product as shown below.

Features

• Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test)

• S tan dar d frame and extend ed frame tra ns miss io n/rec ept ion enabl ed

• Transfer rate: 1 Mbps max. (CAN clock input ≥ 8 MHz)

• 32 message buffers × 2 channels

• Receive/transmit history list function

• Automatic block transmission function

• Multi-buffer receive block function

• Mask setting of four patterns is possible for each channel

Figure 2-15: Block Diagram of CAN Module

Interrupt request

INTCnTRX INTCnREC INTCnERR

INTCnWUP

CPU

NPB

interface

(NEC peripheral I/O bus)

CAN module

(Memory Access Controller)

CAN RAM

Message

buffer 0

Message

buffer 1 Message

buffer 2 Message

buffer 3

Message buffer 31

NPB

MAC

CnMASK1

CnMASK2

...

CnMASK3

CnMASK4

CAN

protocol

layer

CANTXn

CANRXn

CAN

transceiver

CAN bus

CAN_Hn

CAN_Ln

Remark: n = 0, 1

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2.14 Interrupt/Exception Processing Function

The V850ES/FG2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing. An interrupt is an event that occ urs independ ently of progra m execution, an d an exception is an event whose occurrence is dependent on program execution. The V850ES/FG2 can process interrupt request signals from the on-chip peripheral hardware and external sources. M oreover, exception processing can be s tarted by the TRAP instr uction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap).

Features

• Interrupts

- Non-maskable interrupts:2 sources

- Maskable interrupts: External: 11, Internal: 50 sources

• 8 levels of programmable priorities (maskable interrupts)

• Multiple interrupt control according to priority

• Masks can be specified for each maskable interrupt request

- Noise elimination, edge detection, and valid edge specification for external interrupt request signals

- Exceptions

• Software exceptions: 32 sources

• Exception trap: 2 sources (illegal opcode exception, debug trap)

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2.15 DMA Controller (DMAC)

The V850ES/FG2 inco rporates a direct memory access (DMA) controller (DMAC) that execu tes and controls DMA transfer. The V850ES/FG2 incorporates four independent DMA channels. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests iss ued by the on-chip p eripheral I/O (serial in terface, real-time pu lse unit, and A/D converter), interrupts from external input pin s, or software triggers (m emory refers to intern al RAM or external memory).

Features

• 4 independent DMA channels

• Transfer unit: 8/16 bits

• Maximum transfer count: 65,536 (2

• Transfer type: Two-cycle transfer

• Transfer mode: Single transfer mode

• Transfer re que sts

- Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts from external input pin

- Requests by software trigger

)

• Transfer tar get s

- Peripheral I/O ⇔ Peripheral I/O

- Peripheral I/O ⇔ Internal RAM

Figure 2-16: Block Diagram of DMA Controller

CPU

Internal RAM

Data

control

Channel

Count

control

Internal bus

Address

control

On-chip

peripheral I/O

On-chip peripheral I/O bus

DMA source address register n (DSAnH/DSAnL)

DMA destination address register n (DDAnH/DDAnL)

DMA transfer count register n (DBCn)

DMA channel control register n (DCHCn)

DMA addressing control register n (DADCn)

Remark: n = 0 to 3

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2.16 Key Interrupt Function

Features

A key interrupt request sign al (INTKR) can be generated by inputting a falli ng edge to the eight key input pins (KR0 to KR7) by setting the key return mode register (KRM).

Table 2-5: Assignment of Key Return Detection Pins

Flag Pin Description KRM0 Controls KR0 signal in 1-bit units KRM1 Controls KR1 signal in 1-bit units KRM2 Controls KR2 signal in 1-bit units KRM3 Controls KR3 signal in 1-bit units KRM4 Controls KR4 signal in 1-bit units KRM5 Controls KR5 signal in 1-bit units KRM6 Controls KR6 signal in 1-bit units KRM7 Controls KR7 signal in 1-bit units

KR7 KR6 KR5 KR4 KR3 KR2 KR1 KR0

KRM7

Figure 2-17: Key Return Block Diagram

KRM6

KRM5 KRM4 KRM3 KRM2 KRM1 KRM0

Key return mode register (KRM)

INTKR

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2.17 Standby Function

Overview

The power consumptio n of the sys tem can be effective ly reduced by usi ng the sta ndby m odes in combination and selecting the appropriate mode for the application. The available standby modes are listed below.

Table 2-6: Standby Modes

Mode Functional Outline HALT mode Mode in which only the operating clock of the CPU is stopped

IDLE1 mode

IDLE2 mode Mode in which all the internal operations of the chip except the oscillator are stopped Software STOP mode Subclock operation

mode

Sub-IDLE mode

Mode in which all the internal operations of the chip except the oscillator, PLL flash memory are stopped

Mode in which all the in ternal o peratio ns of the c hip ex cept the subcl ock os cill ator are stopped

Mode in which the subclock is used as the internal system clock

Mode in which all the internal operations of the chip except the oscillator, PLL flash memory are stopped, in the subclock operation mode

, and

a. The PLL holds the previous operating status (in clock-through mode or PLL mode).

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2.18 Reset Function

The reset function is outlined below.

• Reset function by RESET pin input

• Reset function by overflow of watchdog timer 2 (WDT2RES)

• System reset by low voltage detector (LVI)

• System reset by clock monitor (CLM)

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2.19 Clock Monitor

The clock monitor samples the main clock by using the on-chip Ring-OSC and generates a reset request signal when oscillation of the main clock is stopped. Once the operation o f the clock monitor has been enabled by an operation enab le flag, it cannot be cleared to 0 by any means other than reset. The clock monitor automatically stops under the following conditions.

• While oscillation stabilization time is being counted after software STOP mode is released

• When the main clock is stopped (MCK bit of the PCC register = 1 during subclock operation, or

CLS bit of the PCC register = 0 during main clock operation)

• When the sampling clock is stopped (Ring-OSC)

• When the CPU operates with Ring-OSC

Figure 2-18: CLM Block Diagram

Main clock

Ring-OSC clock

Internal reset signal

Enable/disable

CLME

Clock monitor mode register (CLM)

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2.20 Low-voltage Detector

Features

The low-voltage detector (LVI) has the following functions.

• Compares the supply voltage (V interrupt signal or internal reset signal when V

DD) and detected voltage (VLVII) and generates an internal

DD < VLVI.

• The level of the supply voltage to be detected can be changed by software (in two steps).

• Interrupt or reset signal can be selected by software.

• Can operate in STOP mode too.

• Operation can be stopped by software.

If the low-voltage detec tor is us ed to g ene rate a r es et si gna l, bit 0 ( LVIRF) of the reset source fla g r eg ister (RESF) is set to 1 when the reset signal is generated.

Figure 2-19: Block Diagram of Low-Voltage Detector

VDD

Low

voltage

detection

level

selector

Detected voltage

N-ch

source (V

LVI )

Internal reset signal

−

Selector

INTLVI

LVIS0

Low voltage detection level selection register (LVIS)

Internal bus

LVION

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LVIF

Low voltage detection register (LVIM)

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2.21 Voltage Regulator

Features

This product has an on-chip regulator to lower the power consumption and noise. This regulator supplie s a voltage lower than the su pply voltage V logic circuits (except the A/D converter and I/O buffers). The output voltage of the regulator is set to 2.5 V (±0.2 V).

Figure 2-20: Regulator

I/O buffer

REF0

A/D converter

4.0 to 5.5 V

BV (normal port)

3.5 to 5.5 V

DD to the oscillator block an d internal

REGC

Regulator

Main and sub

oscillators

Flash

memory

Internal digital circuit

2.5 V

EVDD I/O buffer (normal port)

3.5 to 5.5 V

Bidirectional level shifter

The regulator of this p roduct operates i n all operation modes (norma l operation, HALT, ID LE1, IDLE2, STOP, and sub-IDLE modes, and during reset).

To stabilize the output voltage of the regulator, connect a capacitor (4.7 µF

Note

) to the REGC pin.

Note: Connect the REGC pin as illustrated below.

Figure 2-21: Connection of REGC Pin (REGC = Capacitance)

4.7 F

VDD

REGC

REG

Supply voltage to oscillators/internal logi

2.5 V

Input voltage

3.5 to 5.5 V

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2.22 Flash Memory

The following products are flash memory versions of the V850ES/FG2.

Caution: There are differences in the amount of noise tolerance and noise radiation between

flash memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM ve rsion during th e process from exper imental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.

µPD70F3235 On-chip 256 KB flash memory

When fetching an instruction, 4 bytes of the flash memory can be accessed in 1 clock in the same manner as the mask ROM versions. The flash memory can be written m ounted on th e target b oard (on- board write ), by conne cting a d edicated flash programmer to the target system. Flash memory is commonly used in the following development environments and applications.

• For altering software after solder-mounting the V850ES/FG2 on the target system

• For differentiat ing software in small-sca le production of various models.

• For data adjustment when starting mass production

Features

• 4-byte/1-clock access (for instruction fetch access)

• Batch erase or block unit erase

• Communication with dedicated flash programmer via serial interface

• Erase/write voltage: Can be erased or written using a single power supply.

• On-board programming

• Flash memory programming by self writing

Erasure unit

The units in which the 256 or 384 KB flash memory can be erased are as follows.

(1)Batch erasure

The areas of flash memory xx000000H to xx03FFFFH, and xx000000H to xx05FFFFH can be erased at the same time.

(2)Block erasure

Note

The flash memory can be erased in block units

. Block 0:56 KB Block 1:8 KB Block 2:56 KB Block 3:8 KB Block 4:56 KB Block 5:56 KB Block 6:8 KB Block 7:8 KB Block 8:32 KB Block 9:32 KB Block 10:32 KB Block 11:32 KB

Note: 8 blocks, blocks 0 to 7, for the 256 KB version (µPD70F3235).

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2.23 ROM Mask Options Function

Mask Options (Flash ROM Product)

The flash memory ver sions in this product series have a n option data area where a block s ubject to mask options is specified. When writing a program to a fl as h mem ory v ers ion , be s ure to s et the opti on d ata c orr esp ond ing to the following option in the program at address 007AH as default data. The data in this area cannot be rewritten during program execution.

Table 2-7: Mask Options

Address Set Value Setting 007AH

00H

01H

02H

03H

C0H

C1H

C2H

C3H

Ring-OSC:Can be stopped. WDT2:Count clock can be selected. Overflow signal can be selected from INTWDT2 or WDT2RES. Subclock:Crystal resonator connection

Ring-OSC:Cannot be stopped. WDT2:Count clock can be selected. Overflow signal can be selected from INTWDT2 or WDT2RES. Subclock:Crystal resonator connection

Ring-OSC:Can be stopped. WDT2:Count clock is fixed to Ring-OSC. Overflow signal is fixed to WDT2RES. Subclock:Crystal resonator connection

Ring-OSC:Cannot be stopped. WDT2:Count clock is fixed to Ring-OSC. Overflow signal is fixed to WDT2RES. Subclock:Crystal resonator connection

Ring-OSC:Can be stopped. WDT2:Count clock can be selected. Overflow signal can be selected from INTWDT2 or WDT2RES. Subclock:RC oscillation connection

Ring-OSC:Cannot be stopped. WDT2:Count clock can be selected. Overflow signal can be selected from INTWDT2 or WDT2RES. Subclock:RC oscillation connection

Ring-OSC:Can be stopped. WDT2:Count clock is fixed to Ring-OSC. Overflow signal is fixed to WDT2RES. Subclock:RC oscillation connection

Ring-OSC:Cannot be stopped. WDT2:Count clock is fixed to Ring-OSC. Overflow signal is fixed to WDT2RES. Subclock:RC oscillation connection

Caution: Do not make any settings other than the above.

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Chapter 2 V850ES/FG2 Introduction

2.24 On-chip Debug Unit (Flash Memory Versions only)

The V850ES/FG2 i nclud es a n on-c hip d ebug u nit. By connect ing an N-Wire em ulator, on-chip de bugging can be executed with the V850ES/FG2 alone.

Caution: The following debug functions are supported by the V850ES/FG2, and whether they

are usable or not differs depending on the debugger. For details of the debugging function, refer to the user’s manual of the debugger to be used.

Functional Outline

The on-chip debug unit of the V850ES/FG2 is RCU1 (Run Control Unit 1).

Debug interface

Communication with the host mac hine is established by using the DRST, DCK, DMS, DDI, and DDO signals via an N-Wire emulator. The communication specifications of N-Wire are used for the interface.

On-chip debug

On-chip debugging can b e exec uted by prepar i ng wir ing and a con nec to r for o n-ch ip d ebug gi ng on the target system. An N-Wire emulator is used as the connector that connects the emulator. Clear the OCDM0 bit of the OCDM register (special register) to 0 when you use on-chip debug mode.

Forced reset function

The V850ES/FG2 can be forcibly reset.

Break reset function

The CPU can be started in the debug mode immediately after reset of the CPU is released.

Forced br ea k function

Execution of the use r program can be for cibly aborted (howev er, the illegal operation code exce ption handler (first address: 00000060H) cannot be used).

Hardware break function

Two breakpoints for instruction and access can be used. The instruction breakpoint can abort program execution at any add ress . The acce ss br eakp oint can ab ort prog ram e xecut ion b y data acce ss t o any address.

Software break function

Up to four software b reakpoints can be set in the internal R OM area. T he number of s oftware break points that can be set in the RAM area differs depending on the debugger to be used.

Debug monitor function

A memory space for debugging that is different fr om the user me mor y s pac e i s us ed dur ing debugging (background monitor mode). The user program can be executed starting from any address. While execution of the user program is aborted, the user resources ( such as memory and I/O ) can be read and written, and the user program can be downloaded.

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Chapter 2 V850ES/FG2 Introduction

Mask function

Each signal can be masked. The correspondence with the mask functions of the debugger (ID850NWC) for the N-Wire emulator (IEV850E1-CD-NW) of NEC Electronics is shown below.

• NMI0 mask function:NMI pin

• N MI1 mas k function:WDT2 int er rupt

• N MI2 mas k function:–

• RESET mask function:RESET pin, WDT2 reset, LVI reset, clock monitor reset

Timer function

The execution time of the user program can be measured.

Peripheral macro operation/stop selection function during break

Depending on the de bugger to be used, whether t he peripher al ma cro ope rates or is s topped durin g a break can be selected.

Functions that are always stopped during break

• Clock monitor

• Watchdog timer 2

Functions that can operate or be stopped during break (however, each function cannot be selected individually)

• A/D converter

• Timer M

• Timer P

• Timer Q

• Watch timer

Peripheral functions that continue operating during break (functions that cannot be stopped)

• P er ipher al func tio ns othe r than above

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Chapter 3 Pin Function of MTRC

3.1 Pin Configuration (Top View)

Figure 3-1: Pinout of MTRC

SMVSS3

SMVDD3 PMT27/SM64 PMT26/SM63

PMT25/SM62 PMT24/SM61

PMT23/SM54 PMT22/SM53 PMT21/SM52 PMT20/SM51

PMT43/EXCLO

CLK

MTCS

MTRESET

MTV

SS1

MTVDD1

MTVDD2

SCK

PMT36

PMT37

PMT34

PMT35

PMT32

PMT33

PMT30

PMT31

SMVSS2 SMVDD2 PMT17/SM44

PMT16/SM43 PMT15/SM42

PMT14/SM41 PMT13/SM34

PMT12/SM33 PMT11/SM32 PMT10/SM31 SM24 SM23 SM22 SM21 SM14 SM13

SM12 SM11 SMV

DD1

SMVSS1

PMT03

PMT01

PMT02

PMT00

PMT40/EXSI1

PMT41/EXSO1

PMT42/EXSCK1

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Chapter 3 Pin Function of MTRC

3.2 List of Pin Functions

Table 3-1: List of Pin Functions (1/2)

Symbol IO Function Connection PMT00 IO I/O Port External PMT01 IO I/O Port External PMT02 IO I/O Port External PMT03 IO I/O Port External SM11 O - Hi-Z Meter1 PWM Output Signal (sin+) External SM12 O - Hi-Z Meter1 PWM Output Signal (sin-) External SM13 O - Hi-Z Meter1 PWM Output Signal (cos+) External SM14 O - Hi-Z Meter1 PWM Output Signal (cos-) External SM21 O - Hi-Z Meter2 PWM Output Signal (sin+) External SM22 O - Hi-Z Meter2 PWM Output Signal (sin-) External SM23 O - Hi-Z Meter2 PWM Output Signal (cos+) External SM24 O - Hi-Z Meter2 PWM Output Signal (cos-) External PMT10/SM31 O - Hi-Z / O Output Port / Meter3 PWM Output Signal (sin+) External PMT11/SM32 O - Hi-Z / O Output Port / Meter3 PWM Output Signal (sin-) External PMT12/SM33 O - Hi-Z / O Output Port / Meter3 PWM Output Signal (cos+) External PMT13/SM34 O - Hi-Z / O Output Port / Meter3 PWM Output Signal (cos-) External PMT14/SM41 O - Hi-Z / O Output Port / Meter4 PWM Output Signal (sin+) External PMT15/SM42 O - Hi-Z / O Output Port / Meter4 PWM Output Signal (sin-) External PMT16/SM43 O - Hi-Z / O Output Port / Meter4 PWM Output Signal (cos+) External PMT17/SM44 O - Hi-Z / O Output Port / Meter4 PWM Output Signal (cos-) External PMT20/SM51 O - Hi-Z / O Output Port / Meter5 PWM Output Signal (sin+) External PMT21/SM52 O - Hi-Z / O Output Port / Meter5 PWM Output Signal (sin-) External PMT22/SM53 O - Hi-Z / O Output Port / Meter5 PWM Output Signal (cos+) External PMT23/SM54 O - Hi-Z / O Output Port / Meter5 PWM Output Signal (cos-) External PMT24/SM61 O - Hi-Z / O Output Port / Meter6 PWM Output Signal (sin+) External PMT25/SM62 O - Hi-Z / O Output Port / Meter6 PWM Output Signal (sin-) External PMT26/SM63 O - Hi-Z / O Output Port / Meter6 PWM Output Signal (cos+) External PMT27/SM64 O - Hi-Z / O Output Port / Meter6 PWM Output Signal (cos-) External PMT30 IO I/O Port External PMT31 IO I/O Port External PMT32 IO I/O Port External PMT33 IO I/O Port External

Note 1

PMT34

Note 1

PMT35

Note 2

PMT36

Note 2

PMT37 PMT40/EXSI1 IO/I I/O Port / Expand Pin for SI External PMT41/EXSO1 IO/O I/O Port / Expand Pin for SO External

IO I/O Port External IO I/O Port External IO I/O Port External IO I/O Port External

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Chapter 3 Pin Function of MTRC

Table 3-1: List of Pin Functions (2/2)

Symbol IO Function Connection PMT42/EXSCK1 PMT43/EXCLO IO/O I/O Port / Expand Pin for System Clock External SMVDD1 Power Supply Input Voltage for Meter1, Meter2 External SMVSS1 Ground Potential for Meter1, Meter2 External SMVDD2 Power Supply Input Voltage for Meter3, Meter4 External SMVSS2 Ground Potential for Meter3, Meter4 External SMVDD3 Power Supply Input Voltage for Meter5, Meter6 External SMVSS3 Ground Potential for Meter5, Meter6 External

CLK I System Cl ock Input

CS I Serial Access Enable

MTCS

MTRESET MTVSS Ground Potential (Digital Unit) External MTVDD Power Supply Input Voltage (Digital Unit) External

SCK

SI I Serial Data Input

SO O Serial Data Output

IO/O I/O Port / Expand Pin for SCK External

Internal to

FG2

Internal to

FG2

At DJ2 device shared with PCM0/WAIT pin of FG2 device (PCM0 has to be configured to output for intern al communication)

I Reset Input External

I Serial Clock Input

Internal to

FG2

Internal to

FG2

Internal to

FG2

Notes: 1. Set PMT3n = “0” (Port output = 0) and PMMT3n = “1” (Input mode)

2. Not used at D_Line (n = 6,7)

set PMT3n = “0” (Port output = 0) and PMMT3n = “1” (Input mode)

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Chapter 3 Pin Function of MTRC

Table 3-2: List of Pin Functions (1/2)

Symbol Alternate Function I/O Circuit Recommended connection

PMT00

PMT01

A-1

PMT02

PMT03 SM11

SM12 Leave open SM13 Leave open SM14 Leave open SM21 Leave open

B-1

SM22 Leave open SM23 Leave open SM24 Leave open

PMT10/SM31

PMT11/SM32

PMT12/SM33

PMT13/SM34

PMT14/SM41

PMT15/SM42

PMT16/SM43

PMT17/SM44

PMT20/SM51

PMT21/SM52

PMT22/SM53

PMT23/SM54

PMT24/SM61

PMT25/SM62

PMT26/SM63

PMT27/SM64

Meter3 PWM Output Signal (sin+)

Meter3 PWM Output Signal (sin-)

Meter3 PWM Output Signal (cos+)

Meter3 PWM Output Signal (cos-)

Meter4 PWM Output Signal (sin+)

Meter4 PWM Output Signal (sin-)

Meter4 PWM Output Signal (cos+)

Meter4 PWM Output Signal (cos-)

Meter5 PWM Output Signal (sin+)

Meter5 PWM Output Signal (sin-)

Meter5 PWM Output Signal (cos+)

Meter5 PWM Output Signal (cos-)

Meter6 PWM Output Signal (sin+)

Meter6 PWM Output Signal (sin-)

Meter6 PWM Output Signal (cos+)

Meter6 PWM Output Signal (cos-)

B-2

Input: Independently c onn ec t to M TV Output: Leave open

Leave open

or MTVSS via a resist or

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Chapter 3 Pin Function of MTRC

Table 3-2: List of Pin Functions (2/2)

Symbol Alternate Function I/O Circuit Recommended connection

PMT30

PMT31

PMT32

PMT33

A-1

Note 1

PMT34

Note 1

PMT35

Note 1

PMT36

Note 1

PMT37

PMT40/EXSI1 Expand Pin for SI D-2

PMT41/EXSO1 Expand Pin for SO D-1 PMT42/

EXSCK1 PMT43/EXCLO

Expand Pin for SCK

Expand Pin for System Clock

D-3

D-4

SMVDD1 SMVSS1 SMVDD2 SMVSS2 SMVDD3 SMVSS3 -

CLK MTCS

MTRESET MTV

MTV

SCK SI

CLK

MTCS

SCK

Note 2

SO SO internal connected IC1, IC2 -

Input: Independentl y con nec t to MTV Output: Leave open

Input: Independentl y con nec t to MTVDD or MTVSS via a resistor Output: Leave open

Input: Independentl y con nec t to MTV Output: Leave open

internal connected

Note 2

internal connected

internal connected internal connected

Input: connect to MTVSS directly

or MTVSS via a resistor

Notes: 1. If not connected to the pinout of the DJ2 device, this port has to be s et to outpu t mode and

“0”.

2. Some input pins of t he M TRC h as go t pu ll down/pull up resistors to av oid no is e e ffects that could cause malfunction during the initialization of the FG2 device. After MTRESET release, this resistors are active. The resistors will be deactivated after the first rising edge of the MTCS signal. They will be reactivated if MTRES = “0”. Therefore these resistors consumpt some currents when they’re activated.

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Chapter 3 Pin Function of MTRC

3.3 Pin I/O Circuits

Each type of port block diagram is as follows. Then, the type of each port is shown in each chapter.

3.3.1 Type A-1

Figure 3-2: Type A-1

PMMT

PMMTmn

PMT

PMTmn

3.3.2 Type B-1

SM12MC

SM11 - SM14

SM21 - SM24

Selector

Address

Selector

Figure 3-3: Type B-1

SM12MC

SM11 - SM14 SM21 - SM24

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3.3.3 Type B-2

Chapter 3 Pin Function of MTRC

Figure 3-4: Type B-2

PMCMT

PMCMTmn

PMMT

PMMTmn

PMT

PMTmn

SM31 - SM34 SM41 - SM44 SM51 - SM54 SM61 - SM64

Selector

Address

PMTmn

3.3.4 Type D-1

PMCMT

PMMT

PMT

PMCMT41

EXSO1

PMMT41

PMT41

Figure 3-5: Type D-1

Selector

Address

Selector

PMT41/EXSO1

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3.3.5 Type D-2

PMCMT

PMMT

PMT

Chapter 3 Pin Function of MTRC

Figure 3-6: Type D-2

PMCMT40

PMMT40

PMT40

PMT40/EXSI

3.3.6 Type D-3

PMCMT

PMMT

PMT

EXSCK1

PMCMT42

PMMT42

PMT42

Selector

Address

EXSI1

Selector

Figure 3-7: Type D-3

Selector

PMT42/EXSCK1

Selector

Address

Selector

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3.3.7 Type D-4

PMCMT

PMMT

PMT

Chapter 3 Pin Function of MTRC

Figure 3-8: Type D-4

PMCMT43

PMMT43

PMT43

EXCLO

Selector

PMT43/EXCLO

3.3.8 Type CLK

3.3.9 Type MTCS

Selector

Address

Figure 3-9: Type CLK

CLK

pull-down enable

Selector

CLK

N-ch

Figure 3-10: Type MTCS

MTCS

pull-down enable

MTCS

N-ch

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3.3.10 Type SCK

Chapter 3 Pin Function of MTRC

Figure 3-11: Type SCK

3.3.11 Type SI

3.3.12 Type SO

pull-up disable

SCK

Figure 3-12: Type SI

pull-down enable

P-ch

SCK

N-ch

Figure 3-13: Type SO

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Chapter 4 Port Functions

4.1 Setting Alternate Pin Functions

Set “1” to the PMCmn bit of PMCm register to set the pin to the alternate pin function. Refer to the following table for setting the alternate pin function for every port pin. Not any port provides alternate pin function and therefore this registers has no PMCMTmn register. Please refer to the peripheral function chapter to get more details.

Remark: m = 1, 2, 4

n = 0 to 7

Table 4-1: Alternate Pin Functions (1/2)

Port name

PMT00 PMT01 PMT02 PMT03 PMT10 SM31 PMT11 SM32 PMT12 SM33 PMT13 SM34 PMT14 SM41 PMT15 SM42 PMT16 SM43 PMT17 SM44 PMT20 SM51 PMT21 SM52 PMT22 SM53 PMT23 SM54 PMT24 SM61 PMT25 SM62 PMT26 SM63 PMT27 SM64 PMT30 PMT31 PMT32 PMT33 PMT34 PMT35 PMT36 PMT37

Alternate pin name

Note 1 Note 1 Note 1 Note 1

Note 1

Notes 1, 2

Note 3

Setting value when selecting alternate function

PMTmn PMMTmn PMCMTmn Remark

0/1 1 -

0/1 0/1 1

0/1 1 -

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Chapter 4 Port Functions

Table 4-1: Alternate Pin Functions (2/2)

Port name

PMT40 EXSI1 PMT41 EXSO1 PMT42 EXSCK1 PMT43 EXCLO

Alternate pin name

PMTmn PMMTmn PMCMTmn Remark

0/1 0/1 1

Setting value when selecting alternate function

Connect to SO only if MTCS = “0” Connect to SI only if MTCS = “0” Connect to _SCK only if MTCS =”0” Connect to CLK only if MTCS =”0”

Notes: 1. PMT00-PMT03 and PMT30-PMT35 haven’t got an alternate function

2. PMT34 and PMT35 are not available at DJ2

3. PMT36-PMT37 are not connected to the pinout of the D_Line.

4. The external MTCS pin signal is identical with the internal PCM0 signal.

But the switch to the alternate EXCSI1 fu nc tio n c an be del ay ed. Be ca us e th e i nte rnal ly l ast transferred byte will be finished before the alternate EXCSI1 function will be activated, even if the PCM0/MTCS pin signal is “0”. Tis has to be regarded if an external component has been connected to the EXCSI1.

Note 4

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4.2 Port MT0

4.2.1 Port MT0 functions

• 4-bit I/O Port

• Port I/O data specified in 1-bit units

Chapter 4 Port Functions

Table 4-2: Port MT0 Functions

Port Mode Alternate Function TYPE

PMT00 - A-1 × × PMT01 - A-1 × × PMT02 - A-1 × × PMT03 - A-1 × × -

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not avail abl e

PORT PM PMC

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Chapter 4 Port Functions

4.2.2 Register (1) Port Register 0 (PMT0)

MTRC Port register 0 (MT0) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit.

Figure 4-1: Port Register 0 (PMT0) Format

76543210Address

PMT00000PMT03PMT02PMT01PMT000x20undefined

R/W R R R R R/W R/W R/W R/W

PMT0n Output data control (n= 0 - 3)

0Output 0 1Output 1

Initial value

(2) Port MT0 Mode Register 0 (PMMT0)

This is an 8-bit register used to specify the input mode/output mode. It can be read and written in 8-bit unit.

Figure 4-2: Port MT0 Mode Register 0 (PMMT0) Format

76543210Address

PMMT01111PMMT03PMMT02PMMT01PMMT000x250xFF

R/W R R R R R/W R/W R/W R/W

PMMT0n I/O mode control (n= 0 - 3)

0 Output mode 1 Input mode

Preliminary User’s Manual U17763EE1V1UD00

Initial value

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Chapter 4 Port Functions

4.3 Port MT1

4.3.1 Port MT1 functions

• 8-bit output port

• Port I/O specified in 1-bit units (PMMT1 register)

• Port mode/control mode (alternate function) specified in 1-bit units (PMCMT1 register)

Table 4-3: Port MT1 Functions

Port Mode Alternate Function TYPE

PMT10 SM31 B-2 × × × PMT11 SM32 B-2 × × × PMT12 SM33 B-2 × × × PMT13 SM34 B-2 × × × PMT14 SM41 B-2 × × × PMT15 SM42 B-2 × × × PMT16 SM43 B-2 × × × PMT17 SM44 B-2 × × ×

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not avail abl e

PORT PM PMC

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Chapter 4 Port Functions

4.3.2 Registers (1) Port Register 1 (PMT1)

MTRC Port register 1 (MT1) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit.

Figure 4-3: Port Register 1 (PMT1) Format

76543210Address

PMT1 PMT17 PMT16 PMT15 PMT14 PMT13 PMT12 PMT11 PMT10 0x21 undefined

R/W R/W R/W R/W R/W R/W R/W R/W R/W

PMT1n Output data control (n= 0 - 7)

0Output 0 1Output 1

Initial value

(2) Port Mode Register 1 (PMMT1)

It can be read and written in 8-bit unit.

Figure 4-4: Port Mode Register 1 (PMMT1) Format

76543210Address

PMMT1 PMMT17PMMT16 PMMT15 PMMT14 PMMT13 PMMT12 PMMT11PMMT10 0x26 0xFF

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

PMMT1n I/O mode control (n= 0 - 7)

0 Output mode 1 Input mode

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Chapter 4 Port Functions

(3) Port Mode Control Register (PMCMT1)

It can be read and written in 8-bit unit.

Figure 4-5: Port Mode Control Register 1 (PMCMT1) Format

76543210Address

PMCMT1 PMCMT17PMCMT16PMCMT15PMCMT14PMCMT13PMCMT12 PMCMT11PMCMT10 0x2A 0x00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

PMCMT1n PMMT1n PMCMTn mode control (n = 0 - 7)

0 0 Output port 0 1 Hi-Z output

SM44 output (n = 7) SM43 output (n = 6) SM42 output (n = 5)

SM41 output (n = 4) SM34 output (n = 3) SM33 output (n = 2) SM32 output (n = 1) SM31 output (n = 0)

Initial value

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Chapter 4 Port Functions

4.4 Port SM1/SM2

4.4.1 Port SM1/SM2 functions

• 8-bit output port

• Port mode/control mode (Hi-Z output as alternate function) specified in 1-bit units (SM12MC

Table 4-4: Port MT2 Functions

Port Mode Alternate Function TYPE

Hi-Z SM11 B-1 - - × Hi-Z SM12 B-1 - - × Hi-Z SM13 B-1 - - × Hi-Z SM14 B-1 - - × Hi-Z SM21 B-1 - - × Hi-Z SM22 B-1 - - × Hi-Z SM23 B-1 - - × Hi-Z SM24 B-1 - - ×

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not available

(1) SM1SM2 Mode Control Register (SM12MC)

It can be read and written in 8-bit unit.

PORT PM PMC

Figure 4-6: SM1SM2 Mode Control Register (SM12MC) Format

76543210Address

SM12MC SM24HZCSM23HZCSM22HZCSM21HZCSM14HZCSM13HZCSM12HZCSM11HZC 0x2D 0x00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

SMmnHZC Output data control (m = 1, 2 and n = 1 - 4)

0 Hi-Z output 1 SMmn output

Initial value

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Chapter 4 Port Functions

4.5 Port MT2

4.5.1 Port MT2 functions

• 8-bit output port

• Port mode/control mode (alternate function) specified in 1-bit units (PMCMT2 register)

• Hi-Z output controllable in 1-bit units (PMMT2, PMCMT2 register)

Table 4-5: Port MT2 Functions

Port Mode Alternate Function TYPE

PMT20 SM51 B-2 × × × PMT21 SM52 B-2 × × × PMT22 SM53 B-2 × × × PMT23 SM54 B-2 × × × PMT24 SM61 B-2 × × × PMT25 SM62 B-2 × × × PMT26 SM63 B-2 × × × PMT27 SM64 B-2 × × ×

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not avail abl e

PORT PM PMC

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Chapter 4 Port Functions

4.5.2 Registers (1) Port Register 2 (PMT2)

MTRC Port register 2 (MT2) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit.

Figure 4-7: Port Register 2 (PMT2) Format

76543210Address

PMT2 PMT27 PMT26 PMT25 PMT24 PMT23 PMT22 PMT21 PMT20 0x22 undefined

R/W R/W R/W R/W R/W R/W R/W R/W R/W

PMT2n Output data control (n= 0 - 7)

0Output 0 1Output 1

Initial value

(2) Port Mode Register 2 (PMMT2)

It can be read and written in 8-bit unit.

Figure 4-8: Port Mode Register 2 (PMMT2) Format

76543210Address

PMMT2 PMMT27PMMT26 PMMT25 PMMT24 PMMT23 PMMT22PMMT21PMMT20 0x27 0xFF

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

PMMT2n I/O mode control (n= 0 - 7)

0 Output mode 1 Input mode

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Chapter 4 Port Functions

(3) Port Mode Control Register 2 (PMCMT2)

It can be read and written in 8-bit unit.

Figure 4-9: Port Mode Control Register 2 (PMCMT2) Format

76543210Address

PMCMT2 PMCMT27PMCMT26PMCMT25PMCMT24PMCMT23PMCMT22PMCMT21PMCMT20 0x2B 0x00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

PMCMT2n PMMT2n PMCMTn mode control (n = 0 - 7)

0 0 Output port 0 1 Hi-Z output

SM64 output (n = 7) SM63 output (n = 6) SM62 output (n = 5)

SM61 output (n = 4) SM54 output (n = 3) SM53 output (n = 2) SM52 output (n = 1) SM51 output (n = 0)

Initial value

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Chapter 4 Port Functions

4.6 Port MT3

Caution: Some ports of are not connected to the D_Line pinout, therefore for at DJ2 n = 0 to 3

has effects only.

4.6.1 Port MT3 functions

• 8 -b it I/O port

• Port I/O specified in 1-bit units

Table 4-6: Port MT3 Functions

Port Mode Alternate Function TYPE

PMT30 - A-1 × × PMT31 - A-1 × × PMT32 - A-1 × × PMT33 - A-1 × × -

Note

PMT34

Note

PMT35

Note

PMT36

Note

PMT37

Note: n = 0 to 3

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not available

PORT PM PMC

-A-1××-

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Chapter 4 Port Functions

4.6.2 Registers (1) Port Register 3 (PMT3)

MTRC Port register 3 (MT3) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit.

Figure 4-10: Port Register 3 (PMT3) Format

76543210Address

PMT3 PMT37 PMT36 PMT35 PMT34 PMT33 PMT32 PMT31 PMT30 0x23 undefined

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note

PMT3n

0Output 0 1Output 1

Output data control (n= 0 - 7)

Initial value

Note: at DJ2 n = 0 to 3:

(n = 4, 5) at DJ2 set PMT3n = “0” (Port output = 0) (n = 6, 7) set PMT3n = “0” (Port output = 0)

(2) Port Mode Control Register 3 (PMMT3)

It can be read and written in 8-bit unit.

Figure 4-11: Port Mode Control Register 3 (PMMT3) Format

76543210Address

PMMT3 PMMT37PMMT36 PMMT35 PMMT34 PMMT33 PMMT32 PMMT31PMMT30 0x28 0xFF

R/W R/W R/W R/W R/W R/W R/W R/W R/W

PMMT3n

Note

0 Output mode 1 Input mode

I/O mode control (n= 0 - 7)

Initial value

Note: at DJ2 n = 0 to 3:

(n = 4, 5) at DJ2 set PMMT3n = “1” (Input mode) (n = 6, 7) set PMMT3n = “1” (Input mode)

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Chapter 4 Port Functions

4.7 Port MT4

4.7.1 Port MT4 functions

• 4 -b it I/O port

• Port I/O specified in 1-bit units (PMMT4 register)

• Port mode/control mode (alternate function) specified in 1-bit units (PMCMT4 register)

Table 4-7: Port MT4 Functions

Port Mode Alternate Function TYPE

PMT40 EXSI1 D-2 × × × PMT41 EXSO1 D-1 × × × PMT42 EXSCK1 PMT43 EXCLO D-4 × × ×

Remarks: 1. PORT: Port

PM: Port mode register PMC: Port mode control register PFC: Port function control register

2. ×: available

-: not available

PORT PM PMC

D-3×××

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4.7.2 Registers (1) Port Register 4 (PMT4)

MTRC Port register 4 (MT4) is an 8-bit register that controls pin level read, output level write. It can be read and written in 8-bit unit.

Figure 4-12: Port Register 4 (PMT4) Format

76543210Address

PMT4 0 0 0 0 PMT43 PMT42 PMT41 PMT40 0x24 undefined

R/WRRRRR/WR/WR/WR/W

PMT4n Output data control (n= 0 - 3)

0Output 0 1Output 1

Initial value

(2) Port Mode Register 4 (PMMT4)

It can be read and written in 8-bit unit.

Figure 4-13: Port Mode Register 4 (PMMT4) Format

76543210Address

PMMT4 1 1 1 1 PMMT43PMMT42PMMT41PMMT40 0x29 0xFF

R/WRRRRR/WR/WR/WR/W

Initial value

PMMT4n Output data control (n= 0 - 3)

0 Output mode 1 Input mode

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Chapter 4 Port Functions

(3) Port Mode Control Register 4 (PMCMT4)

It can be read and written in 8-bit unit.

Figure 4-14: Port Mode Control Register 4 (PMCMT4) Format

7654 3 2 1 0Address

PMCMT40000PMCMT43PMCMT42PMCMT41PMCMT400x2C0x00

R/WRRRRR/WR/WR/WR/W

PMCMT43 PMCMT43 mode control

0 I/O port 1 E XCLO output

PMCMT42 PMCMT42 mode control

0 I/O port 1

PMCMT41 PMCMT41 mode control

0 I/O port 1

EXSCK1

EXSO1 output

output

Note

Initial value

PMCMT40 PMCMT40 mode control

0 I/O port 1

EXSI1 Input

Note

Note: The alternate function is only available if MTCS = “0”.

When MTCS = “1”, each I/O status is as follows.

Pin name Status

EXSCK1 “H” level output

EXSO1 “L” level output

EXSI1 Input disabled

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Chapter 5 Clock Generator

5.1 Ring Oscillator

To support a high frequency clock source for the MTRC an internal high speed Ring Oscillator is implemented in the MTRC. This R ing Oscillator is controll ed with SFRs to realize sto p, restart and calibration.

After the release of the MTR ESET the MTCS signal will be set from “0” to “1”.

Remark: For mass production tests the MTRC can be clocked alternatively direct from the FG2

device via the CLKO UT pi n. T his pi n i s inte rn ally c onne ct ed w ith the CLK pi n o f the MTRC. Due to EME reason this mode is not useful for real applications.

5.1.1 Autocalibration function

At the first sta rt o f the ring oscillator i t is uncalibrated and t her efo re si gni fic an t d ev iat ion s from i ts b asi c frequency (8 MHz) could be possible. The Ring Oscillato r Unit s upplies an autoca libration function. Wi th 5 spe cified cal ibration pulses at the CS pin of the MTRC (therefore PCM0/WAIT pin at the FG2) direct after MTRES release, the Ring Oscillator self-calibratio n unit adj us ts the fre que nc y iterat iv ely. The calculated calib ration factor is stored in the MRCAL regis ter. This register controls the cal ibration unit of the Ring Oscillator to set its frequency to 8 MHz.

5.1.2 Ring Oscillator states

With the Ring Oscillator 3 different states have to be separated:

• C ali br ati on Mod e

pin the Ring Oscillator is sto pped. It will be automatical ly started if

• Start-up after MTRESET

• Start-up after Standby Mode release

At each state different actions are necessary to handle the Ring Oscillator. The basic separation depends on the handling of the MRCAL register.

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Chapter 5 Clock Generator

5.2 Ring Oscillator Control Registers

5.2.1 RingOSC Control Register (MRCTL)

The MRCTL register is an 8-bit register that controls the RingOSC operation. This register can be read or written in 8-b it un its. Howev er, bits 1 (MRCALSF) and 0 (MRCALE RR) are read-only.

Cautions: 1. After system reset has been release d, the MRCALEN bit can be written only one

time.

2. When the MRON bit = 0, the MRCLKSEL bit can’t be written.

Figure 5-1: RingOSC Control Register (MRCTL) Format (1/2)

7 6 5 4 3 2 1 0 Address Initial value

MRCTL MRON MRCL KSEL 0 MRCALEN 0 0 MRCAL SF MRCALERR 0x2E 0x5 0

After Reset 0 1 0 1 0 0 0 0

R/W R/W R/W R R/W R R R R

MRON Operation / Stop of RingOSC and MRNGCTL operation control

0 Ring Oscillator stopped 1 Ring Oscillator enabled

This bit will be set when MRCLKSEL = 1 and a rising edge at MTCSP pin occurs.

Cautions: 1. After MTRESET and MTCS = “1” the MRON bit is changed from “0” to “1” by hard-

ware.

2. To save power consumption the Ring Oscillator can be stopped by clearing the MRON bit to “0”. After that, the MTRC has to be woken up via the PCM0/CS signal. The MRCAL register has to be updated, too.

MRCLKSEL System clock selection for meter

0 CLK as input for clock supply by FG2 1 internal Ring Oscillator as clock source

Caution: If MRON bit = “0” (Ring Oscillator stopped for power saving) no MTRC register

access is possible. Therefor the MRON bit can’t be set to “1” (Ring Oscillator as clock source)

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Chapter 5 Clock Generator

Figure 5-1: RingOSC Control Register for the Meter (MRCTL) Format (2/2)

MRCALEN Ring Oscillator frequency calibration operation control

0 Calibration disabled 1 Calibration enabled

Caution: After the MTRESET

pin has been released, the MRCALEN bit can be written only one

time.

MRCALSF RingOSC frequency calibration operation status flag

0 Ring Oscillator calibration procedure is not active 1 during the Ring Oscillator calibration procedure

The MRCALSF bit will be set to “1” when the MRON bit = 1(ring oscillator activated) and the MRCALEN bit = “1” (MTRC is set to calibration mode) The MRCALSF bit will be reset to “0” by the following condition:

• when MRON bit = “0” (ring oscillator deactivated)

• when calibration procedure was finished successful

• when calibration error occurred with MRCALEN bit = “1”

• when MRCALEN bit = “0” (calibration register MRCAL has to be rewritten manually without auto-

matic calibration procedure)

MRCALERR RingOSC frequency calibration error flag

0 No calibration error 1 Calibration error

The MRCALERR bit is set to “1 ”, when the rin g oscil lator ca librati on is not no rmally execute d. This will happen, when the pulse width of the calibration pulse at the MTCS pin hasn’t got the specified high and low pulse width, or the calibration temperature is not in the specified range.

When the MRON bit is set to “0” (ring oscillator stopped) the MRCALLERR bit will be reset to “0“.

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Chapter 5 Clock Generator

5.2.2 RingOSC Calibration Register (MRCAL)

The MRCAL register is a 5-bit register for the RingOSC calibration operation. This register can be read or written in 8-bit units.

This register can be se t i n a ra nge of 0x 01to 0x1F. The frequency of RingOSC will b e i ncr eas ed by the MRCAL register value.

If the MRON bit = “0” and the MRCALEN bit = “1” (MRCT L register) the MRCAL r egister will be set to 0x10, which is the middle of its value range.

This register can be written only once:

• after MTRESET

pin release: After setting MRON bit = 1 (done by hardware if MTCS bit = 1) and MRCALEN bit = 0 (written manually)

• after standby mode release: After setting MRON bit from 0 to 1 while MRCALEN bit = 0

Figure 5-2: RingOSC Calibration Register (MRCAL) Format

7 6 5 4 3 2 1 0 Address Initial value

MRCAL 0 0 0 MRCAL4 MRCAL3 MRCAL2 MRCAL1 MRCAL0 0xXX 0x50

After Reset 0 0 0 1 0 0 0 0

R/W R R R R/W R/W R/W R/W R/W

Caution: When the MRON bit is set to 1 after a power save mode (MRON bit was “0”) this regis-

ter has to be rewritten with the formerly stored calibration value (e.g. external EEPROM) that has f ollowed fr om the fr equency ca libration at the sp ecified temper ature and voltage.

5.3 Calibration Procedure

To calibrate the Ring Oscillator 5 specified calibration pulses of the same length at the PCM0 pin of the FG2 are necessary. To guarante e the maxi mum deviatio n of the ca librated Ring Oscillato r this ca libration has to be performed at the specified temperature and with the specified voltage.

After the autocalib ration of the ring oscil lator the calibration cor rection value is stored in the MRCAL register. This value has to be read out and stored in a nonvo latile memory (e.g. external EEPR OM) if the ring oscillator has to be stopped for power save mode and woken up again after power save mode. This is due to the fact, that the data retentio n of the MRCAL register can’t be guaranteed duri ng the time of the stopped ring oscillator.

Please see the following procedure for the autocalibration function.

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Chapter 5 Clock Generator

Figure 5-3: Flowchart for Frequency Calibration

Initial Settings

MTRESET=1

Set PCM0 pin=1

wait for eliminating noise time

Set PCM0 pin=0

wait for oscillation stabilization time

one specified pulse output

via PCM0

auto control

5 specified pulse output

completion?

Yes

FG2 pin settings (SOB1, SCKB1, SIB1, PCM0). Setting to form the specified pulse via PCM0 (Timer etc.)

RingOSC oscillation start, enable MRINGCTL operation (after eliminating noise time of MTCSP pin)

Set PCM0 pin=1

No calibration error?

Yes

MRCAL register read

Store in the EEPROM

soft control serial communication

MRCALERR bit read

Set MRON=0

Set MTCS pin=0

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Ring Oscillator

MTRESET pin

Chapter 5 Clock Generator

Figure 5-4: Timing Diagram for Frequency Calibration

PCM0/CS pin

MRON bit

MRCALSF bit

MRCALEN bit

"H"

RingOSC

oscillation start

enable MRINGCTL

operation

eliminating noise time

Oscillation stabilization time

Calibration

start

1st specified pulse

RingOSC count start

2nd specified pulse

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5.4 MTRESET Release of the MTRC

If the MTRC is reset, the MRCAL register will be reset, too. Therefore the befor ehand stored MRCAL register value has to be written back. Please see the following procedure for the MTRESET

Figure 5-5: Flowchart for MTRESET Release

Release of the MTRC.

Ring Oscillator is stopped

uncalibrated

RingOsc is running

calibrated

RingOsc is running

Initial Settings

MTRESET = 1

Set PCM0 pin = 1

wait for Eliminating noise time + Oscillation stabilization time

Set MRCALEN = 0

The value stored in the

EEPROM is loaded to

the MRCAL register

wait for Oscillation stabilization time

FG2 pin settings (SOB1, SCKB1, SIB1, PCM0)

RingOSC oscillation start after eliminating noise time of PCM0 pin. MRINGCTL operation is enabled.

soft control serial communication

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Ring Oscillator

MTRESET pin

Chapter 5 Clock Generator

Figure 5-6: Timing for MTRES Release

Autocalibration won't performed

even for rising edge at PCM0/CS pin

PCM0/CS pin

MRON bit

MRCALSF bit

MRCALEN bit

"L"

RingOSC

oscillation start

enable MRINGCTL

operation

Calibration start

eliminating noise time

Oscillation stabilization time

Calibration disable

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Chapter 5 Clock Generator

5.5 Standby Mode Release of the Ring Oscillator

To save power, the ring oscillator could be switched off via setting the MRON bit of the MRCTL register = 0. During the time of the stopp ed Ring Os cill ator, the data retention of the MRCAL regi ster ca n’t be guaranteed. Therefore the before stored value of the MRCA L r egiste r ( e.g. in an external EEPROM) h as to be write back to the MRCAL register after the waken. The PCM0 pin of the FG2 will wake up the Ring Oscillator from its standby mode. To switch the Ring Oscillator on again the following procedure has to be fulfilled.

Figure 5-7: Flowchart for Standby Mode Release

Set MRON=0

calibrated

RingOsc is running

(RingOsc is stopped)

Set PCM0/CS pin=0

Standby mode setting

RingOsc is stopped

uncalibrated

RingOsc

calibrated

RingOsc

Standby mode

Standby mode release

Set PCM0/CS pin=1

wait for Eliminating noise time + Oscillation stabilization time

The value stored in the

EEPROM is loaded to

the MRCAL register

wait for Oscillation stabilization time

RingOSC oscillation start. Enable MRINGCTL operation after eliminating noise time of MTCSP pin)

soft control serial communication

100

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