Datasheet UPD78P322GF-3B9, UPD78P322L, UPD78P322KD, UPD78P322KC, UPD78P322K Datasheet (NEC)

DATA SHEET

MOS Integrated Circuit

µ

PD78P322

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78P322 is a version provided by replacing the µPD75322's internal mask ROM with one-time PROM

or EPROM.

Because the one-time PROM version is programmable only once by users, it is ideally suited for small-scale

production of many different products, and rapid development and time-to-market of application sets.

The EPROM version is reprogrammable, and suited for the evaluation of systems.

µ

PD78P322K, which is the EPROM version, does not maintain planned reliability when

The
used in mass-produced products. Please use only experimentally or for evaluating functions
during trial manufacture.

Functions are described in detail in the following user's manual. Be sure to read it for designing.

µ

PD78322 User's Manual: IEU-1248

FEATURES

•

µ

PD78322 compatible

µ

• For mass-production, the
ROM

PD78P322 can be replaced with the µPD78322 which incorporates mask

• Internal PROM: 16,384 × 8 bits

• Programmable once only (one-time PROM version without window)

• Erasable with ultraviolet rays and electrically programmable (EPROM version with window)

• PROM programming characteristics:

• The

µ

PD78P328 is a QTOPTM microcontroller

Remark QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM, and

are totally supported by NEC's programming service (from programming to marking, screening, and
verification).

ORDERING INFORMATION

Part Number Package Internal ROM Quality Grade

µ

PD78P322GF-3B9 80-pin plastic QFP (14 × 20 mm) One-time PROM Standard

µ

PD78P322GJ-5BJ 74-pin plastic QFP (20 × 20 mm) One-time PROM Standard

µ

PD78P322L 68-pin plastic QFJ (950 × 950 mils) One-time PROM Standard

µ

PD78P322K 80-pin ceramic WQFN EPROM Not applicable

µ

PD78P322KC 68-pin ceramic WQFN EPROM Standard

µ

PD78P322KD 74-pin ceramic WQFN EPROM Standard

µ

PD27C256A compatible

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the
specification of quality grade on the devices and its recommended applications.

Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document.

Document No. U10435EJ5V0DS00 (5th edition)

(Previous No. IC-2485)
Date Published December 1995 P
Printed in Japan

The information in this document is subject to change without notice.

The mark * shows revised points.

©

©

1991

1994

PIN CONFIGURATIONS (Top View)

(1) Normal operating mode

• 80-pin plastic QFP (14 × 20 mm)

µ

PD78P322GF-3B9

• 80-pin ceramic WQFN

µ

PD78P322K

80NC79

P27/INTP6/TI

NC

NC
P30/TxD
P31/RxD

P32/SO/SB0

P33/S1/SB1

P34/SCK
P80/TO00
P81/TO01
P82/TO02
P83/TO03
P84/TO10

NC

P85/TO11

RESET

X2
X1

V

WDTO

RTP0/P00

NC

TRP1/P01

NC

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25 26 27 28 29 30 31 32 33 34 35 36 37

P26/INTP5

P25/INTP4

P24/INTP3

78

77

76

P23/INTP2

P22/INTP1

P21/INTP0

75

74

73

DD

DD

P20/NMI

V

AV

72

71

REF

AV

70

P75/ANI5

P76/AN6

P77/AN765P73/AN3

67

68

69

38

66

39

P74/AN4

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41 P42/AD2

40

P72/ANI2
NC
NC
P71/ANI1
P70/ANI0

SS

AV
V

DD

P57/A15
P56/A14

P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
NC
NC
NC

µ

PD78P322

SSVSS

EA

RTP2/P02

RTP3/P03

RTP4/P04

RTP5/P05

RTP6/P06

RTP7/P07

V

P92/TAS

P93/TMD

P91/WR

ASTB

P90/RD

P40/AD0

P41/AD1

Caution Connect NC pins to VSS as a measure against noise (can leave open).

µ

Remark These pins are compatible with the

µ

PD78P322K does not maintain planned reliability when used in mass-produced products. Please use only

The

PD78322GF pins.

experimentally or for evaluating functions during trial manufacture.

2

• 74-pin plastic QFP (20 × 20 mm)

µ

PD78P322GJ-5BJ

• 74-pin ceramic WQFN

µ

PD78P322KD

P42/AD2

P41/AD1

74 73 72 71 70 69 68 67 66 65 64 63 62 57

P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7

P50/A8

P51/A9
P52/A10
P53/A11
P54/A12
P55/A13

NC
P56/A14
P57/A15

V

AVSS
P70/AN0
P71/AN1

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

20 21 22 23 24 25 26 27 28 29 30 31 32

19

P40/AD0

ASTB

P90/RD

P91/WR

P92/ TAS

P93/ TMD

VSSEA

P07/RTP7

P06/RTP6

P05/RTP5

61

33

P04/RTP4

P03/RTP3

P02/RTP2

60

59

58

34

35

36NC37

P01/RTP1

NC

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38

µ

PD78P322

P00/RTP0
WDTO

SS

V
NC
X1
X2
RESET
P85/TO11
P84/TO10
P83/TO03
P82/TO02
P81/TO01
P80/TO00
NC
P34/SCK
P33/SI/SBI
P32/SO/SB0
P31/RxD
P30/TxD

NC

P72/AN2

P73/AN3

P74/AN4

P75/AN5

Caution Connect NC pins to V

SS for measures against noise (can leave open).

Remark These pins are compatible with the

REF

VDD

AVDD

AV

P76/AN6

P77/AN7

µ

PD78322GJ pins.

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2

P24/INTP3

P25/INTP4

P26/INTP5

P27/INTP6

3

• 68-pin plastic QFJ (950 × 950 mils)

µ

PD78P322L

• 68-pin ceramic WQFN

µ

PD78P322KC

P27/INTP6/TI

P26/INTP5

P25/INTP4

98765432168676665 61

P30/TxD

P31/RxD

P32/SO/SB0

P33/SI/SB1

P34/SCK
P80/TO00
P81/TO01
P82/TO02

P83/TO03
P84/TO10
P85/TO11

RESET

X2
X1

V

WDTO

RTP0/P00

SS

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27 28 29 30 31 32 33 34 35 36 37 38 39

P24/INTP3

P23/INTP2

P22/INTP1

P21/INTP0

P20/NMI

VDDAVDD

AVREF

P77/AN7

P76/AN664P75/AN563P74/AN462P73/AN3

40

41

P72/AN2

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

P71/AN1
P70/AN0

SS

AV
VDD
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3

µ

PD78P322

SS

EA

V

P02/RTP2

P03/RTP3

P01/RTP1

P04/RTP4

P05/RTP5

P06/RTP6

P07/RTP7

P93/TMD

Remark These pins are compatible with the µPD78322L pins.

P91/WR

P92/TAS

ASTB

P90/RD

P40/AD0

P41/AD142P42/AD2

4

µ

PD78P322

P00-P07 : Port 0 RESET : Reset
P20-P27 : Port 2 X1, X2 : Crystal
P30-P34 : Port 3 WDTO : Watchdog Timer Output
P40-P47 : Port 4 EA : External Access
P50-P57 : Port 5 TMD : Turbo Mode
P70-P77 : Port 7 TAS : Turbo Access Strobe
P80-P85 : Port 8 WR : Write Strobe
P90-P93 : Port 9 RD : Read Strobe
NMI : Nonmaskable Interrupt ASTB : Address Strobe
INTP0-INTP6 : Interrupt From Peripherals AD0-AD7 : Address/Data Bus
RTP0-RTP7 : Real-Time Port A8-A15 : Address Bus
TI : Timer Input AN0-AN7 : Analog Input
TxD : Transmit Data AV
RxD : Receive Data AVSS : Analog VSS
SB0/SO : Serial Bus/Serial Output AVDD : Analog VDD
SB1/SI : Serial Bus/Serial Input VDD : Power Supply
SCK : Serial Clock VSS : Ground
TO00-TO03 : NC : No Connection
TO10, TO11 :

Timer Output

}

REF : Analog Reference Voltage

5

(2) PROM programming mode (RESET = H, AVDD = L)

• 80-pin plastic QFP (14 × 20 mm)

µ

PD78P322GF-3B9

• 80-pin ceramic WQFN

µ

PD78P322K

µ

PD78P322

(G)
NC
NC
OE
CE

(L)

A8
A10
A11
A12
A13

NC

A14

RESET

(Open)

(G)
V

(Open)

A0

NC

A1

NC

(G)

80NC79 78 77A576 75 74 73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

SS

19
20
21
22
23
24

25 26 27 28 29 30 31 32 33 34 35 36 37

A9

72

DD

V

71

DD

AV

70 676869 6566

(G)

38D039D140

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41 D2

(G)
NC
NC

V

D7
D6
D5
D4
D3
NC
NC
NC

(G)

DD

(Open)

A2A3A4

A6

A7

PPVSSVSS

V

(Open)

Cautions 1. The recommended connection of the unused pins in the PROM programming mode are

indicated in parentheses.
L : Connect each pin to V

SS via a resistor.

G : Connect the pin to VSS.
Open : Leave the pin unconnected.

2. Connect NC pins to V

SS for measures against noise (can leave open).

The µPD78P322K does not maintain planned reliability when used in mass-produced products. Please use only
experimentally or for evaluating functions during trial manufacture.

6

• 74-pin plastic QFP (20 × 20 mm)

µ

PD78P322GJ-5BJ

• 74-pin ceramic WQFN

µ

PD78P322KD

µ

PD78P322

(L)

(L)

(G)

D3
D4
D5
D6
D7

NC

V

D2D1D0

74 73 72 71 70 69 68 67 66 65 64 63 62 57

1
2
3
4
5
6
7
8
9
10
11
12
13
14

DD

15
16
17
18

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36NC37

19

(Open)

(L)

VSSVPPA7A6

A561A460A359A258A1

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38

NC

A0
(Open)

SS

V
NC
(G)
(Open)
RESET
A14
A13
A12
A11
A10
A8
NC

(L)

CE
OE

DD

NC

(G)

AV

A9

VDD

(G)

Cautions 1. The recommended connection of the unused pins in the PROM programming mode are

indicated in parentheses.
L : Connect each pin to V

SS via a resistor.

G : Connect the pin to VSS.
Open : Leave the pin unconnected.

2. Connect NC pins to V

SS as measure against noise.

7

• 68-pin plastic QFJ (950 × 950 mil)

µ

PD78P322L

• 68-pin ceramic WQFN

µ

PD78P322KC

µ

PD78P322

OE

CE

(L)

A8
A10
A11
A12
A13
A14

RESET

(Open)

(G)
V

(Open)

A0

(G)

98765432168676665 61

10
11
12
13
14
15
16
17
18
19
20
21
22
23

SS

24
25
26

27 28 29 30 31 32 33 34 35 36 37 38 39

A9

DD

DD

V

AV

(G)

64 63 62

40D041D142D243

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

V

D7
D6
D5
D4
D3

(G)

DD

(L)

A1

A2

A3

A5A6A7

A4

PPVSS

V

(L)

(Open)

Caution The recommended connection of the unused pins in the PROM programming mode are indicated

in parentheses.
L : Connect each pin to V

SS via a resistor.

G : Connect the pin to VSS.
Open : Leave the pin unconnected.

A0-A14 : Address Bus RESET :
D0-D7 : Data Bus AV
CE : Chip Enable V

DD :

PP : Programming Power Supply

Programming Mode set

}

OE : Output Enable NC : No Connection

8

BLOCK DIAGRAM

(P20) NMI

INTP0-INTP5

(P21-P26)

(P80) TO00
(P81) TO01

(P82) TO02
(P83) TO03
(P84) TO10
(P85) TO11

(P27) TI/INTP6

(P34) SCK

(P32) SO/SB0

(P33) SI/SB1

(P30) TxD

(P31) RxD

PROGRAMMABLE
INTERRUPT
CONTROLLER

TIMER/COUNTER UNIT
(REALTIME PULSE
UNIT)

SERIAL INTERFACE

(SBI)

(UART)

EXU

Main RAM

GENERAL
REGISTERS
128 bytes
&
DATA
MEMORY
128 bytes

MICRO SEQUENCE
CONTROL

MICRO ROM

A/D CONVERTER

(10 bits)

AV

AVDD

ANI0-ANI7

(P70-P77)

SS

ALU

PROM/RAM

PROM

16

Kbytes

/

Peripheral

RAM

384

bytes

BCU

SYSTEM

CONTROL

&

BUS

CONTROL

&

PREFETCH

CONTROL

X1
X2

RESET
ASTB
RD
WR
TAS
TMD

Note

EA/V

PP

A8-A15 (P50-P57)

AD0-AD7 (P40-P47)

A0-A14

D0-D7
CE

OE

Note

PORTWDT

2

AVREF

2

WDTO

VDD

VSS

P80-P85

P90-P93

P50-P57

P70-P77

P40-P47

P00-P07 (REALTIME PORT)

P20-P27

P30-P34

Note

During PROM programming mode

µ

PD78P322

9

CONTENTS

1. PIN FUNCTIONS ... 11

1.1 Normal Operating Mode ... 11

1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 13

1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 14

2. DIFFERENCES BETWEEN µPD78P322 and µPD78322 ... 16

3. PROM PROGRAMMING ... 17

3.1 Operation Mode ... 17

3.2 PROM Write Procedure ... 18

3.3 PROM Read Procedure ... 20

4. ERASURE CHARACTERISTICS (FOR µPD78P322K/KC/KD ONLY) ... 21

5. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P322K/KC/KD ONLY) ... 21

µ

PD78P322

6. ONE-TIME PROM VERSION SCREENING ... 21

7. ELECTRICAL SPECIFICATIONS ... 22

8. PACKAGE DRAWINGS ... 36

9. RECOMMENDED SOLDERING CONDITIONS ... 42

APPENDIX A.

APPENDIX B. TOOLS ... 48

B.1 Development Tools ... 48
B.2 Evaluation Tools ... 52

*

B.3 Embedded Software ... 52

DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS

... 44

10

µ

PD78P322

1. PIN FUNCTIONS

1.1 Normal Operating Mode

(1) Port Pins

Pin Name Input/Output Function Alternate

Function

P00-P07 Input/Output PORT0 RTP0-RTP7

(Output) 8-bit input/output port

Input or output mode can be specified bit-wise.

The port can also operate as a real-time output port.
P20 Input PORT 2 NMI
P21 8-bit input-only port INTP0
P22 INTP1
P23 INTP2
P24 INTP3
P25 INTP4
P26 INTP5
P27 INTP6/TI
P30 Input/Output PORT 3 TxD
P31 5-bit input/output port RxD
P32 Input or output mode can be specified bit-wise. SO/SB0
P33 SI/SB1
P34 SCK
P40-P47 Input/Output PORT 4 AD0-AD7

8-bit input/output port

Input or output mode can be specified in 8-bit units.
P50-P57 Input/Output PORT 5 A8-A15

8-bit input/output port

Input or output mode can be specified bit-wise.
P70-P77 Input PORT 7 AN0-AN7

8-bit input-only port
P80 Input/Output PORT 8 TO00
P81 6-bit input/output port TO01
P82 Input or output mode can be specified bit-wise. TO02
P83 TO03
P84 TO10
P85 TO11
P90 Input/Output PORT 9 RD
P91 4-bit input/output port WR
P92 Input or output mode can be specified bit-wise. TAS
P93 TMD

11

(2) Non-Port Pins (1/2)

Pin Name Input/Output Function Alternate

RTP0-RTP7 Output Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07

INTP0 Input Edge-detected external interrupt request input. P21
INTP1 The valid edge can be specified in the mode register. P22
INTP2 P23
INTP3 P24
INTP4 P25
INTP5 P26
INTP6 P27/TI
NMI Input Edge-detected nonmaskable interrupt request input. P20

TI Input External count clock input pin to timer 1 (TM1). P27/INTP6
RxD Input Serial data input pin to asynchronous serial interface (UART). P31
TxD Output Serial data output pin from asynchronous serial interface (UART). P30
SI Input Serial data input pin to clocked serial interface in 3-wire mode. P33/SB1
SO Output Serial data output pin from clocked serial interface in 3-wire mode. P32/SB0
SB0 Input/Output Serial data input/output pins to/from clocked serial interface in SBI mode. P32/SO
SB1 P33/SI
SCK Input/Output Serial clock input/output pin to/from clocked serial interface. P34
AD0-AD7 Input/Output Multiplexed address/data bus used when external memory is added. P40-P47
A8-A15 Output Address bus used when external memory is added. P50-P57
RD Output Strobe signal output for external memory read operation. P90
WR Strobe signal output for external memory write operation. P91

*

TAS Output Control signal output pins to access turbo access manager (µPD71P301).
TMD P93
TO00 Output Pulse output from real-time pulse unit. P80
TO01 P81
TO02 P82
TO03 P83
TO10 P84
TO11 P85
ASTB Output Timing signal output pin to externally latch low-order address information output from —

WDTO Output Signal output which indicates that watchdog timer generated non-maskable interrupt. —
EA Input For µPD78P322, normally connect the EA pin to VDD. When the EA pin is connected to —

the real-time pulse unit (RPU).

The rising or falling edge can be selected for the valid edge by setting the mode register.

Note

AD0-AD7 for external memory access.

VSS, the µPD78P322 enters the ROMless mode and external memory is accessed.
The EA pin level cannot be changed during operation.

µ

PD78P322

Function

P92

Note Turbo access manager (µPD71P301) is available for maintenance purposes only.

12

µ

PD78P322

(2) Non-Port Pins (2/2)

Pin Name Input/Output Function Alternate

Function
AN0-AN7 Input Analog input to A/D converter. P70-P77
AVREF Input A/D converter reference voltage input. —
AVDD — A/D converter analog power supply. —
AVSS — A/D converter GND. —
RESET Input System reset input. —
X1 Input Crystal resonator connection pin for system clock generation. To supply external clock, —
X2 input to the X1 and input inverted signal to the X2 pin (X2 pin can be unconnected.)
VDD — Positive power supply pin. —
VSS — GND pin. —
NC — No internal connection. Connect to VSS (can leave open). —

1.2 PROM Programming Mode (RESET = H, AVDD = L)

Pin Name Input/Output Function
AVDD Input PROM programming mode setting.
RESET
A0-A14 Input Address bus.
D0-D7 Input/Output Data bus.
CE Input PROM enable to PROM.
OE Input Read strobe to PROM.
VPP — Write power supply.
VDD Positive power supply.
VSS GND.
NC No internal connection. Connect to VSS (can leave open).

13

1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins

Table 1-1 and Figure 1-1 show the pin input/output circuit schematically.

Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins

Pin Input/Output Recommended connection of unused pins

circuit type

P00/RTP0-P07/RTP7 5 Input state: Independently connect to VDD or VSS via a resistor.

Output state: Leave Open.
P20/NMI 2 Connect to V SS.
P21/INTP0-P26/INTP5
P27/INTP6/TI
P30/TxD 5 Input state: Independently connect to VDD or VSS via a resistor.
P31/RxD Output state: Leave Open.
P32/SO/SB0 8
P33/SI/SB1
P34/SCK
P40/AD0-P47/AD7 5
P50/A8-P57/A15
P70/AN0-P77/AN7 9 Connect to V SS.
P80/TO00-P83/TO03 5 Input state: Independently connect to VDD or VSS via a resistor.
P84/TO10, P85/TO11 Output state: Leave Open.
P90/RD 5
P91/WR
P92/TAS
P93/TMD
WDTO 3 Leave Open.
ASTB 4
EA 1 —
RESET 2 —
AVDD — Connect to VDD.
AVREF — Connect to VSS.
AVSS
VPP — Connect to VDD.
NC — Connect to VSS (can leave open).

µ

PD78P322

14

Figure 1-1. Pin Input/Output Circuits

TYPE 1 TYPE 5

V

DD

IN

P-ch

N-ch

output
disable

input
disable

data

µ

PD78P322

V

DD

P-ch

IN/OUT

N-ch

TYPE 2

IN

TYPE 8

data

output
disable

Schmitt-triggerred input with hysteresis characteristics

TYPE 3 TYPE 9

V

DD

P-ch

OUT

IN

N-ch

TYPE 4

P-ch
N-ch

(Threshold voltage)

V

DD

P-ch

N-ch

V

REF

IN/OUT

Comparator

+

–

input
enable

V

DD

data

output
disable

Push-pull output that can be placed in high impedance
(both P-ch and N-ch off).

P-ch

N-ch

OUT

15

µ

PD78P322

2. DIFFERENCES BETWEEN µPD78P322 and µPD78322

The µPD78P322 is a version provided by replacing the µPD78322's on-chip mask ROM with one-time PROM
or EPROM. Thus, the µPD78P322 and µPD78322 are the same in function except for the ROM specifications such
as write or verify. Table 2-1 lists the differences between these two products.

µ

This Data Sheet describes the PROM specification function. Refer to the
other functions.

PD78322 documents for details of

Table 2-1. Differences between µPD78P322 and µPD78322

Item
Internal program memory One-time PROM EPROM Mask ROM
(electrical program) (programmable only once) (reprogrammable) (nonprogrammable)
PROM programming pin Contained Not contained
Package • 68-pin plastic QFJ • 68-pin ceramic WQFN • 68-pin plastic QFJ

*
*

*

Electrical specifications Current dissipations are different.
Others Noise immunity and noise radiation differ because circuit complexity and mask layout are

Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To

replace the PROM version with the mask ROM version when shifting from experimental production
to mass production, evaluate your system by using the CS version (not ES version) of the mask
ROM version.

Part Number

µ

PD78P322

• 74-pin plastic QFP • 74-pin ceramic WQFN • 74-pin plastic QFP

• 80-pin plastic QFP • 80-pin ceramic WQFN • 80-pin plastic QFP

different.

µ

PD78322

16

µ

PD78P322

3. PROM PROGRAMMING

The PROM incorporated in the µPD78P322 is a 16,384 × 8-bit electrically writable PROM. For programming,

set the PROM programming mode by using the RESET and AVDD pins.

The programming characteristics are compatible with the µPD27C256A programming characteristics.

Table 3-1. Pin Function in Programming Mode

Function Normal Operating Mode Programming Mode
Address input P00-P07, P80, P20, P81-P85 A0-A14
Data input P40-P47 D0-D7
Chip enable/program pulse P31 CE
Output enable P30 OE
Program voltage VPP
Mode control RESET, AVDD

3.1 Operation Mode

To set the program write/verify mode, set RESET = H and AV

selected by setting the CE and OE pins, as listed in Table 3-2.

To read the PROM contents, set the read mode.
Connect the unused pins exactly as indicated in Pin Configuration.

DD = L. For the mode, the operation mode can be

Table 3-2. PROM Programming Operation Mode

Mode RESET AVDD CE OE VPP VDD D0-D7
Program write H L L H +12.5 V +6 V Data input
Program verify H L Data output
Program inhibit H H High impedance
Read L L +5 V +5 V Data output
Output disable L H High impedance
Standby H L/H High impedance

Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is prohibited.

17

3.2 PROM Write Procedure

The write procedure into PROM is as follows:

µ

PD78P322

(1) Fix RESET = H and AV

DD = L. Connect other unused pins exactly as indicated in section "Pin Configuration."

(2) Supply +6 V to the VDD and +12.5 V to the VPP pin.
(3) Supply an initial address.
(4) Supply write data.
(5) Supply 1 ms program pulse (active low) to the CE pin.
(6) Execute the verify mode. Check whether or not the write data is written normally.

• When it is written normally: Proceed to step (8).

• When it is not written normally: Repeat steps (4) to (6).

If the data is not written normally after 25 repetitions of the steps, proceed to step (7).
(7) Assume the device to be defective. Stop write operation.
(8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write).
(9) Increment the address.
(10) Repeat steps (4) to (9) to the last address.

Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above.

Figure 3-1. PROM Write/Verify Timing

X-time repetition

Write

Verify

Additional
data write

A0-A14

D0-D7

+12.5 V

V

PP

+6 V

V

DD

CE (input)

OE (input)

Address input

Hi-ZHi-Z Hi-Z Hi-Z

Data input

V

DD

V

DD

Data

output

Data input

3 X ms

18

Figure 3-2. Write Procedure Flowchart

µ

PD78P322

(1)

(2)

(3)

(4)

(5)

Write NG

(after 24

repetition or less)

(8)

(9)

WRITE START

Supply power

Supply initial address

Supply write data

Supply program pulse

(6)

Verify mode

Write OK

Make additional write

(3X ms pulses)

Increment address

Write NG
(at the 25th repetition)

X: Number of write

repetitions

< end address

(10)

End address

> end address

WRITE END Defective device

(7)

19

3.3 PROM Read Procedure

The read procedure of the PROM contents into the external data bus (D0-D7) is as follows.

µ

PD78P322

(1) Fix RESET = H and AV
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of the data to be read to the A0-A14 pins.
(4) Execute the read mode.
(5) The data is output to the D0-D7 pins.

Figure 3-3 shows the PROM read timing steps (2) to (5) above.

DD = L. Connect other unused pins exactly as indicated in Pin Configuration.

Figure 3-3. PROM Read Timing

A0-A14

CE (input)

OE (input)

D0-D7

Hi-Z Hi-Z

Address input

Data output

20

µ

PD78P322

4. ERASURE CHARACTERISTICS (FOR µPD78P322K/KC/KD ONLY)

The data written into the µPD78P322K/KC/KD program memory can be erased (FFH) and new data can be

rewritten into the memory.

To erase data, apply light with a wavelength shorter than 400 nm to the window. Normally, apply ultraviolet rays

having the 254-nm wavelength. The radiation amount required to completely erase data is as follows:

2

• Ultraviolet strength x erasure time: 15 W•s/cm

• Erasure time: 15 to 20 minutes when a 12,000
prolonged due to ultraviolet lamp performance deterioration, dirty window, etc.

For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the

ultraviolet lamp, remove the filter before applying ultraviolet rays.

or more

µ

W/cm2 ultraviolet lamp is used. However, the time may be

5. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P322K/KC/KD ONLY)

If the µPD78P322K/KC/KD window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may
be erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a
protective seal on the window.

A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at
shipment.

6. ONE-TIME PROM VERSION SCREENING

The one-time PROM versions (µPD78P322GF-3B9, 78P322GJ-5BJ, 78P322L) cannot be completely tested by
NEC for shipment because of their structure. For screening, it is recommended to verify PROM after storing the
necessary data under the following conditions:

Storage temperature Storage time
125˚C 24 hours

NEC provides chargeable services ranging from one-time PROM writing to marking, screening and verification
for QTOP microcontroller products. For details, contact an NEC sales representative.

21

µ

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25 °C)

Parameter Symbol Test Conditions Ratings Unit
Power supply voltage VDD –0.5 to +7.0 V

AVDD –0.5 to VDD +0.5 V
VPP –0.5 to +13.5 V
AVSS –0.5 to +0.5 V

Input voltage VI1 Note 1 –0.5 to VDD +0.5 V

VI2 P20/NIM (A9) PIN –0.5 to +13.5 V
Output voltage VO –0.5 to VDD +0.5 V
Output current, low IOL All output pins 4.0 mA

Total for all pins 90 mA

Output current, high IOH All output pins –1.0 mA

Total for all pins –20 mA

Analog input voltage VIAN Note 2 AVDD > VDD –0.5 to VDD +0.5 V

VDD ≥ AVDD –0.5 to AVDD +0.5
A/D converter reference AVREF AVDD > VDD –0.5 to VDD +0.3 V
input voltage VDD ≥ AVDD –0.5 to AVDD +0.3
Operating ambient temperature TA –10 to +70 °C
Storage temperature Tstg –65 to +150 °C

PD78P322

Notes 1. Pins except for P20/NMI (A9), P70/AN0-P77/AN7

2. P70/AN0-P77/AN7

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,

*

even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions

Oscillation frequency TA VDD
8 MHz ≤ fXX ≤ 16 MHz –10 to +70 ˚C +5.0 V ±5%

Capacitance (TA = 25 °C, VSS = VDD = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input capacitance CI f = 1 MHz 10 pF
Output capacitance CO Unmeasured pins returned to 0 V 20 pF
I/O capacitance CIO 20 pF

22

µ

PD78P322

Oscillator Characteristics (TA = –10 to +70 °C, VDD = +5 V±5%, VSS = 0 V)

Resonator Recommended Circuit Parameter MIN. MAX. Unit
Ceramic or crystal Oscillation frequency (fXX) 8 16 MHz
resonator

V

X1X2

SS

C1C2

External clock X1 input frequency (fX) 8 16 MHz

X1 X2

HCMOS
Inverter

or

X1 X2

Open

HCMOS
Inverter

X1 input rise, fall time (fXR, tXF) 0 20 ns

X1 input high, low level width 25 80 ns
(tWXH, tWXL)

Caution When using the system clock oscillator, wire the portion enclosed in broken lines in the figure as

follows to avoid adverse influences on the wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of
lines through which a high fluctuating current flows.

• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

SS. Do not connect the power source pattern through which a high current flows.

V

• Do not extract signals from the oscillator.

23

Recommended Oscillator Constants

Ceramic resonator

Manufacturer Name Part Number Frequency Recommended

MURATA CSA8.00MT 8.0 30 30

[MHz] Constants

C1 [pF] C2 [pF]

CSA12.0MT 12.0
CSA14.74MXZ040 14.74 15 15
CSA16.00MX040 16.0
CST8.00MTW 8.0 Internal Internal
CST12.0MTW 12.0
CST14.74MXW0C3 14.74
CST16.00MXW0C3 16.0

µ

PD78P322

Crystal resonator

Manufacturer Name Part Number Frequency Recommended

[MHz] Constants

C1 [pF] C2 [pF]

KINSEKI HC49/U-S 8 to 16 10 10

HC49/U

24

µ

PD78P322

DC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input voltage, low VIL 0 0.8 V
Input voltage, high VIH1 Note 1 2.2 V

VIH2 Note 2 0.8VDD
Output voltage, low VOL IOL = 2.0 mA 0.45 V
Output voltage, high VOH IOH = –400 µAVDD–1.0 V
Input leakage current ILI 0 V ≤ VI ≤ VDD ±10
Output leakage current ILO 0 V ≤ VO ≤ VDD ±10
VDD power supply current IDD1 Operation mode 40 65 mA

IDD2 HALT mode 20 35 mA
Data retention voltage VDDDR STOP mode 2.5 V
Data retention current IDDDR STOP mode VDDDR = 2.5 V 2 10

VDDDR = 5.0 V ±5% 10 50

µ

A

µ

A

µ

A

µ

A

Notes 1. Pins other than mentioned in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/

INTP6/TI, P32/SO/SB0, P33/SI/SB1, or P34/SCK pins.

25

AC Characteristics (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

*

Discontinuous read/write operation (when general-purpose memory is connected)

Parameter Symbol Test Conditions MIN. MAX. Unit
System clock cycle time tCYK 125 250 ns
Address setup time (to ASTB ↓)tSAST 32 ns
Address hold time (from ASTB ↓)tHSTA 32 ns
Address → RD ↓ delay time tDAR 85 ns
RD ↓ → address float time tFRA 0ns
Address → data input time tDAID 222 ns
RD ↓ → data input time tDRID 112 ns
ASTB ↓ → RD ↓ delay time tDSTR 42 ns
Data hold time (from RD ↑)tHRID 0ns
RD ↑ → address active time tDRA 50 ns
RD low level width tWRL 157 ns
ASTB high level width tWSTH 37 ns
Address → WR ↓ delay time tDAW 85 ns
ASTB ↓ → data output time tDSTOD 102 ns
WR ↓ → data output time tDWOD 40 ns
ASTB ↓ → WR ↓ delay time tDSTW 42 ns
Data setup time (to WR ↑)tSODW 147 ns
Data hold time (from WR ↑)tHWOD 32 ns
WR ↑ → ASTB ↑ delay time tDWST 42 ns
WR low level width tWWL 157 ns

µ

PD78P322

26

tCYK-Dependent Bus Timing Definition

Parameter Calculation expression MIN./MAX. Unit
tSAST 0.5T – 30 MIN. ns
tHSTA 0.5T – 30 MIN. ns
tDAR T – 40 MIN. ns
tDAID (2.5 + n) T – 90 MAX. ns
tDRID (1.5 + n) T – 75 MAX. ns
tDSTR 0.5T – 20 MIN. ns
tDRA 0.5T – 12 MIN. ns
tWRL (1.5 + n) T – 30 MIN. ns
tWSTH 0.5T – 25 MIN. ns
tDAW T – 40 MIN. ns
tDSTOD 0.5T + 40 MAX. ns
tDSTW 0.5T – 20 MIN. ns
tSODW 1.5T – 40 MIN. ns
tHWOD 0.5T – 30 MIN. ns
tDWST 0.5T – 20 MIN. ns
tWWL (1.5 + n) T – 30 MIN. ns

µ

PD78P322

Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency).

2. n is the number of wait cycles defined by user software.

3. Only parameters listed in the table are dependent on tCYK.

27

µ

PD78P322

Serial Operation (TA = –10 to +70 °C, VDD = +5 V ±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. MAX. Unit
Serial clock cycle time tCYSK SCK Output Internal divide by 8 1

SCK Input External clock 1

Serial clock high-level width tWSKL SCK Output Internal divide by 8 420 ns

SCK Input External clock 420 ns

Serial clock high-level width tWSKH SCK Output Internal divide by 8 420 ns

SCK Input External clock 420 ns
SI setup time (to SCK ↑)tSRXSK 80 ns
SI hold time (from SCK ↑)tHSKRX 80 ns
SCK ↓ → SO delay time tDSKTX R = 1 kΩ, C = 100 pF 210 ns

µ

s

µ

s

Other operations (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = 0 V)

Parameter Symbol Test Conditions MIN. MAX. Unit
NMI high, low-level width tWNIH,5

tWNIL

INTP0 high, low-level width tWI0H,8TtCYK

tWI0L

INTP1 high, low-level width tWI1H,8TtCYK

tWI1L

INTP2 high, low-level width tWI2H,8TtCYK

tWI2L

INTP3 high, low-level width tWI3H,8TtCYK

tWI3L

INTP4 high, low-level width tWI4H,8TtCYK

tWI4L

INTP5 high, low-level width tWI5H,8TtCYK

tWI5L

INTP6 high, low-level width tWI6H,8TtCYK

tWI6L

RESET high, low-level width tWRSH,5

tWRSL

TI high, low-level width tWTIH, TM1 8T tCYK

tWTIL In the event counter mode

µ

s

µ

s

28

µ

PD78P322

A/D Converter (TA = –10 to +70˚C, VDD = +5 V±5%, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Total error

Quantization error ±1/2 LSB
Conversion time tCONV 144 tCYK
Sampling time tSAMP 24 tCYK
Zero scale error

Fullscale error

Nonlinear error

Analog input voltage
Basic voltage AVREF 3.4 AVDD V
AVREF current AIREF 1.0 3.0 mA
AVDD supply current AIDD 2.0 6.0 mA
A/D converter data AIDDDR STOP mode AVDDDR = 2.5 V 2.0 10
retention current AVDDDR = 5 V±5% 10 50

Note1

Note1

Note1

Note1

Note2

4.5 V ≤ AVREF ≤ AVDD ±0.4 %FSR

3.4 V ≤ AVREF ≤ AVDD ±0.7 %FSR

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

4.5 V ≤ AVREF ≤ AVDD +1.5 ±2.5 LSB

3.4 V ≤ AVREF ≤ AVDD +1.5 ±4.5 LSB

VIAN –0.3 AVDD V

µ

A

µ

A

*

Notes 1. Quantization error is excluded.

2. When –0.3 V ≤ V

IAN ≤ 0 V, conversion result is 000H.

When 0 V < VIAN < AVREF, conversion is executed with 10-bit resolution.
When AV

REF ≤ VIAN ≤ AVDD, conversion result is 3FFH.

29

Discontinuous Read Operation

(CLK)

t

CYK

µ

PD78P322

P50-P57
(output)

P40-P47
(input/output)

ASTB
(output)

RD (output)

Discontinuous Write Operation

(CLK)

P50-P57
(output)

t

(output)

t

DAR

DAID

t

t

DSTR

HSTA

t

SAST

Low-order address

t

WSTH

High-order address High-order address

Hi-ZHi-Z Hi-Z Hi-Z

t

FRA

Data (input)

t

t

DRID

t

WRL

HRID

t

DRA

Low-order address

(output)

High-order address High-order address

P40-P47
(input/output)

ASTB
(output)

WR (output)

t

SAST

Low-order address

(output)

t

WSTH

t

HSTA

t

DSTW

t

DAW

Undefined

t

DSTOD

t

DWOD

t

WWL

Data (output)

t

SODW

t

HWOD

t

DWST

Low-order address

(output)

30

Serial Operation

SCK

SO

SI

Interrupt Input Timing

t

DSKTX

t

SRXSK

t

WSKL

t

CYSK

t

WSKH

t

HSKRX

µ

PD78P322

Remark n = 0-6

NMI

INTPn

t

WNIH

0.8V

0.8 V

t

WInH

t

WNIL

DD

t

WInL

31

Reset Input Timing

µ

PD78P322

TI Pin Input Timing

RESET

TI

t

WRSH

0.8V

t

WTIH

DD

0.8 V

t

WRSL

t

WTIL

32

µ

PD78P322

DC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)

Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit

Note1

Input voltage, high VIH VIH 2.2 VDDP V

+0.3
Input voltage, low VIL VIL –0.3 0.8 V
Input leakage current ILIP ILI 0 ≤ VI ≤ VDDP
Output voltage, high VOH VOH IOH = –400 µA 2.4 V
Output voltage, low VOL VOL IOL = 2.0 mA 0.45 V
Input current IA9 — A9 (P20/NMI) pin ±10
Output leakage current ILO —0 ≤ VO ≤ VDDP, OE = VIN 10
PROG pin high voltage input IIP — ±10
current
VDDP power supply voltage VDDP VDD Program memory write mode 5.75 6.0 6.25 V

Program memory read mode 4.5 5.0 5.5 V

VPP power supply voltage VPP VPP Program memory write mode 12.2 12.5 12.8 V

Program memory read mode VPP = VDDP V

VDDP power supply current IDD IDD Program memory write mode 10 30 mA

Program memory read mode 10 30 mA
CE = VIL, VI = VIH

VPP power supply current IPP IPP Program memory write mode 10 30 mA

CE = VIL, OE = VIH
Program memory read mode 1 100

Note 2

±10

µ

A

µ

A

µ

A

µ

A

µ

A

Notes 1. Corresponding µPD27C256A symbols.

2. VDDP is VDD pin during the programming mode.

33

µ

PD78P322

AC Programming Characteristics (TA = 25 ± 5 °C, VSS = 0 V)

Parameter Symbol Symbol Test conditions MIN. TYP. MAX. Unit

Note

Address setup time (to CE ↓)tSAC tAS 2
Data → OE ↓ delay time tDDOO tOES 2
Input data setup time (to CE ↓)tSIDC tDS 2
Address hold time (from CE ↑)tHCA tAH 2
Input data hold time (from CE ↑)tHCID tDH 2
Output data hold time (from OE ↑)tHOOD tDF 0 130 ns
VPP setup time (to CE ↓)tSVPC tVPS 2
VDDP setup time (to CE ↓)tSVDC tVDS 2
Initial program pulse width tWL1 tPW 0.95 1.0 1.05 ms
Additional program pulse width tWL2 tOPW 2.85 78.75 ms
Address → data output time tDAOD tACC OE = VIL 2
OE ↓ → data output time tDOOD tOE 1
Data hold time (from OE ↑)tHCOD tDF 0 130 ns
Data hold time (from address) tHAOD tOH OE = VIL 0ns

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Note Corresponding µPD27C256A symbols.

34

PROM Write Mode Timing

µ

PD78P322

V

V

DDP

CE

OE

PP

A12-A0

D7-D0

V

V

DDP

V

DDP

+1

V

DDP

V

V

V

V

t

SAC

Hi-Z Hi-Z Hi-Z Hi-Z

PP

IH

IL

IH

IL

Data input

t

SIDC

t

SVPC

t

SVDC

t

WL1

Effective address

Data output Data input

t

HCID

t

DDOO

t

DOOD

Cautions 1. Apply VDDP before VPP and remove it after VPP.

2. VPP must not exceed +13 V, including the overshoot.

PROM Read Mode Timing

t

HOOD

t

SIDC

t

HCA

t

HCID

t

WL2

A12-A0

OE

D7-D0

t

DAOD

Effective address

t

DOOD

t

HAOD

Data output

t

HCOD

Hi-ZHi-Z

35

8. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14×20)

µ

PD78P322

A

B

64

65

80

F

1

G

H

M

I

P

N

NOTE

Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.

41

40

detail of lead end

C

D

S

Q

25

24

J

K

M

L

P80GF-80-3B9-2

ITEM MILLIMETERS INCHES

0.929±0.016

+0.009

0.795

–0.008

+0.009

0.551

–0.008

0.693±0.016

0.039

0.031

+0.004

0.014

–0.005

0.006

0.031 (T.P.)

+0.008

0.071

–0.009

+0.009

0.031

–0.008

+0.004

0.006

–0.003

0.006

M

A

B

C

D

F

G

H

I

J

K

L

N

23.6±0.4

20.0±0.2

14.0±0.2

17.6±0.4

1.0

0.8

0.35±0.10

0.15

0.8 (T.P.)

1.8±0.2

0.8±0.2

+0.10

0.15

–0.05

0.15

P 2.7 0.106

Q

0.1±0.1

0.004±0.004

S 3.0 MAX. 0.119 MAX.

5°±5°

36

74 PIN PLASTIC QFP ( 20)

µ

PD78P322

A

B

2

F

57

56

38

37

C

1

F

74

1

1

G

H

M

IJ

18

19

G

2

K

P

M

N

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

L

D

S

detail of lead end

Q

ITEM MILLIMETERS INCHES

A 23.2±0.4 0.913

B 20.0±0.2 0.787

C 20.0±0.2 0.787

D 23.2±0.4 0.913

1

F
F

2

G

1

G

2

H 0.40±0.10 0.016

I
J 1.0 (T.P.) 0.039 (T.P.)
K 1.6±0.2 0.063±0.008

L 0.8±0.2 0.031

M 0.15 0.006

N 0.10 0.004
P 3.7 0.146

Q

R5°±5° 5 °±5°
S 4.0 MAX.

R

2.0

1.0

2.0

1.0

0.20

+0.10
–0.05

0.1±0.1 0.004±0.004

0.079

0.039

0.079

0.039

0.008

0.158 MAX.

S74GJ-100-5BJ-3

+0.017
–0.016

+0.009
–0.008

+0.009
–0.008

+0.017
–0.016

+0.004
–0.005

+0.009
–0.008

+0.004
–0.003

37

68 PIN PLASTIC QFJ ( 950 mil)

68

1

µ

PD78P322

A
B

C

D

F E

G

H

IJ

K

M

N

NOTE

Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

Q

M

P

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

M

N

P

Q

T

U

25.2±0.2

24.20

24.20

25.2±0.2

1.94±0.15

0.6

4.4±0.2

2.8±0.2

0.9 MIN.

3.4

1.27 (T.P.)

0.40±1.0

0.12

23.12±0.20

0.15

R 0.8

+0.10

0.20

–0.05

U

T

0.992±0.008

0.953

0.953

0.992±0.008

0.076

0.024

0.173

0.110

0.035 MIN.

0.134

0.050 (T.P.)

0.016

0.005

0.910

0.006

R 0.031

0.008

P68L-50A1-2

+0.007

–0.006

+0.009

–0.008

+0.009

–0.008

+0.004

–0.005

+0.009

–0.008

+0.004

–0.002

38

80 PIN CERAMIC WQFN

µ

PD78P322

A

B

T

U

E

NOTE

Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.

K

C

D

W

H

I

G

F

Q

80

S

1

M

J

R

X80KW-80A-1

ITEM MILLIMETERS INCHES

+0.017

0.787

–0.016

0.748

0.520

0.559±0.016

0.065

0.084

0.160 MAX.

0.020±0.004

0.003

0.031 (T.P.)

+0.009

0.039

–0.008

C 0.020

0.031

0.043

R 0.118

0.472

+0.008

0.030

–0.009

Q

W

A

B

C

D

E

F

G

H

I

J

K

20.0±0.4

19.0

13.2

14.2±0.4

1.64

2.14

4.064 MAX.

0.51±0.10

0.08

0.8 (T.P.)

1.0±0.2

C 0.5

R

S

T

U

0.8

1.1

R 3.0

12.0

0.75±0.2

39

74 PIN CERAMIC WQFN

µ

PD78P322

A

B

T

Y

E

U

NOTE

Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.

K

C

D

W

H

G

F

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

Q

R

S

T

U

W

Y

20.0±0.4

18.0

18.0

20.0±0.4

1.94

2.14

4.0 MAX.

0.51±0.10

0.10

1.0 (T.P.)

1.0±0.2

C 0.3

2.0

2.0

R 2.0

10.0

0.7±0.2

C 1.5

M

I

J

X74KW-100A-1

0.787

0.709

0.709

0.787

0.076

0.084

0.158 MAX.

0.020±0.004

0.004

0.039 (T.P.)

0.039

C 0.012

0.079

0.079

R 0.079

0.394

0.028

C 0.059

1

R

+0.017

–0.016

+0.017

–0.016

+0.009

–0.008

+0.008

–0.009

Q

74

S

40

68 PIN CERAMIC WQFN

µ

PD78P322

A

B

T

U

Y

E

NOTE

Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

K

C

D

H

G

F

M

I

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

L

P

Q

R

S

T

U

Y

24.13±0.4

21.5

21.5

24.13±0.4

1.65

2.03

3.50 MAX.

0.64±0.10

0.12

1.27 (T.P.)

1.27±0.2

2.16±0.2

R 0.2

C 1.02

1.905

1.905

R 3.0

12.0

C 0.5

0.950±0.016

0.846

0.846

0.950±0.016

0.065

0.080

0.138 MAX.

0.025

0.005

0.05 (T.P.)

0.05±0.008

0.085±0.008

R 0.008

C 0.04

0.075

0.075

R 0.118

0.472

C 0.020

L

Q

P

68

1

R

J

X68KW-50A-1

+0.005
–0.004

S

41

µ

PD78P322

9. RECOMMENDED SOLDERING CONDITIONS

It is recommended that this device be soldered under the following conditions.
For details on the recommended soldering conditions, refer to information document "Semiconductor Devices
Mounting Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.

Table 9-1. Soldering Conditions for Surface Mount Devices (1/2)

µ

*

PD78P322GF-3B9: 80-pin plastic QFP (14 × 20 mm)

Soldering Method Soldering Conditions Recommended Soldering

Code

Infrared reflow Package peak temperature: 235˚C, IR35-207-2

Time: 30 seconds max. (210˚C min.),
Number of times: 2 max., Maximum number of days: 7 days
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

VPS Package peak temperature: 215˚C, VP15-207-2

Time: 40 seconds max. (200˚C min.),
Number of times: 2 max., Maximum number of days: 7 days
(thereafter, 20 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Wave soldering Soldering bath temperature: 260˚C max., Time: 10 seconds max., WS60-207-1

Number of times: 1,
Preheating temperature: 120°C max. (package surface temperature),
Maximum number of days: 7 days
prebaking is required at 125˚C).

Partial heating Pin temperature: 300˚C max., —

Time: 3 seconds max. (per pin)

Note

(thereafter, 20 hours of

Note

Note

µ

PD78P322GJ-5BJ: 74-pin plastic QFP (20 × 20 mm)

Soldering Method Soldering Conditions Recommended Soldering

Code

Infrared reflow Package peak temperature: 230˚C, IR30-107-1

Time: 30 seconds max. (210˚C min.), Number of times: 1,
Maximum number of days: 7 days
(thereafter, 10 hours of prebaking is required at 125˚C)

VPS Package peak temperature: 215˚C, VP15-107-1

Time: 40 seconds max. (200˚C min.), Number of times: 1,
Maximum number of days: 7 days
(thereafter, 20 hours of prebaking is required at 125˚C)

Partial heating Pin temperature: 300˚C max., —

Time: 3 seconds max. (per pin)

Note

Note

Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max.

Caution Do not use different soldering methods together (except for partial heating method).

42

µ

PD78P322

Table 9-1. Soldering Conditions for Surface Mount Devices (2/2)

µ

PD78P322L: 68-pin plastic QFJ (950 × 950 mils)

Soldering Method Soldering Conditions Recommended Soldering

Code

Infrared reflow Package peak temperature: 235˚C, IR35-367-2

Time: 30 seconds max. (210˚C min.), Number of times: 2 max.,
Maximum number of days: 7 days
(thereafter, 36 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

VPS Package peak temperature: 215˚C, VP15-367-2

Time: 40 seconds max. (200˚C min.), Number of times: 2 max.,
Maximum number of days: 7 days
(thereafter, 36 hours of prebaking is required at 125˚C)
< Cautions >
(1) Wait for the device temperature to return to normal after the first

reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Partial heating Pin temperature: 300˚C max., —

Time: 3 seconds max. (per pin)

Note

Note

*

Note Number of days after unpacking the dry pack. Storage conditions are 25°C and 65% RH max.

Caution Do not use different soldering methods together (except for partial heating method).

43

µ

PD78P322

APPENDIX A. DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS

(1) EV-9200G-74

Figure A-1. Drawing of Conversion Socket (EV-9200G-74)

(For reference only)

E

C

D

No.1 pin index

C 1.5

1

A

B

EV-9200G-74

G

H

I

M

25.0

20.35

20.35

25.0

4-C 2.8

1.0

11.0

22.0

24.7

5.0

22.0

24.7

8.0

7.8

2.5

2.0

1.35

0.35±0.1

φ

2.3

φ

1.5

N

F

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P

Q

R

S

T

O

R

S

J

P

EV-9200G-74-G0

0.984

0.801

0.801

0.984

4-C 0.11

0.039

0.433

0.866

0.972

0.197

0.866

0.972

0.315

0.307

0.098

0.079

0.053

+0.004

0.014

–0.005

φ

0.091

φ

0.059

Q

T

L

K

44

µ

PD78P322

Figure A-2. Recommended Footprint of Conversion Socket (EV-9200G-74)

(For reference only)

G

J

F

E

D

K

C

B

H

I

A

EV-9200G-74-P0

ITEM MILLIMETERS INCHES

+0.002

–0.001

+0.002

–0.001

1.012

0.827

0.827

1.012

0.433

0.197

0.024

φ

0.093

φ

0.062

+0.004

–0.003

+0.003

–0.004

+0.001

–0.002

+0.001

–0.002

+0.001

–0.002

A

B

C

D

E

F

G

H

I

J

K

Caution

25.7

21.0

±

1.0

0.02 × 18=18.0

±

1.0

0.02 × 18=18.0

±

0.05

0.039 × 0.709=0.709

±

0.05

0.039 × 0.709=0.709

21.0

25.7

11.00±0.08

5.00±0.08

0.6±0.02

φ

2.36±0.03

φ

1.57±0.03

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).

+0.002

–0.003

+0.002

–0.003

45

(2) EV-9200G-80

Figure A-3. Drawing of Conversion Socket (EV-9200G-80)

(For reference only)

µ

PD78P322

F

E

C

D

No.1 pin index

1

A

B

EV-9200G-80

H

I

J

N

G

ITEM MILLIMETERS INCHES

A

B

C

D

E

F

G

H

I

J

K

L

M

O

N

P

Q

R

S

T

U

O P

25.0

20.30

4.0

14.45

19.0

4-C 2.8

0.8

11.0

22.0

24.7

5.0

16.2

18.9

8.0

7.8

2.5

2.0

1.35

0.35±0.1

φ

2.3

φ

1.5

S

K

Q

T

U

EV-9200G-80-G0

0.984

0.799

0.157

0.569

0.748

4-C 0.11

0.031

0.433

0.866

0.972

0.197

0.638

0.744

0.315

0.307

0.098

0.079

0.053

+0.004

0.014

–0.005

φ

0.091

φ

0.059

R

L

M

46

µ

PD78P322

Figure A-4. Recommended Footprint of Conversion Socket (EV-9200G-80)

(For reference only)

G

H

L

F

E

D

M

C

B

A

EV-9200G-80-P0

ITEM MILLIMETERS INCHES

+0.002

–0.001

+0.002

–0.001

1.012

0.827

0.598

0.783

0.433

0.217

0.197

0.098

+0.001

0.02

–0.002

φ

0.093

φ

0.062

+0.004

–0.003

+0.001

–0.002

+0.003

–0.004

+0.002

–0.001

+0.001

–0.002

+0.001

–0.002

M

A

B

C

D

E

F

G

H

I

J

K

L

25.7

21.0

±

0.8

0.02 × 23=18.4

±

0.8

0.02 × 15=12.0

15.2

19.9

11.00±0.08

5.50±0.03

5.00±0.08

2.50±0.03

0.5±0.02

φ

2.36±0.03

φ

1.57±0.03

±

0.05

0.031 × 0.906=0.724

±

0.05

0.031 × 0.591=0.472

J

I

K

+0.003

–0.002

+0.003

–0.002

Caution

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).

47

APPENDIX B. TOOLS

*

B.1 Development Tools

The following development tools are readily available to support development of systems using the µPD78P322:

Language Processor

78K/III Series Relocatable assembler common to the 78K/III series. Since it contains the macro function, the
relocatable assembler development efficiency can be improved. A structured assembler which enables you to explicity
(RA78K/III) describe program control structure is also attached and program productivity and maintenance

78K/III Series C compiler common to the 78K/III series. This is a program to convert a program written in C
C compiler language into an object code executable with a microcontroller. When using the compiler,
(CC78K/III) 78K/III series relocatable assembler (RA78K/III) is necessary.

µ

PD78P322

can be improved.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS

IBM PC/AT

TM

PC DOS
and compatible machine 5-inch 2HC
HP9000 series 700
SPARCstation

TM

NEWS

TM

HP-UX

TM

SunOS

NEWS-OS

TM

TM

TM

TM

TM

3.5-inch 2HD
5-inch 2HD

3.5-inch 2HC

DAT
Cartridge tape
(QIC-24)

µ

S5A13RA78K3

µ

S5A10RA78K3

µ

S7B13RA78K3

µ

S7B10RA78K3

µ

S3P16RA78K3

µ

S3K15RA78K3

µ

S3R15RA78K3

Host machine Ordering code

OS Supply medium (product name)
PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD

IBM PC/AT

TM

PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC
HP9000 series 700 HP-UX DAT
SPARCstation SunOS Cartridge tape
NEWS NEWS-OS (QIC-24)

µ

S5A13CC78K3

µ

S5A10CC78K3

µ

S7B13CC78K3

µ

S7B10CC78K3

µ

S3P16CC78K3

µ

S3K15CC78K3

µ

S3R15CC78K3

Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under

the operating systems listed above.

48

µ

PD78P322

PROM Write Tools

Hard- PG-1500 PG-1500 is a PROM programmer which enables you to program single chip micro­ware controllers containing PROM by stand-alone or host machine operation by connecting an

attached board and optional programmer adapter to PG-1500. It also enables you to

program typical PROM devices of 256K bits to 4M bits.
UNISITE PROM programmer manufactured by Data I. O. Japan.
2900
PA-78P322GF PROM programmer adapters to write programs onto the µPD78P322 on a general
PA-78P322GJ purpose PROM programmer such as PG-1500.
PA-78P322K PA-78P322GF ... µPD78P322GF
PA-78P322KC PA-78P322GJ ... µPD78P322GJ
PA-78P322KD PA-78P322K ... µPD78P322K
PA-78P322L PA-78P322KC ... µPD78P322KC

PA-78P322KD ... µPD78P322KD

PA-78P322L ... µPD78P322L

Soft- PG-1500 controller Connects PG-1500 and a host machine by a serial or parallel interface and controlls
ware PG-1500 on the host machine.

Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HD
and compatible machine 5-inch 2HC

µ

S5A13PG1500

µ

S5A10PG1500

µ

S7B13PG1500

µ

S7B10PG1500

Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating

systems listed above.

49

µ

PD78P322

Debugging Tools

Hard- IE-78327-R IE-78327-R and IE-78320-R are in-circuit emulators that can be used for application
ware IE-78320-R

EP-78320GF-R Emulation probe to connect IE-78327-R or IE-78320-R to the target system.

EP-78320GJ-R EP-78320GF-R ................. 80-pin plastic QFP

EP-78320L-R EP-78320GJ-R.................. 74-pin plastic QFP

Soft- IE-78327-R Program to control IE-78327-R on a host machine. Automatic execution of commands,
ware control program etc., is enabled for more efficient debugging.

(IE controller) Host machine Ordering code

IE-78320-R Program to control IE-78320-R on a host machine. Automatic execution of commands,
control program
(IE controller) Host machine Ordering code

Note

Note

system development and debugging. Connect a host machine for debugging.
IE-78327-R can be used in common for the µPD78322 subseries and the µPD78328
subseries. IE-78320-R can be used for the µPD78322 subseries.

EP-78320L-R .................... 68-pin plastic QFJ

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

etc., is enabled for more efficient debugging.

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 5-inch 2HC
and compatible machine

µ

S5A13IE78327

µ

S5A10IE78327

µ

S7B13IE78327

µ

S7B10IE78327

µ

S5A13IE78320

µ

S5A10IE78320

µ

S7B10IE78320

Remarks 1. The operation of the IE controller is guaranteed only on the host machine under the operating

systems listed above.

µ

PD78322 subseries:

2.

µ

PD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1),
78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1),
78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1),
78P324(A2)

µ

PD78328 subseries:

µ

PD78327, 78328, 78P328, 78327(A), 78328(A)

Note Conventional IE-78320-R is a maintenance product. When purchasing a new incircuit emulator, use an

alternative product IE-78327-R.

50

Host machine
PC-9800 series or
IBM PC/AT

Software

RS-232-C

RS-232C

PG-1500

Relocatable assembler
(with structured
assembler)

PG-1500
controller

IE controller

IE-78327-R
In-circuit
emulator

PROM
programmer

On-chip PROM version

Programmer adapter

PD78P322GF

PA-78P322GJ

PA-78P322GF

EV-9200G-80
EV-9200G-74

EP-78320GF-R
EP-78320GJ-R

EP-78320L-R

Socket to connect emulation probe and target system

Note

Socket for plastic QFJ

Target system

PA-78P322L

Note
Remarks

The socket is attached to the emulation probe.

The host machine and PG-1500 can be connected directly by RS-232-C.

Emulation probe

+

+++

+

µ

PD78P322GJ

µ

PD78P322L

µ

PD78P322K

µ

PD78P322KC

µ

PD78P322KD

µ

PD78P322K

µ

PD78P322KC

µ

PD78P322KD

µ

Development Tool Configuration

51

µ

PD78P322

µ

PD78P322

B.2 Evaluation Tools

The following evaluation tools are provided to evaluate the µPD78P322 function:

Ordering Code Host Machine Function
(product name)
EB-78320-98 PC-9800 series The µPD78P322 function can be easily evaluated by connecting the evaluation tool to

a host machine. The EB-78320-98/PC command system basically is compliant with the

EB-78320-PC IBM PC/AT IE-78327-R or IE-78320-R command system. Thus, easy transition to application system

and compatible development process by IE-78327-R or IE-78320-R can be made. The evaluation tools
machine enable turbo access manager (µPD71P301)

Note

to be mounted on the printed circuit board.

Note Turbo access manager (

µ

PD71P301) is available for maintenance purpose only.

Cautions 1. EB-78320-98/PC is not the µPD78P322 application system development tool.

2. EB-78320-98/PC does not contain the emulation function at internal PROM execution of the

µ

PD78P322.

B.3 Embedded Software

The following embedded software products are readily available to support more efficient program development

and maintenance:

Real-time OS

Real-time OS The purpose of RX78K/III is to realize a multi-task environment in a control area which requires
(RX78K/III) real-time processing. RX78K/III allocates idle times of CPU to other processing to improve

overall performance of the system.
RX78K/III provides a system call based on the µITRON specification.
RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to
prepare multiple information tables.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

µ

S5A13RX78320

µ

S5A10RX78320

µ

S7B13RX78320

µ

S7B10RX78320

Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the

User's Agreement.

Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary.

52

µ

PD78P322

Fuzzy Inference Development Support System

Fuzzy Knowledge Data Program supporting input of fuzzy knowledge data (fuzzy rule and membership function),
Preparation Tool input/editing (edit), and evaluation (simulation).
(FE9000, FE9200) Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS WindowsTM3.5-inch 2HC
and compatible machine 5-inch 2HC

Translator Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation
(FT78K3)

Fuzzy Inference Module Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge
(FI78K/III)

Fuzzy Inference Debugger Support software evaluating and adjusting fuzzy knowledge data at hardware level by using
(FD78K/III) in-circuit emulator.

Note

Note

tool to the assembler source program for the RA78K/III.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

data converted by translator.
Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

Host machine Ordering code

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5-inch 2HD

5-inch 2HD
IBM PC/AT PC DOS 3.5-inch 2HC
and compatible machine 5-inch 2HC

µ

S5A13FE9000

µ

S5A10FE9000

µ

S7B13FE9200

µ

S7B10FE9200

µ

S5A13FT78K3

µ

S5A10FT78K3

µ

S7B13FT78K3

µ

S7B10FT78K3

µ

S5A13FI78K3

µ

S5A10FI78K3

µ

S7B13FI78K3

µ

S7B10FI78K3

µ

S5A13FD78K3

µ

S5A10FD78K3

µ

S7B13FD78K3

µ

S7B10FD78K3

Note Under development

53

[MEMO]

µ

PD78P322

54

µ

NOTES FOR CMOS DEVICES

(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate

oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it once,
when it has occurred. Environmental control must be adequate. When it is dry,
humidifier should be used. It is recommended to avoid using insulators that easily
build static electricity. Semiconductor devices must be stored and transported in an
anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.

(2) HANDLING OF UNUSED INPUT PINS FOR CMOS

PD78P322

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection

is provided to the input pins, it is possible that an internal input level may be generated
due to noise, etc., hence causing malfunction. CMOS devices behave differently than
Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by
using a pull-up or pull-down circuitry. Each unused pin should be connected to V
or GND with a resistor, if it is considered to have a possibility of being an output pin.
All handling related to the unused pins must be judged device by device and related
specifications governing the devices.

(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device. Immediately
after the power source is turned ON, the devices with reset function have not yet been
initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or
contents of registers. Device is not initialized until the reset signal is received. Reset
operation must be executed immediately after power-on for devices having reset
function.

DD

QTOP is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.

55

µ

PD78P322

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other than
Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

License not needed: µPD78P322K, 78P322KC, 78P322KD
The customer must judge the need for license: µPD78P322GF-3B9, 78P322GJ-5BJ, 78P322L

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11