NEC UPD78F9328 DATA SHEET

PRELIMINARY PRODUCT INFORMATION

MOS INTEGRATED CIRCUIT

µµµµ

PD78F9328

8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD78F9328 is a µPD789327 Subseries (designed for remote controller with on-chip LCD) product in the 78K/0S Series, featuring expanded flash memory in place of the internal ROM of the µPD789322, 789324, 789326, and 789327.

Because flash memory allows the program to be written and erased with the device mounted on the target board, this product is ideal for development trials, small-scale production, or for applications that require frequent upgrades.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing.

µµµµ

PD789327, 789467 Subseries User’s Manual: To be prepared

78K/0S Series User’s Manual Instructions: U11047E

FEATURES

• Pin-compatible with mask ROM product (except VPP)

• Flash memory: 32 Kbytes

• Internal high-speed RAM: 512 bytes

• LCD display RAM: 24 bytes

• Variable minimum instruction execution time: High speed (0.4 µs: @5.0-MHz operation with main system clock),

low speed (1.6 µs: @5.0-MHz operation with main system clock), and ultra low speed (122 µs: @32.768-kHz

operation with subsystem clock)

• I/O ports: 21

• Serial interface (3-wire serial I/O mode): 1 channel

• LCD controller/driver

Segment signals: 24

Common signals: 4

• Timer: 4 channels

• Supply voltage: VDD = 1.8 to 5.5 V

APPLICATIONS

Remote-control devices, healthcare equipment, etc.

ORDERING INFORMATION

Part Number Package

PD78F9328GB-8ET 52-pin plastic LQFP (10 mm × 10 mm)

The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U14411EJ1V0PM00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan

78K/0S SERIES LINEUP

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products in mass production

Products under development

Small-scale, general-purpose applications

44-pin 42-/44-pin

28-pin

PD789046

PD789026 PD789014

Small-scale, general-purpose applications + A/D

PD789026 with internal subsystem clock PD789014 with enhanced timer and expanded ROM, RAM

On-chip UART. Capable of low-voltage (1.8 V) operation

µµµµ

PD78F9328

78K/0S

Series

44-/48-pin 44-/48-pin 44-pin 44-pin 30-pin

30-pin 30-pin 30-pin 30-pin 30-pin

44-pin

88-pin 80-pin 80-pin

64-pin 64-pin 64-pin 64-pin 64-pin 64-pin

PD789 PD789 PD789177 PD789167 PD789156

PD789146 PD789134A PD789124A PD789114A PD789104A

Inverter control

PD789842

LCD drive

PD789830 PD789417A

PD789407A PD789457 PD789447 PD789437 PD789427 PD789316 PD789306

217AY

197AY

µ µ

µ µ µ µ µ

µ µ µ

µ µ µ µ µ µ

RC oscillation version of the PD789197AY PD789177 with on-chip EEPROM

PD789167 with enhanced A/D converter

µ µ

PD789104A with enhanced timer

PD789146 with enhanced A/D converter PD789104A with EEPROM

PD789124A with enhanced A/D converter

RC oscillation version of the PD789104A PD789104A with enhanced A/D converter

PD789026 with added A/D, multiplier

On-chip inverter control circuit and UART

On-chip UART and dot LCD

PD789407A with enhanced A/D converter

PD789457 with enhanced I/O

PD789447 with enhanced A/D converter RC oscillation version of the PD789427

PD789427 with enhanced A/D converter

PD789306 with A/D converter RC oscillation version of the PD789306 Basic subseries for LCD drive

and SMB

ASSP

44-pin 44-pin 20-pin 20-pin

5-pin

PD789800

µ µ

PD789840

PD789861

PD789860

IC card

PD789810

Preliminary Product Information U14411EJ1V0PM00

For PC keyboard, on-chip USB function For key pad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip POC and key return circuit

On-chip EEPROM, security circuit

The major functional differences among the subseries are listed below.

µµµµ

PD78F9328

Subseries Name

PD789046 16 K 1 ch

Smallscale, generalpurpose applications

Smallscale, generalpurpose applications + A/D

Inverter

PD789026 4 K to 16 K

PD789014 2 K to 4 K 2 ch

PD789217AY

PD789197AY

PD789177

PD789167

PD789156

PD789146

PD789134A

PD789124A

PD789114A

PD789104A

PD789842 8 K to 16 K 3 ch

control LCD drive

PD789830 24 K 1 ch

PD789417A

PD789407A

PD789457

PD789447 4 ch

PD789437

PD789427

PD789316

PD789306

ROM

Capacity

8-Bit 16-Bit

TimerFunction

Watch

1 ch 1 ch 34

−

16 K to 24 K 3 ch 1 ch

8 K to 16 K

1 ch

−

2 K to 8 K

Note

1 ch 1 ch 8 ch

1 ch 1 ch 1 ch

12 K to 24 K 3 ch

16 K to 24 K

2 ch

8 K to 16 K

WDT

1 ch

8-Bit

10-Bit

A/D

−−

−

Serial Interface I/O V

A/D

1 ch (UART: 1 ch)

2 ch UART: 1ch

8 ch

SMB : 1ch

1 ch (UART: 1 ch)

8 ch

4 ch

−

4 ch

−

4 ch

−

4 ch

−

1 ch (UART: 1 ch) 30 4.0 V

−

1 ch (UART: 1 ch)

−

7 ch 43 1.8 V

7 ch

−

4 ch

−

2 ch (UART: 1 ch)

−

4 ch

−

4 ch

−

Min.

Value

1.8 V

30 2.7 V

Remarks

−

RC oscillation version, on-chip EEPROM

On-chip EEPROM

−

On-chip EEPROM

RC oscillation version

−

RC oscillation version

−

RC oscillation version

−

ASSP

PD789800

PD789840

PD789861

PD789860

IC cardµPD789810 6 K

10-bit timer: 1 channel

Note

8 K 1 ch

4 K

2 ch

−

−−−

Preliminary Product Information U14411EJ1V0PM00

1 ch

−

2 ch (USB: 1 ch) 31 4.0 V

−

4 ch 1 ch 29 2.8 V

−

14 1.8 V

RC oscillation version

−

1 ch

−− −

1 2.7 V

On-chip EEPROM

OVERVIEW OF FUNCTIONS

Item Description

µµµµ

PD78F9328

Internal memory

Main system clock (oscillation frequency)

Subsystem clock (oscillation frequency)

General-purpose registers 8 bits × 8 registers Instruction set

I/O ports Total: 21

Timers

Timer outputs 1 Serial interface 3-wire serial I/O mode: 1 channel LCD controller/driver

sources

Reset

Supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = −40 to +85°C Package 52-pin plastic LQFP (10 m m × 10 mm)

Flash memory 32 Kbytes High-speed RAM 512 bytes LCD display RAM 24 bytes

Ceramic/crystal resonator (1.0 to 5.0 MHz)

Crystal resonator (32.768 kHz)

0.4 µs/1.6 µs (@5.0-MHz operation with main system clock)Minimum instructi on execution time 122

s (@32.768-kHz operation with s ubsystem clock)

16-bit operations

•

Bit manipulation (set, reset, test) etc.

•

CMOS I/O: 21

8-bit timer: 2 channels

•

Watch timer: 1 c hannel

•

Watchdog timer: 1 channel

•

Segment signal outputs: 24

•

Common signal outputs: 4

•

Maskable Internal: 6, External: 2Vectored interrupt Non-maskable Internal: 1

Reset by RESET signal input

•

Internal reset by watchdog timer

•

Reset via power-on-clear circuit

•

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 7

2. BLOCK DIAGRAM.................................................................................................................................8

3. PIN FUNCTIONS....................................................................................................................................9

3.1 Port Pins......................................................................................................................................... 9

3.2 Non-Port Pins .............................................................................................................................. 10

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.......................................... 11

4. CPU ARCHITECTURE.........................................................................................................................13

4.1 Memory Space............................................................................................................................. 13

4.2 Data Memory Addressing........................................................................................................... 14

4.3 Processor Registers ................................................................................................................... 15

4.3.1 Control registers...............................................................................................................................15

4.3.2 General-purpose registers................................................................................................................16

4.3.3 Special function registers (SFRs).....................................................................................................17

5. PERIPHERAL HARDWARE FUNCTIONS ......................................................................................... 19

5.1 Ports.............................................................................................................................................19

5.1.1 Port functions....................................................................................................................................19

5.1.2 Port configuration .............................................................................................................................21

5.1.3 Port function control registers...........................................................................................................22

5.2 Clock Generator .......................................................................................................................... 25

5.2.1 Clock generator function...................................................................................................................25

5.2.2 Clock generator configuration...........................................................................................................25

5.2.3 Clock generator control registers......................................................................................................27

5.3 8-Bit Timer 30, 40 ........................................................................................................................ 30

5.3.1 Functions of 8-bit timer 30, 40..........................................................................................................30

5.3.2 Configuration of 8-bit timer 30, 40....................................................................................................31

5.3.3 8-bit timer 30, 40 control registers....................................................................................................36

5.4 Watch Timer.................................................................................................................................40

5.4.1 Watch timer functions.......................................................................................................................40

5.4.2 Watch timer configuration.................................................................................................................41

5.4.3 Watch timer control register..............................................................................................................42

5.5 Watchdog Timer.......................................................................................................................... 43

5.5.1 Watchdog timer functions.................................................................................................................43

5.5.2 Watchdog timer configuration...........................................................................................................43

5.5.3 Watchdog timer control register........................................................................................................44

5.6 Serial Interface 10........................................................................................................................ 45

5.6.1 Functions of serial interface 10 ........................................................................................................45

5.6.2 Configuration of serial interface 10...................................................................................................45

5.6.3 Control register for serial interface 10 ..............................................................................................47

5.7 LCD Controller/Driver ................................................................................................................. 49

5.7.1 LCD controller/driver functions.........................................................................................................49

5.7.2 LCD controller/driver configuration...................................................................................................49

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

5.7.3 LCD controller/driver control registers..............................................................................................52

6. INTERRUPT FUNCTION......................................................................................................................55

6.1 Interrupt Types ............................................................................................................................55

6.2 Interrupt Sources and Configuration ........................................................................................55

6.3 Interrupt Function Control Registers........................................................................................58

7. STANDBY FUNCTION.........................................................................................................................64

7.1 Standby Function........................................................................................................................64

7.2 Standby Function Control Register...........................................................................................66

8. RESET FUNCTION...............................................................................................................................67

8.1 Reset Function ............................................................................................................................67

8.2 Power Failure Detection Function.............................................................................................69

9. FLASH MEMORY PROGRAMMING...................................................................................................70

9.1 Selection of Communication Mode ...........................................................................................70

9.2 Flash Memory Programming Functions....................................................................................71

9.3 Flashpro III Connection Example...............................................................................................71

9.4 Setting Example Using Flashpro III (PG-FP3)...........................................................................72

10. INSTRUCTION SET OVERVIEW......................................................................................................73

10.1 Conventions...............................................................................................................................73

10.1.1 Operand formats and descriptions..................................................................................................73

10.1.2 Operation field definitions...............................................................................................................74

10.1.3 Flag operation field definitions........................................................................................................74

10.2 Operations..................................................................................................................................75

11. ELECTRICAL SPECIFICATIONS ......................................................................................................80

APPENDIX A. DIFFERENCES BETWEEN

APPENDIX B. DEVELOPMENT TOOLS ................................................................................................92

APPENDIX C. RELATED DOCUMENTS................................................................................................94

PD78F9328 AND MASK ROM VERSIONS................91

µµµµ

Preliminary Product Information U14411EJ1V0PM00

1. PIN CONFIGURATION (TOP VIEW)

µµµµ

PD78F9328

52-pin plastic LQFP (10 mm

PD78F9328GB-8ET

µµµµ

RESET P60/TO40 P43/KR03 P42/KR02 P41/KR01 P40/KR00

P03 P02 P01 P00

INT/P61

P11 P10

10 mm)

××××

X1X2VDD

52 51 50 49 48 47 46 45 44 43 42

1 2 3 4 5 6 7 8 9 10 11 12 13

14 15 16 17 18 19 20 21 21 23 24

VSS

XT2

XT1

VPP

P20/SCK10

LC0

P21/SO10

P22/SI10

S23

41 40

P80/S22

39 38 37 36 35 34 33 32 31 30 29 28

P81/S21 P82/S20 P83/S19 P84/S18 P85/S17 S16 S15 S14 S13 S12 S11 S10 S9

COM0

COM1

COM2

COM3

S1S2S3S4S5

Caution In normal operation mode, directly connect the VPP pin to VSS.

COM0 to COM3: Common Output RESET: Reset INT: Interrupt from Peripherals S0 to S23: Segment Output KR00 to KR03: Key Return SCK10: Serial Clock Input/Output P00 to P03: Port 0 SI10: Serial Data Input P10, P11: Port 1 SO10: Serial Data Output

P20 to P22: Port 2 V P40 to P43: Port 4 V

: Power Supply

LC0

: Power Supply for LCD P60, P61: Port 6 VPP: Programming Power Supply P80 to P85: Port 8 VSS: Ground TO40: Timer Output X1, X2: Crystal (Main system clock)

XT1, XT2: Crystal (Sabsystem clock)

Preliminary Product Information U14411EJ1V0PM00

2. BLOCK DIAGRAM

µµµµ

PD78F9328

TO40/P60

SCK10/P20

SO10/P21

SI10/P22

S0 to S23

COM0 to COM3

LC0

8-bit timer 30

8-bit timer 40

Watchdog timer

Serial interface 10

Cascaded

16-bit timer

Watch timer

LCD controller/driver

78K/0S CPU core

RAM

Flash

memory

RAM space for LCD data

Port 0

Port 1

Port 2

Port 4

Port 6

Port 8

System control

P00 to P03

P10, P11

P20 to P22

P40 to P43

P60, P61

P80 to P85

RESET X1 X2 XT1 XT2

Power-on clear

VDDVSSV

INT/P61

Interrupt control

KR00/P40 to KR03/P43

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function Af ter Reset Alternate Function

P00 to P03 I/O Port 0.

This is a 4-bit I/O port. Input/output can be spec i f i ed i n 1-bi t units. When used as an input port, on-chip pull -up resistors can be specified for the whole port using pull-up resistor option register 0 (PU0).

P10, P11 I/O Port 1.

This is a 2-bit I/O port. Input/output can be spec i f i ed i n 1-bi t units. When used as an input port, on-chip pull -up resistors can be specified for the whole port using pull-up resistor option

P40 to P43 I/O Port 4.

P60 TO40 P61

P80 to P85 I/O Port 8.

I/O Port 2.

This is a 3-bit I/O port.

Input/output can be spec i f i ed i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be

specified in 1-bit units using pull-up resistor option regi s ter 2

(PUB2).

This is a 4-bit I/O port.

Input/output can be spec i f i ed i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be

specified for the whole port using pull-up resistor option

I/O Port 6.

This is a 2-bit I/O port.

Input/output can be spec i f i ed i n 1-bi t units.

This is a 6-bit I/O port.

Input/output can be spec i f i ed i n 1-bi t units.

Input

SI10

Input KR00 to KR03

Input

INT

Low-level output

S22 to S17

−

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

3.2

Non-Port Pins

Pin Name I/O Function Af ter Reset Alternate Function

INT Input External interrupt input f or whi ch the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified. KR00 to KR03 Input Key return signal detection Input P40 to P43 TO40 Output 8-bit timer 40 output Input P60 SCK10 I/O Serial cl ock input/output of serial i nterface 10 Input P20 SI10 Input Serial data input of serial i nt erface 10 Input P22 SO10 Output Serial data out put of serial interface 10 Input P21 S0 to S16 S17 to S22 P85 to P80 S23 COM0 to COM3 Output LCD controller/driver common si gnal out puts Low-level

LC0

V X1 Input X2 XT1 Input XT2 RESET Input System reset input Input

Output LCD controller/driver segment signal outputs Low-level

LCD drive voltage

−

Connecting crystal res onator for main system clock oscillation

−

Connecting crystal res onator for subsystem clock oscillation

−

Positive power supply

−

Ground potential

−

Flash memory programming mode setting.

−

High-voltage application for program write/verify.

In normal operation mode, connect di rectly to V

Input P61

output

−−

−

Preliminary Product Information U14411EJ1V0PM00

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins is shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins

Pin Name I/O Ci rcuit Type I/O Recommend Connection of Unused Pi ns P00 to P03 P10, P11

5-A

I/O Input: Independently connec t to V

Output: Leave open.

P20/SCK10 8-A P21/SO10 5-A P22/SI10

8-A P40/KR00 to P43/KR03 P60/TO40 5 P61/INT 8 P80/S22 to P85/S17 17-G S0 to S16, S23 17-D

Output

Leave open.

COM0 to COM3 18-B

LC0

−

XT1 Input Connect to VSS. XT2

−

Leave open.

RESET 2 Input

−−

Connect directly to V

or VSS via a resistor.

−

µµµµ

PD78F9328

Figure 3-1. I/O Circuit Type (1/2)

Type 2 Type 5

Output disable

Schmitt-triggered input with hysteresis characteristics.

Input enable

Data

P-ch

IN/OUT

N-ch

Preliminary Product Information U14411EJ1V0PM00

Figure 3-1. I/O Circuit Type (2/2)

Type 5-A Type 8

µµµµ

PD78F9328

Pull-up enable

Data

Output disable

P-ch

N-ch

P-ch

IN/OUT

Data

Output disable

Input enable

Type 8-A Type 17-D

Pull-up enable

Data

P-ch

VLC3

SEG

IN/OUT

Output disable

N-ch

LC0

data

LC2

P-ch P-ch

N-ch

P-ch N-ch

P-ch

IN/OUT

N-ch

P-ch

OUT

N-ch

Type 17-G Type 18-B

Data

P-ch

IN/OUT

Output disable

N-ch

VSS

Input enable

LC0

VLC1

P-ch P-ch

N-ch

P-ch

COM

data

SEG

data

N-ch

LC2

P-ch N-ch

N-ch

LC0

LC1

P-ch

N-ch

P-ch

N-ch

OUT

P-ch

LC2

N-ch

P-ch N-ch

N-ch

Remark

LC1

: V

LC0

× 2/3, V

LC2

LC0

: V

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

4. CPU ARCHITECTURE

4.1 Memory Space

The µPD78F9328 is provided with 64 Kbytes of accessible memory space. Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

F F F F H

Special function registers

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

512 × 8 bits

F D 0 0 H

Data memory

space

F C F F H

F A 1 8 H F A 1 7 H

F A 0 0 H F 9 F F H

8 0 0 0 H

7 F F F H

Reserved

LCD display RAM

24 × 8 bits

7 F F F H

Reserved

Program

memory space

0 0 0 0 H

Flash memory

32 K × 8 bits

0 0 8 0 H 0 0 7 F H

0 0 4 0 H 0 0 3 F H

0 0 1 4 H 0 0 1 3 H

0 0 0 0 H

Program area

CALLT table area

Program area

Vector table area

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

4.2 Data Memory Addressing

The µPD78F9328 is provided with a variety of addressing modes to improve the operability of the memory. In the area that incorporates data memory (FD00H to FFFFH) in particular, specific addressing modes that correspond to the particular functions of an area, such as the special function registers (SFRs), are available. Figure 4-2 shows the data memory addressing modes.

Figure 4-2. Data Memory Addressing Modes

F F F F H

Special function registers (SFRs)

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

SFR addressing

F E 2 0 H F E 1 F H

F D 0 0 H

F C F F H

F A 1 8 H F A 1 7 H

F A 0 0 H F 9 F F H

8 0 0 0 H

7 F F F H

Internal high-speed RAM

512 × 8 bits

Reserved

LCD display RAM

24 × 8 bits

Reserved

Flash memory

32 K × 8 bits

Short direct addressing

Direct addressing

Based addressing

0 0 0 0 H

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

4.3 Processor Registers

4.3.1 Control registers

(1) Program counter (PC)

The PC is a 16-bit register that holds the address information of the next program to be executed.

Figure 4-3. Program Counter Configuration

PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The PSW is an 8-bit register that indicates the status of the CPU according to the results of instruction execution.

Figure 4-4. Program Status Word Configuration

IE Z 0 AC 0 0 1 CY

015

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgement of the CPU.

(b) Zero flag (Z)

This flag is set (1) if the result of an operation is zero; otherwise it is reset (0).

AC is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0).

(d) Carry flag (CY)

CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or add instruction.

(3) Stack pointer (SP)

The SP is a 16-bit register that holds the start address of the stack area. Only the internal RAM area (FD00H to FEFFH) can be specified as the stack area.

Figure 4-5. Stack Pointer Configuration

SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

015

Caution RESET input makes the SP contents undefined, so be sure to initialize the SP before instruction

execution.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

4.3.2 General-purpose registers

PD78F9328 has eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H).

The

These registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (AX, BC, DE, and HL), and can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3).

Figure 4-6. General-Purpose Register Configuration

(a) Absolute register names

16-bit processing

RP3

RP2

RP1

RP0

15 0

(b) Functional register names

16-bit processing

8-bit processing

15 0

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

4.3.3 Special function registers (SFRs)

Special function registers are used as peripheral hardware mode registers and control registers, and are mapped

in the 256-byte space from FF00H to FFFFH.

Note that the bit number of a bit name that is a reserved word in the RA78K0S and defined under the header file

“sfrbit.h” in the CC78K0S appears enclosed in a circle in the register formats. Refer to the register formats in

PERIPHERAL HARDWARE FUNCTIONS

Table 4-1. Special Function Registers (1/2)

FF00H Port 0 P0 FF01H Port 1 P1 FF02H Port 2 P2 FF03H port 4 P4 FF05H Port 6 P6 FF08H Port 8 P8 FF20H Port mode regi ster 0 PM0 FF21H Port mode regi ster 1 PM1 FF22H Port mode regi ster 2 PM2 FF24H Port mode regi ster 4 PM4 FF26H Port mode regi ster 6 PM6 FF28H Port mode regi ster 8 PM8 FF32H Pull-up res i s tor option register B2 PUB2 FF4AH Wat ch timer mode control register WTM FF58H Port func tion register 8 PF8 FF63H 8-bit com pare regi ster 30 CR30 W FF64H 8-bit tim er c ounter 30 TM30 R FF65H 8-bit ti m er m ode control register 30 TMC30 R/W FF66H 8-bit com pare regi ster 40 CR40 FF67H 8-bit H wi dth compare register 40 CRH40 FF68H 8-bit tim er c ounter 40 TM40 R FF69H 8-bit ti m er m ode control register 40 TMC40 R/W FF6AH Carrier generator output control register 40 TCA40 W FF72H Serial operat i on m ode regi ster 10 CSIM10 FF74H Transmis sion/reception shift register 10 SIO10 FFB0H LCD display mode register 0 LCDM0 FFB2H LCD clock control register 0 LCDC0 FFDDH Power-on-cl ear regi ster 1 POCF1

R/W

Bit Unit for Manipulati onAddress Special Function Regist er (SFR) Name S ymbol R/W 1 Bit 8 Bits 16 Bits

√√− √√− √√− √√− √√− √√− √√− √√− √√− √√− √√− √√− √√− √√− √√−

−√−

−√− √√−

−√−

−√− √√− √√− √√− √√− √√− √√− √√−

After

Reset

00H

FFH

00H

Undefined

00H

Undefined

00H

Undefined

00H

Note

00H

This value is 04H only after a power-on-clear reset.

Note

Preliminary Product Information U14411EJ1V0PM00

Table 4-1. Special Function Registers (2/2)

µµµµ

PD78F9328

FFE0H Interrupt request flag register 0 IF0 FFE4H Interrupt mask flag register 0 MK0 FFECH External interrupt m ode regi ster 0 INTM0 FFF0H Subclock oscillation mode register SCKM FFF2H Subclock control register CSS FFF5H Key return mode register 00 KRM00 FFF7H Pull-up resistor option register 0 PU0 FFF9H Watchdog timer mode register WDTM FFFAH Oscillation stabilization time selection register OSTS FFFBH Processor clock control register PCC

Bit Unit for Manipulati onAddress Special Function Regist er (SFR) Name S ymbol R/ W 1 Bit 8 Bits 16 Bits

R/W

√√− √√−

−√− √√− √√− √√− √√− √√−

−√− √√−

After

Reset

00H FFH 00H

04H 02H

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

5.1.1 Port functions

Various kinds of control operations are possible using the ports provided in the

illustrated in Figure 5-1 and their functions are listed in Table 5-1.

A number of alternate functions are also provided, except for those ports functioning as digital I/O ports. Refer to

3. PIN FUNCTIONS

for details of the alternate function pins.

Figure 5-1. Ports

PD78F9328. These ports are

Port 4

Port 6

Port 8

P40

P43

P60 P61

P80

P85

P00

P03

P10 P11

P20

P22

Port 0

Port 1

Port 2

Preliminary Product Information U14411EJ1V0PM00

Table 5-1. Port Functions

Port Name Pin Name Function

Port 0 P00 to P03 This is an I/O port f or whi ch input and output can be specified i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be specifi ed using pull-up resistor option register 0 (PU0).

Port 1 P10, P11 This is an I/O port for whi ch input and output can be specifi ed i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be specifi ed using pull-up resistor option register 0 (PU0).

Port 2 P20 to P22 This is an I/O port f or whi ch input and output can be specified i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be specifi ed using pull-up resistor option register B2 (PUB2).

Port 4 P40 to P43 This is an I/O port f or whi ch input and output can be specified i n 1-bi t units.

When used as an input port, on-chip pull -up resistors can be specifi ed using pull-up

resistor option register 0 (PU0), or key return mode register 00 (KRM 00). Port 6 P60, P61 This is an I/O port for whi ch input and output can be specifi ed i n 1-bi t units. Port 8 P80 to P85 This is an I/O port f or whi ch input and output can be specified i n 1-bi t units.

µµµµ

PD78F9328

Preliminary Product Information U14411EJ1V0PM00

5.1.2 Port configuration

The ports consist of the following hardware.

Table 5-2. Port Configuration

Item Configuration

Control registers Port mode registers (PMm: m = 0 to 2, 4, 6, 8)

Pull-up resistor option registers (PU0, PUB2)

Port function regist er 8 (P F8) Ports Total: 21 (CMOS I/O: 21) Pull-up resistors Total: 13 (software control: 13)

Figure 5-2. Basic Configuration of CMOS Port

PUm

µµµµ

PD78F9328

Internal bus

PU×

PORTm

Selector

PORTm

Output latch

Pmn

PMm

PMmn

P-ch

Pmn

Caution Figure 5-2 shows the basic configuration of a CMOS I/O port. This configuration differs

depending on the functions of alternate function pins. Also, an on-chip pull-up resistor can be connected to port 4 by means of a setting in key return mode register 00 (KRM00).

Remark

PU×: Pull-up resistor option register (× = 0, B2) PMmn: Bit n of port mode register m (m = 0 to 2, 4, 6, 8 n = 0 to 5) Pmn: Bit n of port m RD: Port read signal WR: Port write signal

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5.1.3 Port function control registers

The ports are controlled by the following three types of registers.

Port mode registers (PM0 to PM2, PM4, PM6, PM8)

•

Pull-up resistor option registers (PU0, PUB2)

•

Port function register 8 (PF8)

•

(1) Port mode registers (PM0 to PM2, PM4, PM6, PM8)

Input and output can be specified in 1-bit units. These registers can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When using the port pins as their alternate functions, set the output latch as shown in Table 5-3.

Caution Because P61 functions alternately as an external interrupt input, when the output level

changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode.

µµµµ

PD78F9328

Figure 5-3. Port Mode Register Format

Symbol76543210AddressAfter resetR/W

PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W

PM1111111PM11PM10FF21HFFHR/W

PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W

PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W

PM6111111PM61PM60FF26HFFHR/W

PM8 1 1 PM85 PM84 PM83 PM82 PM81 PM80 FF28H FFH R/W

PMmn Pmn pin input/output mode s el ection

(m = 0 to 2, 4, 6, 8 n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off )

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

Table 5-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions

Alternate FunctionPin Name

Name I/O

P20 SCK10

P21 SO10 Output 0 1 P22 SI10 Input 1 P40 to P43 KR00 to KR03 Input 1 P60 TO40 Output 0 0 P61 INT Input 1 P80 to P85

Note

Remark

S22 to S17

When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH.

: don’t care

Note

Input 1 Output 0 1

Output

××

PM××: Port mode register P××: Port output latch

(2) Pull-up resistor option register 0 (PU0)

This register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4 on a port by port basis. An onchip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the onchip pull-up resistor has been specified using PU0. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PU0. This also applies to alternate-function pins used as output pins. PU0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

××

× ×

Figure 5-4. Format of Pull-Up Resistor Option Register 0

Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/W

PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W

PU0m Port m on-chip pull-up resistor selection

(m = 0, 1, 4) 0 An on-chip pull-up resistor is not connected 1 An on-chip pull-up resistor is connected

Caution Always set bits 2, 3, and 5 to 7 to 0.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(3) Pull-up resistor option register B2 (PUB2)

This register sets whether to use on-chip pull-up resistors for P20 to P22 in bit units. An on-chip pull-up resistor can be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has been specified using PUB2. For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of PUB2. This also applies to alternate-function pins used as output pins. PUB2 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-5. Format of Pull-Up Resistor Option Register B2

Symbol 7 6 5 4 3 <2> <1> <0> Address After reset R/W

PUB2 0 0 0 0 0 PUB22 PUB21 PUB20 FF32H 00H R/W

PUB2n P2n on-chip pull-up resistor s el ection

(n = 0 to 2) 0 An on-chip pull-up resistor is not connected 1 An on-chip pull-up resistor is connected

Caution Always set bits 3 to 7 to 0.

(4) Port function register 8 (PF8)

This register sets the port function of port 8 in 1-bit units. The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according to the setting of PF8. PF8 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-6. Format of Port Function Register 8

Symbol76543210AddressAfter resetR/W

PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W

PF8n P8n port function (n = 0 to 5)

0 Operates as a general-purpose port 1 Operates as an LCD segment signal output

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

5.2 Clock Generator

5.2.1 Clock generator function

The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware. There are two types of system clock oscillators:

Main system clock oscillator (ceramic/crystal resonator)

•

This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or by means of a processor clock control register (PCC) setting. Subsystem clock oscillator

•

This circuit generates a frequency of 32.768 kHz. Oscillation can be stopped using the subclock oscillation mode register (SCKM).

5.2.2 Clock generator configuration

The clock generator consists of the following hardware.

Table 5-4. Clock Generator Configuration

Item Configuration

Control registers Processor clock control register (PCC)

Subclock oscillation mode register (SCKM) Subclock control register (CSS)

Oscillators Main system clock oscillator

Subsystem clock oscillator

Preliminary Product Information U14411EJ1V0PM00

Internal bus

Figure 5-7. Clock Generator Block Diagram

µµµµ

PD78F9328

XT1 XT2

X1 X2

FRC

SCC

Subsystem

clock

oscillatior

Main system

clock

oscillator

STOP

Subclock oscillation mode register (SCKM)

MCC

PCC1

1/2

Watch timer LCD controller/driver

Prescaler

Standby

control

circuit

Clock to peripheral hardware

Wait

control

circuit

CPU clock

CPU

)

Selector

CLS

CSS0

Processor clock control register (PCC)

Subclock control register (CSS)

Internal bus

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

5.2.3 Clock generator control registers

The clock generator is controlled by the following three registers.

Processor clock control register (PCC)

•

Subclock oscillation mode register (SCKM)

•

Subclock control register (CSS)

•

(1) Processor clock control register (PCC)

This register is used to select the CPU clock and set the frequency division ratio. PCC is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 02H.

Figure 5-8. Format of Processor Clock Control Register

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W

MCC Main system clock oscillator operation control

0 Operation enabled 1 Operation stopped

CPU

CSS0 PCC1

00f 01 1×f

The CPU clock is selected by a combination of flag settings in the PCC and CSS registers. (Refer to

Note

CPU clock (f

(0.2 µs) 0.4 µs /22 (0.8 µs)

/2 (61 µs) 122 µs

) selection

5.2.3 (3) Subclock control register (CSS)

Note

Minimum instructi on execution time: 2f

1.6

Cautions 1. Always set bits 0 and 2 to 6 to 0.

2. MCC can be set only when the subsystem clock is selected as the CPU clock. Setting MCC to 1 while the main system clock is operating is invalid.

: Main system clock oscillation frequency

Remarks 1.

f fXT: Subsystem clock oscillation frequency

The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

CPU

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(2) Subclock oscillation mode register (SCKM)

This register is used to select a feedback resistor for the subsystem clock and control the oscillation of the clock. SCKM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-9. Format of Subclock Oscillation Mode Register

Symbol 7 6 5 4 3 2 1 <0> Address After res et R/W

SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W

FRC F eedback resistor selecti on

0 An on-chip feedback resis t or i s used 1 An on-chip feedback resis t or i s not used

SCC Control of subsystem clock oscillator operation

0 Operation enabled 1 Operation stopped

Caution Always set bits 2 to 7 to 0.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(3) Subclock control register (CSS)

This register is used to specify whether the main system or subsystem clock oscillator is selected and to indicate the operating status of the CPU clock. CSS is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-10. Format of Subclock Control Register

Symbol76543210AddressAfter resetR/W

Note

CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H

CLS CPU clock operating status

0 Operating on the output of the (divi ded) main system clock 1 Operating on the output of the subsystem clock

CSS0 Selection of main system clock or subsystem clock oscillator

0 Main system clock oscillator (divided) output 1 Subsystem clock oscillator output

R/W

Bit 5 is read-only.

Note

Caution Always set bits 0 to 3, 6, and 7 to 0.

Preliminary Product Information U14411EJ1V0PM00

5.3 8-Bit Timer 30, 40

5.3.1 Functions of 8-bit timer 30, 40

The 8-bit timer in the

table are possible by means of mode register settings.

PD78F9328 has 2 channels (timer 30 and timer 40). The operation modes in the following

Table 5-5. List of Modes

µµµµ

PD78F9328

Channel Mode 8-bit timer counter mode

(discrete mode) 16-bit timer counter mode

(cascade connection mode) Carrier generator mode PWM output mode –

Timer 30 Timer 40

√√

(1) 8-bit timer counter mode (discrete mode)

The timer can be used for the following functions in this mode.

8-bit resolution interval timer

•

8-bit resolution square wave output (timer 40 only)

•

(2) 16-bit timer counter mode (cascade connection mode)

These timers can be used for 16-bit timer operations via a cascade connection. The timer can be used for the following functions in this mode.

16-bit resolution interval timer

•

16-bit resolution square wave output

•

√

(3) Carrier generator mode

In this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30.

(4) PWM output mode

In this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output.

Preliminary Product Information U14411EJ1V0PM00

5.3.2 Configuration of 8-bit timer 30, 40

8-bit timers 30 and 40 consist of the following hardware.

Table 5-6. Configuration of 8-Bit Timer 30, 40

Item Configuration Timer counter 8 bits × 2 (TM30, TM40) Registers Com pare regi sters: 8 bits × 3 (CR30, CR40, CRH40) Timer outputs 1 (TO40) Control registers 8-bit timer mode control register 30 (TMC30)

8-bit timer mode control register 40 (TMC40) Carrier generator output control register 40 (TCA40) Port mode register 6 (PM6)

µµµµ

PD78F9328

Preliminary Product Information U14411EJ1V0PM00

Figure 5-11. Block Diagram of Timer 30

Internal bus

8-bit timer mode control registedr 30

(TMC30)

TCE30

Preliminary Product Information U14411EJ1V0PM00

Bit 7 of TM40

(from Figure

Timer 40 interrupt request signal

Carrier clock (in carrier generator mode)

(in other than carrier generator mode)

(from Figure 5-12 (B))

or timer 40 output signal

(from Figure 5-12 (C))

5-12 (A))

fX/2 fX/2

6 8

Selector

From Figure 5-12 (D) Count operation start signal (for cascade connection)

TCL301

Selector

TCL300

TMD300

Decoder

Cascade connection mode

8-bit compare register 30 (CR30)

Match

8-bit timer counter 30 (TM30)

Clear

Selector

From Figure 5-12 (E)

Timer 40 match signal (in cascade connection mode)

OVF

To Figure 5-12 (G) Timer 30 match signal (in carrier generator mode)

Internal reset signal

INTTM30

µµ

PD78F9328

To Figure 5-12 (F)

Timer 30 match signal (in cascade connection mode)

8-bit timer mode control register 40 (TMC40)

TCE40

TCL402 TCL401 TCL400

TMD401

TMD400

Figure 5-12. Block Diagram of Timer 40

Internal bus

TOE40

8-bit H width compare register 40 (CRH40)

Carrier generator output control register 40 (TCA40)

8-bit compare register 40 (CR40)

RMC40

NRZB40

NRZ40

Decoder

Preliminary Product Information U14411EJ1V0PM00

fX/2

X 2

fX/2

Prescaler

Selector

To Figure 5-11 (D)

Count operation start signal to timer 30 (in cascade connection mode)

Carrier generator mode

PWM mode

Cascade connection mode

8-bit timer counter 40 (TM40)

Clear

Match

Selector

F/F

OVF

Reset

To Figure 5-11 (E)

TM40 timer counter match signal (in cascade connection mode)

Output control circuit

Note

From Figure 5-11 (G)

Timer counter match signal from timer 30 (in carrier generator mode)

TO40/P60

To Figure 5-11 (C)

Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)

To Figure 5-11 (A)

Bit 7 of TM40 (in cascade connection mode)

Internal reset signal INTTM40

To Figure 5-11 (B) Timer 40 interrupt request signal

count clock input signal to TM30

µµ

PD78F9328

Note Refer to Figure 5-13 for details.

To Figure 5-11 (F)

TM30 match signal (in cascade connection mode)

Figure 5-13. Block Diagram of Output Control Circuit (Timer 40)

µµµµ

PD78F9328

TOE40

F/F

RMC40

Carrier generator mode

NRZ40

Selector

P60

output latch

PM60

TO40/P60

Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode)

(1) 8-bit compare register 30 (CR30)

A value specified in CR30 is compared with the count value in 8-bit timer counter 30 (TM30), and if they match, an interrupt request (INTTM30) is generated. CR30 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined.

Caution CR30 cannot be used in carrier generator mode or PWM output mode.

(2) 8-bit compare register 40 (CR40)

A value specified in CR40 is compared with the count value in 8-bit timer counter 40 (TM40), and if they match, an interrupt request (INTTM40) is generated. When operating as a 16-bit timer in cascade connection with TM30, an interrupt request (INTTM40) is only generated if both CR30 and TM30, and CR40 and TM40 match simultaneously (INTTM30 is not issued). CR40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined.

(3) 8-bit H width compare register (CRH40)

In carrier generator mode or PWM output mode, a timer output high-level width can be set by writing a value to CRH40. CRH40 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined.

Preliminary Product Information U14411EJ1V0PM00

(4) 8-bit timer counter 30, 40 (TM30, TM40)

This is an 8-bit register for counting the count pulses. TM30 and TM40 can be read with a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to 00H. The conditions under which TM30 and TM40 are cleared to 00H are listed below.

(a) Discrete mode

(i) TM30

Upon a reset

•

When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0

•

Upon a match between TM30 and CR30

•

If the TM30 count value overflows

•

(ii) TM40

Upon a reset

•

When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0

•

Upon a match between TM40 and CR40

•

If the TM40 count value overflows

•

µµµµ

PD78F9328

(b) Cascade connection mode (TM30 and TM40 cleared to 00H simultaneously)

Upon a reset

•

When the TCE40 flag is cleared to 0

•

Upon a simultaneous match between TM30 and CR30, and TM40 and CR40

•

If the TM30 and TM40 count values overflow simultaneously

•

Upon a reset

•

When the TCE40 flag is cleared to 0

•

Upon a match between TM40 and CR40

•

Upon a match between TM40 and CRH40

•

If the TM40 count value overflows

•

Preliminary Product Information U14411EJ1V0PM00

5.3.3 8-bit timer 30, 40 control registers

8-bit timers 30 and 40 are controlled by the following 4 registers.

8-bit timer mode control register 30 (TMC30)

•

8-bit timer mode control register 40 (TMC40)

•

Carrier generator output control register 40 (TCA40)

•

Port mode register 6 (PM6)

•

µµµµ

PD78F9328

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(1) 8-bit timer mode control register 30 (TMC30)

This register is used to control the timer 30 count clock and operation mode settings. TMC30 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-14. Format of 8-Bit Timer Mode Control Register 30

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W

TCE30

0 TM30 count v al ue cleared and operation stopped 1 Count operation st arts

TCL301 TCL300 Timer 30 count clock selection

/26 (78.1 kHz)

00 01 1 0 Timer 40 match signal 1 1 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator

TMD300 TMD401 TMD400

0 0 0 Disc ret e m ode 1 0 1 Cascade c onnection mode 0 1 1 Carrier generator mode 0 1 0 PWM output mode

Other than above Setting prohibited

/28(19.5 kHz)

mode)

TM30 count control operation

Timer 30, timer 40 operation mode sel ection

Note 1

Note 2

Notes 1.

The TCE30 setting will be ignored in cascade mode because in this case the count operation is controlled by TCE40 (bit 7 of TMC40). The operation mode selection is made using a combination of TMC30 and TMC40 register settings.

Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count

clock.

: Main system clock oscillation frequency

Remarks 1.

f The parenthesized values apply to operation at fX = 5.0 MHz

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(2) 8-bit timer mode control register 40 (TMC40)

This register is used to control the timer 40 count clock and operation mode settings. TMC40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-15. Format of 8-Bit Timer Mode Control Register 40

Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W

TCE40

0 TM40 count v al ue cleared and operation stopped (in cascade c onnection mode, the count value of TM 30 i s

cleared at the same time)

1 Count operation st arts (in cascade connection m ode, the count operation of TM30 starts at the same time)

TCL402 TCL401 TCL400 Timer 40 count clock selec tion

000f 001 010f 011 100 101

Other than above Setting prohibited

TMD300 TMD401 TMD400

0 0 0 Disc ret e m ode 1 0 1 Cascade c onnection mode 0 1 1 Carrier generator mode 0 1 0 PWM output mode

Other than above Setting prohibited

(5 MHz)

/22 (1.25 MHz)

/2 (2.5 MHz)

/22 (1.25 MHz)

/23 (625 kHz)

/24 (313 kHz)

TM40 count control operation

Timer 30, timer 40 operation mode sel ection

Note 1

Note 2

TOE40 Timer output control

0 Output disabl ed (port mode) 1 Output enabled

Notes 1.

: Main system clock oscillation frequency

Remarks 1.

f The parenthesized values apply to operation at fX = 5.0 MHz

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(3) Carrier generator output control register 40 (TCA40)

This register is used to set the timer output data in the carrier generator mode. TCA40 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-16. Format of Carrier Generator Output Control Register 40

Symbol76543<2><1><0>AddressAfter resetR/W

TCA4000000RMC40NRZB40NRZ40FF6AH00HW

RMC40 Remote controller output control

0 When NRZ40 = 1, a carrier puls e i s output to the TO40/P60 pin 1 When NRZ40 = 1, a high level i s output to the TO40/P60 pin

NRZB40 This bit stores the data that NRZ40 will output next. Data is t rans ferred to NRZ40 upon the generation of a

timer 30 match signal.

NRZ40 No return, zero data

0 A low level i s output (the carrier clock i s stopped) 1 A carrier puls e i s output

(4) Port mode register 6 (PM6)

This register is used to set port 6 to input or output in 1-bit units. When the TO40/P60 pin is used as a timer output, set the PM60 and P60 output latches to 0. PM6 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH.

Figure 5-17. Format of Port Mode Register 6

Symbol76543210AddressAfter resetR/W

PM6111111PM61PM60FF26HFFHR/W

PM6n Input/output mode of pin P6n (n = 0, 1)

0 Output mode (output buffer on) 1 Input mode (output buffer off)

Preliminary Product Information U14411EJ1V0PM00

5.4 Watch Timer

5.4.1 Watch timer functions

The watch timer has the following functions.

Watch timer

•

Interval timer

•

The watch and interval timers can be used at the same time. Figure 5-18 shows a block diagram of the watch timer.

Figure 5-18. Watch Timer Block Diagram

Clear

fX/2

Selector

9-bit prescaler

µµµµ

PD78F9328

5-bit counter INTWT

Clear

Selector

WTM7 WTM6 WTM5 WTM4 WTM1

Watch timer mode control register (WTM)

Internal bus

INTWTI

WTM0

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(1) Watch timer

An interrupt request (INTWT) is generated at 0.5-second intervals using the 4.19-MHz main system clock or

32.768-kHz subsystem clock.

Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second

interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWTI) at preset intervals.

Table 5-7. Interval Time of Interval Timer

Interval Time At f

24 × 1/f

25 × 1/f

26 × 1/f

27 × 1/f

28 × 1/f

29 × 1/f

Remarks 1.

: Watch timer clock frequency (fX/27 or fXT)

f fX: Main system clock oscillation frequency fXT: Subsystem clock oscillation frequency

= 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation

409.6 µs 488 µs 488 µs

819.2 µs 977 µs 977 µs

1.64 ms 1.95 ms 1.95 ms

3.28 ms 3.91 ms 3.91 ms

6.55 ms 7.81 ms 7.81 ms

13.1 ms 15.6 ms 15.6 ms

5.4.2 Watch timer configuration

The watch timer consists of the following hardware.

Table 5-8. Watch Timer Configuration

Item Configuration Counter 5 bits × 1 Prescaler 9 bits × 1 Control register Watch timer mode c ontrol register (WTM)

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µµµµ

PD78F9328

5.4.3 Watch timer control register

The following register controls the watch timer.

Watch timer mode control register (WTM)

•

(1) Watch timer mode control register (WTM)

This register is used to enable/disable the count clock and operation of the watch timer and set the interval time of the prescaler and operation control of the 5-bit counter. WTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-19. Format of Watch Timer Mode Control Register

Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W

WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W

WTM7 Watch timer count clock (fW) selection

/27(39.1 kHz)

0 1fXT(32.768 kHz)

WTM6 WTM5 WTM4 Prescaler interval time selection

000 001 010 011 100 101

Other than above Setting prohibited

WTM1 5-bit counter operation control

0 Cleared after operation stopped 1Start

WTM0 Watch timer operat i on enabl e

0 Operation s topped (both prescaler and timer cleared) 1 Operation enabled

: Watch timer clock frequency (fX/27 or fXT)

Remarks 1.

f fX: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency

The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

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µµµµ

PD78F9328

5.5 Watchdog Timer

5.5.1 Watchdog timer functions

The watchdog timer has the following functions.

(1) Watchdog timer

The watchdog timer is used to detect a program runaway. If a runaway is detected, either a non-maskable interrupt or the RESET signal can be generated.

(2) Interval timer

The interval timer is used to generate interrupts at preset intervals.

5.5.2 Watchdog timer configuration

The watchdog timer consists of the following hardware.

Table 5-9. Watchdog Timer Configuration

Item Configuration Control register Watchdog timer mode register (WDTM)

Figure 5-20. Watchdog Timer Block Diagram

Internal bus

WDTMK

WDTIF

7-bit counter

Clear

RUN

Control circuit

WDTM4 WDTM3

Watchdog timer mode register (WDTM)

INTWDT maskable interrupt request

RESET INTWDT

non-maskable interrupt request

Internal bus

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µµµµ

PD78F9328

5.5.3 Watchdog timer control register

The watchdog timer is controlled by the following register.

Watchdog timer mode register (WDTM)

•

(1) Watchdog timer mode register (WDTM)

This register is used to set the watchdog timer operation mode and whether to enable or disable counting. WDTM is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-21. Format of Watchdog Timer Mode Register

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W

WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W

RUN

0 Counting stopped 1 Counter cleared and counting starts

WDTM4 WDTM3

0 0 Operation stopped 01 1 0 Watchdog timer mode 1 (when an overflow occurs, a non-maskable i nterrupt is generated) 1 1 Watchdog timer mode 2 (when an overflow occurs, a reset operation i s activated)

Notes 1.

Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Consequently, once

Interval timer mode (when an overf l ow occurs, a maskable interrupt i s generated)

Watchdog timer operation selec tion

Watchdog timer operation mode sel ection

Note 1

Note 2

Note 3

counting begins, it cannot be stopped by any means other than RESET input.

Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software.

The interval timer starts operating as soon as the RUN bit is set to 1.

Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time

will be up to 0.8% shorter than the time specified by the watchdog timer clock selection register.

2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant rewriting ends.

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µµµµ

PD78F9328

5.6 Serial Interface 10

5.6.1 Functions of serial interface 10

Serial interface 10 has the following two modes.

Operation stopped mode

•

3-wire serial I/O mode

•

(1) Operation stopped mode

This mode is used to minimize power consumption when serial transfer is not performed.

(2) 3-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)

This mode is used to transmit 8-bit data, using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). As 3-wire serial I/O mode supports simultaneous transmission and reception, the time required for data processing can be reduced. In 3-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with the MSB or LSB, allowing serial interface 10 to be connected to any device regardless of whether that device is designed for MSB-first or LSB-first transmission. 3-wire serial I/O mode is effective for connecting peripheral I/O circuits and display controllers having conventional clock synchronous serial interfaces, such as those of the 75XL, 78K, and 17K Series devices.

5.6.2 Configuration of serial interface 10

Serial interface 10 consists of the following hardware.

Table 5-10. Configuration of Serial Interface 10

Item Configuration Register Transmission/reception shift regi ster 10 (SIO10) Control register Serial operation mode regis ter 10 (CSIM10)

(1) Transmission/reception shift register 10 (SIO10)

This is an 8-bit register used for parallel/serial data conversion and for serial transmission or reception in synchronization with the serial clock. SIO10 is set using an 8-bit memory manipulation instruction. RESET input makes this register undefined.

Preliminary Product Information U14411EJ1V0PM00

SI10/P22

SO10/P21

PM21

Figure 5-22. Block Diagram of Serial Interface 10

Serial operation mode register 10

CSIE10

(CSIM10)

TPS101

TPS100

DIR10

Internal bus

CSCK10

Transmission/reception shift

SCK10/P20

PM20

Serial clock counter

Clock control

circuit

F/F

Selector

Interrupt request

generator

fX/2 fX/2

Selector

TPS101

TPS100

INTCSI10

2 3

µµ

PD78F9328

µµµµ

PD78F9328

5.6.3 Control register for serial interface 10

Serial interface 10 is controlled by the following register.

Serial operation mode register 10 (CSIM10)

•

Figure 5-23. Format of Serial Operation Mode Register 10

Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W CSIM10 CSIE10 0 TPS101 TPS 100 0 DI R10 CSCK10 0 FF72H 00H R/W

CSIE10 3-wire serial I/O mode operation c ontrol

0 Operat i on stopped 1 Operat i on enabl ed

TPS101 TPS100 Selecti on of count clock when internal clock selected

/22 (1.25 MHz)

00 01

Other than above Setting prohi bi t ed

/23 (625 kHz)

DIR10 First-bit specification

0MSB 1LSB

CSCK10 SIO10 clock selection

0 External clock pulse input to the SCK10 pin 1 Internal clock selected wi t h TPS100, TPS101

Cautions 1. Bits 0, 3 and 6 must be fixed to 0.

2. Be sure to switch to operation mode after stopping the serial transmission/reception operation.

: Main system clock oscillation frequency

Remarks 1.

f The parenthesized values apply to operation at fX = 5.0 MHz.

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Table 5-11. Operation Mode Settings for Serial Interface 10

(1) Operation stopped mode

µµµµ

PD78F9328

CSIM10

CSIE10

DIR10

CSCK10

(2) 3-wire serial I/O mode

CSIM10

CSIE10

Notes 1.

DIR10

CSCK10

Can be used freely as a port Can be used as P22 (CMOS I/O) only when transmitting

PM22

Note 1

PM22

Note 2

P22

PM21

Note 1

P22

PM210P211PM20

Note 2

P21

Note 1

PM20

Note 1

P20

Note 1

P20

First

Bit

−

Shift

Clock

−

P22/SI10

Pin Function

P21/SO10

Pin Function

P20/SCK10

Pin Function

P22 P21 P20

Setting prohibitedOther than above

First

MSB

Bit

Shift

Clock

External clock

Internal

P22/SI10

Pin Function

Note 2

SI10

P21/SO10

Pin Function

SO10 (CMOS output)

P20/SCK10

Pin Function

SCK10 input

SCK10 output

clock

LSB

External

SCK10 input

clock

Internal

SCK10 output

clock

Setting prohibitedOther than above

Remark

: don’t care

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

5.7 LCD Controller/Driver

5.7.1 LCD controller/driver functions

The LCD controller/driver incorporated in the

(1) Segment and common signals based on the automatic reading of the display data memory can be

automatically output (2) Four types of frame frequencies are selectable (3) 24 segment signal outputs (S0 to S23), 4 common signal outputs (COM0 to COM3) (4) Operation with a subsystem clock is possible

The maximum number of displayable pixels is shown in Table 5-12 below.

Table 5-12. Maximum Number of Display Pixels

Bias Method Time Di vision Common Si gnal s Used Maximum Number of Di splay Pixels

1/3 4 COM0 to COM3 96 (24 segments × 4 commons)

PD78F9328 has the following features.

The LCD panel of the figure

Note

5.7.2 LCD controller/driver configuration

The LCD controller/driver consists of the following hardware.

Table 5-13. Configuration of LCD Controller/Driver

Item Configuration

Display outputs Segment signals: 24

Common signals: 4

Control registers LCD display mode register 0 (LCDM0)

LCD clock control register 0 (LCDC0) Port function regist er 8 (P F8)

consists of 12 rows with 2 segments per row.

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The correspondence with the LCD display RAM is shown in Figure 5-24 below.

Figure 5-24. Correspondence with LCD Display RAM

Address Bit Segment

76543210 FA17H 0 0 0 0 FA16H 0 0 0 0 FA15H 0 0 0 0 FA14H 0 0 0 0 FA13H 0 0 0 0 FA12H 0 0 0 0 FA11H 0 0 0 0 FA10H 0 0 0 0 FA0FH 0000 FA0EH 0000 FA0DH 0000 FA0CH 0000 FA0BH 0000 FA0AH 0000 FA09H 0 0 0 0 FA08H 0 0 0 0 FA07H 0 0 0 0 FA06H 0 0 0 0 FA05H 0 0 0 0 FA04H 0 0 0 0 FA03H 0 0 0 0 FA02H 0 0 0 0 FA01H 0 0 0 0 FA00H 0 0 0 0

→ → → → → → → → → → → → → → → → → → → → → → → →

S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

µµµµ

PD78F9328

Remark

Common↑COM3↑COM2↑COM1↑COM0

Bits 4 to 7 are fixed to 0.

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Figure 5-25. LCD Controller/Driver Block Diagram

Internal bus

LCD clock control register 0 (LCDC0)

LCDC03 LCDC02

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X/2

fX/2

fXT

LCDC01

fCLK

Selector

fCLK

LCDC00

Prescaker

fCLK

LCDON0

fCLK

LCD clock

selection

circuit

LCD display mode register 0 (LCDM0)

LIPS0

VAON0

fLCD

PF85

PF84

Port function register 8 (PF8)

PF83

PF82 PF80

PF81

Timing

controller

FA00H

LCDON0

Display data memory

32106574

3210

Selector

. . . .

LCDON0

FA11H

32106574

3210

Selector

. . .

FA16H

LCDON0

32106574

3210

Selector

FA17H

LCDON0

3210654

3210

Selector

LCD drive voltage control circuit

1 3

VLC0

RLCD

VLC0

RLCD

VSS

RLCD

VLC0

Common driver

COM0 COM1 COM2 COM3

Segment

driver

PF85

. . . . . . . . . .

Segment

driver

S17/P85

. . . . .

PF80

Segment

driver

S22/P80

Segment

driver

S23

µµ

PD78F9328

µµµµ

PD78F9328

5.7.3 LCD controller/driver control registers

The LCD controller/driver is controlled by the following three registers.

LCD display mode register 0 (LCDM0)

•

LCD clock control register 0 (LCDC0)

•

Port function register 8 (PF8)

•

(1) LCD display mode register 0 (LCDM0)

This register is used to enable/disable operation, and set the operation mode and the supply of power for LCD drive. LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-26. Format of LCD Display Mode Register 0

Symbol <7> <6> 5 <4> 3 2 1 0 Address After res et R/W LCDM0 LCDON0 VAON0 0 LIPS0 0 0 0 0 FFB0H 00H R/W

LCDON0 LCD display enable/disable

0 Display off (all segment outputs are unselected for signal output) 1 Display on

VAON0

0 No internal boos ter (for 2.7- to 5.5-V display) 1 Internal boos ter enabled (for 1.8- to 5.5-V display )

LIPS0

0 Power not supplied for LCD drive 1 Power suppl i ed for LCD drive

To reduce power consumption when the LCD display is not being used, set VAON0 and LIPS0 to 0.

Note

LCD controller/driver operation m ode

Supply of power for LCD drive

Note

Cautions 1. Always set bits 0 to 3 and 5 to 0.

2. Always manipulate VAON0 after turning off the LCD display by setting LIPS0 and LCDON0 to 0.

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µµµµ

PD78F9328

(2) LCD clock control register (LCDC0)

This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of LCD clock time divisions. LCDC0 is set using a 1 - bit or 8-bit memory manipula t ion instruction. RESET input sets this register to 00H.

Figure 5-27. Format of LCD Clock Control Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W

LCDC03 LCDC02

Internal clock (f

00fXT(32.768 kHz)

/25(156.3 kHz)

01 10 11

/26(78.1 kHz)

/27(39.1 kHz)

LCDC01 LCDC00 LCD clock (f

CLK

00 01 10 11

Select f

Note

Remarks 1.

CLK

so that a clock of at least 32 kHz is set for the internal clock f

fX: Main system clock oscillation frequency

fXT: Subsystem clock oscillation frequency The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz

Caution Always set bits 4 to 7 to 0.

CLK

) selection

LCD

) selection

Note

CLK

Examples of the frame frequencies when the internal clock is fXT (32.768 kHz) are shown in Table 5-14 below.

Table 5-14. Frame Frequency (Hz)

Time Division

LCD Clock (f

LCD

)

(64 Hz)

4 163264128

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(128 Hz)

(256 Hz)

(512 Hz)

µµµµ

PD78F9328

(3) Port function register 8 (PF8)

This register is used to select whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose ports. PF8 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 5-28. Format of Port Function Register 8

Symbol76543210AddressAfter resetR/W

PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W

PF8n Port function of P8n (n = 0 to 5)

0 Operates as a general-purpose port 1 Operates as an LCD segment signal output

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µµµµ

PD78F9328

6. INTERRUPT FUNCTION

6.1 Interrupt Types

Two types of interrupts are supported.

(1) Non-maskable interrupts

Non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled. These interrupts take precedence over all other interrupts and are not subject to interrupt priority control. A non-maskable interrupt causes the generation of the standby release signal An interrupt from the watchdog timer is the only non-maskable interrupt source supported in the µPD78F9328.

(2) Maskable interrupts

Maskable interrupts are subject to mask control. If two or more maskable interrupts occur simultaneously, the default priority listed in Table 6-1 applies. A maskable interrupt causes the generation of the standby release signal. Maskable interrupts from 2 external and 6 internal sources are supported in the µPD78F9328.

6.2 Interrupt Sources and Configuration

The µPD78F9328 supports a total of 9 maskable and non-maskable interrupt sources (see

Table 6-1

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Table 6-1. Interrupt Sources

µµµµ

PD78F9328

Non-maskable

Maskable

Notes 1.

Default priority is the priority order when more than one maskable interrupt request is generated at the

Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in

Note 1

Priority

−

0 INTWDT Watchdog timer overflow (with

1 INTP0 Pin input edge detection External 0006H (C) 2 INTCSI10 End of serial interface 10 3-wire

3 INTWT Watch timer interrupt 000AH 4 INTTM30 Generation of 8-bit timer 30

5 INTTM40 Generation of 8-bit timer 40

6 INTKR00 Key return signal detection External 0010H (C) 7 INTWTI Watch timer interval timer

Name Trigger

INTWDT Watchdog timer overflow (with

Interrupt SourceInterrupt Type Default

watchdog timer mode 1 selected)

interval timer mode selected)

SIO transfer reception

matching signal

interrupt

Internal/ External

Internal 0004H

Internal

Internal 0012H (B)

Vector Table

Address

0008H

000CH

000EH

same time. 0 is the highest priority and 7 is the lowest.

Figure 6-1

Basic

Configuration

Type

Note 2

(A)

(B)

Remark

Only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be selected.

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Figure 6-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

µµµµ

PD78F9328

Interrupt request

(B) Internal maskable interrupt

Interrupt request

Internal bus

Vector table address generator

Standby release signal

Vector table address generator

Standby release signal

INTM0, KRM00

Edge

Interrupt request

detection circuit

INTM0: External interrupt mode register 0 KRM00: Key return mode register 00 IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag

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Vector table address generator

Standby release signal

6.3 Interrupt Function Control Registers

Interrupts are controlled by the following five registers.

Interrupt request flag register 0 (IF0)

•

Interrupt mask flag register 0 (MK0)

•

External interrupt mode register 0 (INTM0)

•

Program status word (PSW)

•

Key return mode register 00 (KRM00)

•

Table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags.

Table 6-2. Interrupt Request Signals and Corresponding Flags

Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag

INTWDT INTP0 INTCSI0 INTWT INTTM30 INTTM40 INTKR00 INTWTI

WDTIF PIF0 CSIIF0 WTIF TMIF30 TMIF40 KRIF00 WTIIF

WDTMK PMK0 CSIMK0 WTMK TMMK30 TMMK40 KRMK00 WTIMK

µµµµ

PD78F9328

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

(1) Interrupt request flag register 0 (IF0)

An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed. IF0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 6-2. Format of Interrupt Request Flag Register 0

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After res et R/W

IF0 WTIIF KRIF00 TMIF40 TMIF30 WTIF CSIIF0 PIF0 WDTIF FFE0H 00H R/W

××IF× Interrupt request f l ag

0 No interrupt request signal generated 1 An interrupt request signal is generated and an interrupt request made

Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an

interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2.

2. Because P61 functions alternately as an external interrupt, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before using the port in output mode.

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µµµµ

PD78F9328

(2) Interrupt mask flag register 0 (MK0)

Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH.

Figure 6-3. Format of Interrupt Mask Flag Register 0

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address After res et R/W

MK0 WTIMK KRMK00 TMMK40 TMMK30 WTMK CSIMK0 PMK0 WDTMK FFE4H FFH R/W

××MK Interrupt servicing control

0 Interrupt servicing enabled 1 Interrupt servicing disabled

Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to

read the WDTMK flag results in an undefined value being detected.

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µµµµ

PD78F9328

(3) External interrupt mode register 0 (INTM0)

This register is used to specify the valid edge for INTP0. INTM0 is set using an 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 6-4. Format of External Interrupt Mode Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W

ES01 ES 00 INTP0 valid edge selection

0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibit ed 1 1 Both rising and falling edges

Cautions 1. Always set bits 0, 1, and 4 to 7 to 0.

2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts. To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt mask flag (PMK0).

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µµµµ

PD78F9328

(4) Program status word (PSW)

The program status word is used to hold the instruction execution results and the current status of the interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW. The PSW can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically saved to the stack, and the IE flag is reset (0). RESET input sets the PSW to 02H.

Figure 6-5. Program Status Word Configuration

Symbol After reset

76543210

IE Z 0 AC 0 0 1 CYPSW

0 1

Disabled Enabled

Interrupt acknowledgement enable/disable

02H

Used in the execution of ordinary instructions

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µµµµ

PD78F9328

(5) Key return mode register 00 (KRM00)

This register is used to set the pin that is to detect the key return signal (rising edge of port 4). KRM00 is set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H.

Figure 6-6. Format of Key Return Mode Register 00

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W KRM00 0 0 0 0 0 0 0 KRM000 FFF5H 00H R/W

KRM000 Key return signal detection control

0 Key return signal not detected 1 Key return signal detected (port 4 falling edge detection)

Cautions 1. Always set bits 1 to 7 to 0.

2. Before setting KRM00, set (1) bit 6 (KRMK00) of MK0 to disable interrupts. To enable interrupts, clear (0) KRMK00 after clearing (0) bit 6 (KRIF00) of IF0.

3. On-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (P40 to P43). Although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged.

P40/KR00 P41/KR01 P42/KR02 P43/KR03

Note

Figure 6-7. Block Diagram of Falling Edge Detection Circuit

Key return mode register 00 (KRM00)

Note

Falling edge detection circuit

Selector

KRMK00

For selecting the pin to be used as falling edge input.

KRIF00 setting signal

Standby release signal

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µµµµ

PD78F9328

7. STANDBY FUNCTION

7.1 Standby Function

A standby function is incorporated to minimize the system’s power consumption. There are two standby modes:

HALT and STOP.

The HALT and STOP modes are selected using the HALT and STOP instructions.

(1) HALT mode

In this mode, the CPU operating clock is stopped. The average current consumption can be reduced by intermittent operation combining this mode with the normal operation mode.

(2) STOP mode

In this mode, main system clock oscillation is stopped. All operations performed with the main system clock are suspended, thus minimizing power consumption.

Caution When shifting to STOP mode, execute the STOP instruction after first stopping the operation

of the hardware.

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Table 7-1. Operation Statuses in HALT Mode

µµµµ

PD78F9328

Item

HALT Mode Operation Status During M ai n

System Clock Operat i on

Subsystem Clock

Operating

Subsystem Clock

Stopped

HALT Mode Operation Status During S ub system

Clock Operation

Main System Clock

Operating

Main System Clock

Stopped Main system clock Can be oscillated Oscillation stopped CPU Operation stopped Ports (output latches ) Status before HALT mode setti ng retained 8-bit timer 30, 40 Operable Operation stopped Watch timer Operable

Operable

Note 1

Operable

Note 2

Watchdog timer Operable Operation stopped Power-on-clear circuit Operable Key return circuit Operabl e Serial interface 10 Operable LCD controller/driver External interrupts

Notes 1.

Operation is enabled when the main system clock is selected

Operation is enabled when the subsystem clock is selected

Operation is enabled only when an external clock is selected

The HALT instruction can be set after display instruction execution

Operation is enabled only for a maskable interrupt that is not masked

Operable Operable

Note 4

Note 5

Operable

Notes 1, 4

Operable

Note 4

Operable Operable

Note 3

Notes 2, 4

Table 7-2. Operation Statuses in STOP Mode

STOP Mode Operation Status Duri ng M ai n System Clock OperationItem

Subsystem Clock Operating Subsystem Clock Stopped Main system clock Oscillation stopped CPU Operation stopped Ports (output latches ) Status before STOP mode set t i ng retained 8-bit timer 30, 40 Operati on stopped Watch timer

Operable Watchdog timer Operation stopped Power-on-clear circuit Operable Key return circuit Operabl e Serial interface 10 LCD controller/driver External interrupts

Notes 1.

Operation is enabled when the subsystem clock is selected.

Operation is enabled only when an external clock is selected.

Operation is enabled only for a maskable interrupt that is not masked

Operable

Note 1

Note 2

Note 1

Note 3

Operation stopped

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

7.2 Standby Function Control Register

The oscillation stabilization time selection register (OSTS) is used to control the wait time from the time STOP

mode is released by an interrupt request until oscillation stabilizes.

OSTS is set using an 8-bit memory manipulation instruction. RESET input sets this register to 04H. Note that the time required for oscillation to stabilize after RESET input will

be 215/fX, rather than 217/fX.

Figure 7-1. Format of Oscillation Stabilization Time Selection Register

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W

OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection

/fX(819 µs)

000 010 100

Other than above Setting prohibited

/fX(6.55 ms)

/fX(26.2 ms)

Caution The wait time required after releasing STOP mode does not include the time (“a” in the following

figure) required for the clock oscillation to restart after STOP mode is released, regardless of whether STOP mode is released by RESET input or interrupt.

STOP mode release

X1 pin voltage waveform

Remarks 1.

: Main system clock oscillation frequency

The parenthesized values apply to operation at fX = 5.0 MHz.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

8. RESET FUNCTION

8.1 Reset Function

The µPD78F9328 can be reset using the following three signals.

(1) External reset signal input via RESET pin (2) Internal reset by watchdog timer runaway time detection (3) Internal reset using power-on-clear circuit (POC)

The external and internal reset signals are functionally equivalent. When RESET is input, program execution

begins from the addresses written at addresses 0000H and 0001H.

If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.

If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins once the oscillation stabilization time (215/fX) has elapsed. A reset sequence caused by a watchdog timer overflow is terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time (215/fX).

Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10

µµµµ

2. When a reset is used to release STOP mode, the data of when STOP mode was entered is retained during the reset sequence, except for the port pins, which are in the high-impedance state.

Figure 8-1. Reset Function Block Diagram

RESET

Count clock

Power-on-clear circuit

Reset control circuit

Watchdog timer

Stop

Overflow

Reset signal

Interrupt function

Preliminary Product Information U14411EJ1V0PM00

µµµµ

Table 8-1. Status of Hardware After Reset

Hardware Status After Reset

Program counter (PC)

Stack pointer (SP) Undefined Program status word (PSW) 02H RAM

Ports (P0 to P2, P4, P6, P8) (output latches) 00H Port mode registers (PM0 to PM2, PM4, PM6, PM 8) FFH Port function regist er 8 (P F8) 00H Pull-up resistor option registers (PU0, PUB2) 00H Processor clock control register (PCC) 02H Subclock oscillation mode register (SCKM) 00H Subclock control register (CSS) 00H Oscillation stabilization time selection register (OSTS) 04H 8-bit timer 30, 40

Watch timer Mode control register (WTM) 00H Watchdog timer Mode regist er (WDTM ) 00H

Power-on-clear circuit Power-on-clear register 1 (POCF1) Interrupts

Note 1

Data memory General-purpose registers

Timer counters (TM30, TM40) 00H Compare registers (CR30, CR40, CRH40) Undefined Mode control registers (TMC30, TM C40) 00H Carrier generator output control register 00H

Serial operation mode register 10 (CSIM10) 00HSerial interface 10 Transmission/recept i on s hi ft register 10 (SIO10) Undefined Display mode register 0 (LCDM 0) 00HLCD controller/driver Clock control register 0 (LCDC0) 00H

Request flag register 0 (IF0) 00H Mask flag register 0 (MK0) FFH External interrupt mode regis ter 0 (INTM0) 00H Key return mode register 00 (KRM00) 00H

Contents of reset vector table (0000H, 0001H) set

Undefined Undefined

00H

Note 3

PD78F9328

Note 2

Notes 1.

While a reset signal is being input, and during the oscillation stabilization period, only the contents of

the PC will be undefined; the remainder of the hardware will be the same state as after reset.

In standby mode, RAM enters the hold state after reset.

The value is 04H only after a power-on-clear reset.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

8.2 Power Failure Detection Function

When a reset is generated via the power-on-clear circuit, bit 2 (POCOF1) of the power-on-clear register (POCF1) is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after program execution has started from address 0000H), a power failure can be detected by detecting POCOF1.

Figure 8-2. Format of Power-on-Clear Register 1

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

Note

POCF1 0 0 0 0 0 POCOF1 0 0 FFDDH

POCOF1 Power-on-clear generation status detection

0 Power-on-clear not generated, or cleared by write operat i on 1 Power-on-clear reset generated

The value is 04H only after a power-on-clear reset.

Note

00H

R/W

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

9. FLASH MEMORY PROGRAMMING

The program memory incorporated in the µPD78F9328 is flash memory.

Writing to flash memory can be performed with the device mounted in the target system (on-board programming). Writing is performed with a dedicated flash memory programmer (Flashpro III (part number: FL-PR3 and PG-FP3)) connected to the host machine and the target system.

Remark

FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

9.1 Selection of Communication Mode

Writing to flash memory is performed via serial communication using Flashpro III. Select one of the communication modes from those in Table 9-1. The selection of the communication mode is made by using the format shown in Figure 9-1. The communication mode is selected by the number of VPP pulses shown in Table 9-1.

Table 9-1. Communication Modes

Communication Mode Pi n Used Number of VPP Pulses

3-wire serial I/O SCK10/P20

SO10/P21 SI10/P22

Caution Always select the communication mode using the number of pulses shown in Table 9-1.

Figure 9-1. Communication Mode Selection Format

10 V

12 n

RESET

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

9.2 Flash Memory Programming Functions

Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 9-2 shows the major functions of flash memory programming.

Table 9-2. Major Functions of Flash Memory Programming

Function Description Batch erase Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. Data write Writes to flash memory based on the write s t art address and the number of data to

be written (number of bytes).

Batch verify Checks the entire memory contents and the input data.

9.3 Flashpro III Connection Example

An example of the connection between the µPD78F9328 and Flashpro III is shown in Figure 9-2.

Note

n = 1, 2

Figure 9-2. Connection of Flashpro III Using 3-Wire Serial I/O Mode

Flashpro III PD78F9328

Note

VPPn

RESET

CLK X1

SCK

GND

RESET

SCK10 SI10 SO10

Preliminary Product Information U14411EJ1V0PM00

9.4 Setting Example Using Flashpro III (PG-FP3)

When using Flashpro III (PG-FP3) to write to flash memory, set as follows.

<1> Download the parameter file <2> Select the serial mode and serial clock with the type command <3> A setting example using the PG-FP3 is shown below

Table 9-3. Setting Example Using PG-FP3

µµµµ

PD78F9328

Communication Mode Setting Example Usi ng P G -FP 3 Number of V

Pulses

3-wire serial I/O mode

The number of V

Note

COMM PORT SIO-ch0

On Target BoardCPU CLK

In Flashpro On Target Board 4.1943 MHz SIO CLK 1.0 MHz In Flashpro 4.0 MHz SIO CLK 1.0 MHz

pulses supplied from Flashpro III during the initialization of serial communication. The

pins to be used in communication are determined by this number.

Remark

COMM PORT: Selection of the serial port

SIO CLK: Selection of the serial clock frequency CPU CLK: Selection of the input CPU clock source

Note

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

10. INSTRUCTION SET OVERVIEW

The instruction set for the µPD78F9328 is listed in this section.

10.1 Conventions

10.1.1 Operand formats and descriptions

The description made in the operand field of each instruction conforms to the operand format for the instructions listed below (the details conform to the assembly specification). If more than one operand format is listed for an instruction, one is selected. Uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be written exactly as they appear. The meanings of these special characters are as follows:

#: Immediate data specification

•

$: Relative address specification

•

!: Absolute address specification

•

[ ]: Indirect address specification

•

Immediate data should be described using appropriate values or labels. The specification of values and labels must be accompanied by #, !, $, or [ ].

Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C, etc.) and absolute names (R0, R1, R2, and other names listed in Table 5-1 below).

Table 10-1. Operand Formats and Descriptions

Format Description

r rp sfr

saddr saddrp

addr16

addr5 word

byte bit

Remark

For details concerning special function register symbols, refer to

Registers

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP 2), HL (RP3) Special function regis ter symbol

FE20H to FF1FH Immediate data or l abel FE20H to FF1FH Immediate data or l abel (even addresses only)

0000H to FFFFH Immediate data or label (only even addresses for 16-bit data transfer instructions ) 0040H to 007FH Immediate data or label (even addres ses only)

16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label

Table 4-1 Special Function

Preliminary Product Information U14411EJ1V0PM00

10.1.2 Operation field definitions

A: A register (8-bit accumulator) X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair (16-bit accumulator) BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag to indicate that a non-maskable interrupt is being processed (): Contents of a memory location indicated by a parenthesized address or register name

, XL: Higher and lower 8 bits of a 16-bit register

: Logical product (AND)

∧

: Logical sum (OR)

∨

: Exclusive OR

∀

: Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value)

µµµµ

PD78F9328

10.1.3 Flag operation field definitions

(Blank): No change 0: Clear to 0 1: Set to 1

: Set or clear according to the result

R: Restore to the previous value

Preliminary Product Information U14411EJ1V0PM00

10.2 Operations

MOV

XCH

MOVW

XCHW AX, rp

r, #byte 3 6 r ← byte saddr , #byte 3 6 (saddr) ← byte sfr, #byte 3 6 sfr ← byte A, r r, A A, saddr 2 4 A ← (saddr) saddr, A 2 4 (saddr) ← A A, sfr 2 4 A ← sfr sfr, A 2 4 sfr ← A A, !addr16 3 8 A ← (addr16) !addr16, A 3 8 (addr16) ← A PSW, #byte 3 6 PSW ← byte A, PSW 2 4 A ← PSW PSW, A 2 4 PSW ← A A, [DE] 1 6 A ← (DE) [DE], A 1 6 (DE) ← A A, [HL] 1 6 A ← (HL) [HL], A 1 6 (HL) ← A A, [HL + byte] 2 6 A ← (HL + byte) [HL + byte], A 2 6 (HL + byte) ← A A, X 1 4 A ↔ X A, r A, saddr 2 6 A ↔ (saddr) A, sfr 2 6 A ↔ (sfr) A, [DE] 1 8 A ↔ (DE) A, [HL] 1 8 A ↔ (HL) A, [HL + byte] 2 8 A ↔ (HL + byte) rp, #word 3 6 rp ← word AX, saddrp 2 6 AX ← (saddrp) saddrp, AX 2 8 (saddrp) ← AX AX, rp rp, AX

Note 1

Note 2

Note 3

24A 24r

26A

1 4 AX ← rp 14rp 1 8 AX ↔ rp

←

↔

←

µµµµ

PD78F9328

FlagMnemonic Operand Byte Clock Operation

ZACCY

×××

Notes 1.

Remark

Except when r = A. Except when r = A or X.

Only when rp = BC, DE, or HL.

The instruction clock cycle is based on the CPU clock (f register (PCC).

Preliminary Product Information U14411EJ1V0PM00

CPU

) specified by the processor clock control

ADD

ADDC

SUB

SUBC

AND

A, #byte 2 4 A, CY ← A + byte saddr, #byte 3 6 (saddr), CY ← (saddr) + byte A, r 2 4 A, CY ← A + r A, saddr 2 4 A, CY ← A + (saddr) A, !addr16 3 8 A, CY ← A + (addr16) A, [HL] 1 6 A, CY ← A + (HL) A, [HL + byte] 2 6 A, CY ← A + (HL + byte) A, #byte 2 4 A, CY ← A + byte + CY saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY A, r 2 4 A, CY ← A + r + CY A, saddr 2 4 A, CY ← A + (saddr) + CY A, !addr16 3 8 A, CY ← A + (addr16) + CY A, [HL] 1 6 A, CY ← A + (HL) + CY A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY A, #byte 2 4 A, CY ← A − byte saddr, #byte 3 6 (saddr), CY ← (saddr) − byte A, r 2 4 A, CY ← A − r A, saddr 2 4 A, CY ← A − (saddr) A, !addr16 3 8 A, CY ← A − (addr16) A, [HL] 1 6 A, CY ← A − (HL) A, [HL + byte] 2 6 A, CY ← A − (HL + byte) A, #byte 2 4 A, CY ← A − byte − CY saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY A, r 2 4 A, CY ← A − r − CY A, saddr 2 4 A, CY ← A − (saddr) − CY A, !addr16 3 8 A, CY ← A − (addr16) − CY A, [HL] 1 6 A, CY ← A − (HL) − CY A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY A, #byte 2 4 A ← A saddr, #byte 3 6 (saddr) ← (saddr) A, r 2 4 A ← A ∧ r A, saddr 2 4 A ← A A, !addr16 3 8 A ← A A, [HL] 1 6 A ← A A, [HL + byte] 2 6 A ← A

byte

∧

(saddr)

∧

(addr16)

∧

(HL)

∧

(HL + byte)

∧

byte

µµµµ

PD78F9328

FlagMnemonic Operand Byte Clock Operation

ZACCY

××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× × × × × × × ×

Remark

The instruction clock cycle is based on the CPU clock (f register (PCC).

Preliminary Product Information U14411EJ1V0PM00

CPU

) specified by the processor clock control

XOR

CMP

ADDW AX, #word 3 6 AX, CY ← AX + word SUBW AX, #word 3 6 AX, CY ← AX − word CMPW AX, #word 3 6 AX − word INC

DEC

INCW rp 1 4 rp ← rp + 1 DECW rp 1 4 rp ← rp − 1 ROR A, 1 1 2 (CY, A7 ← A0, A ROL A, 1 1 2 (CY, A0 ← A7, A RORC A, 1 1 2 (CY ← A0, A7 ← CY, A ROLC A, 1 1 2 (CY ← A7, A0 ← CY, A

A, #byte 2 4 A ← A saddr, #byte 3 6 (saddr) ← (saddr) A, r 2 4 A ← A A, saddr 2 4 A ← A A, !addr16 3 8 A ← A A, [HL] 1 6 A ← A A, [HL + byte] 2 6 A ← A A, #byte 2 4 A ← A saddr, #byte 3 6 (saddr) ← (saddr) ∀ byte A, r 2 4 A ← A A, saddr 2 4 A ← A ∀ (saddr) A, !addr16 3 8 A ← A ∀ (addr16) A, [HL] 1 6 A ← A ∀ (HL) A, [HL + byte] 2 6 A ← A ∀ (HL + byte) A, #byte 2 4 A − byte saddr, #byte 3 6 (saddr) − byte A, r 2 4 A − r A, saddr 2 4 A − (saddr) A, !addr16 3 8 A − (addr16) A, [HL] 1 6 A − (HL) A, [HL + byte] 2 6 A − (HL + byte)

r24r saddr 2 4 (saddr) ← (saddr) + 1 r24r saddr 2 4 (saddr) ← (saddr) − 1

←

∨

∀

r + 1

r − 1

byte

∨

(saddr)

∨

(addr16)

∨

(HL)

∨

(HL + byte)

∨

byte

∀

byte

∨

m−1

← Am) × 1

m+1

← Am) × 1

m−1

← Am) × 1

m+1

← Am) × 1

µµµµ

PD78F9328

FlagMnemonic Operand Byte Clock Operation

ZACCY

× × × × × × × × × × × × × × ××× ××× ××× ××× ××× ××× ××× ××× ××× ××× ×× ×× ×× ××

× × × ×

Remark

The instruction clock cycle is based on the CPU clock (f register (PCC).

Preliminary Product Information U14411EJ1V0PM00

CPU

) specified by the processor clock control

µµµµ

PD78F9328

FlagMnemonic Operand Byte Clock Operation

ZACCY

SET1

CLR1

SET1 CY 1 2 CY ← 11 CLR1 CY 1 2 CY NOT1 CY 1 2 CY CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,

CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,

RET 1 6 PCH ← (SP + 1), PCL ← (SP),

RETI 1 8 PCH ← (SP + 1), PCL ← (SP),

saddr.bit 3 6 (saddr.bit) ← 1 sfr.bit 3 6 sfr.bit ← 1 A.bit 2 4 A.bit ← 1 PSW.bit 3 6 PSW bit ← 1 [HL].bit 2 10 (HL).bit ← 1 saddr.bit 3 6 (saddr.bit) ← 0 sfr.bit 3 6 sfr.bit ← 0 A.bit 2 4 A.bit ← 0 PSW.bit 3 6 PSW.bit ← 0 [HL].bit 2 10 (HL).bit ← 0

←

PC ← addr16, SP ← SP − 2

← (00000000, addr5 + 1),

← (00000000, addr5),

SP ← SP − 2

SP ← SP + 2

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0 PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1PUSH rp 1 4 (SP − 1) ← rp

SP ← SP − 2 PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP rp 1 6 rp

SP, AX 2 8 SP ← AXMOVW AX, SP 2 6 AX ← SP !addr16 3 6 PC ← addr16 $addr16 2 6 PC ← PC + 2 + jdisp8 AX 1 6 PC

← (SP + 1), rpL ← (SP),

SP ← SP + 2

← A, PCL ← X

, (SP − 2) ← rpL,

×××

RRR

Remark

The instruction clock cycle is based on the CPU clock (f register (PCC).

Preliminary Product Information U14411EJ1V0PM00

CPU

) specified by the processor clock control

BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1 BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0 BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1 BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0 BT

DBNZ

NOP 1 2 No Operati on EI 3 6 IE ← 1 (Enable Interrupt) DI 3 6 IE ← 0 (Disable Interrupt) HALT 1 2 Set HA LT Mode STOP 1 2 Set STOP Mode

saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8

if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8

if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC ← PC + 4 + disp8 if PSW.bit = 0 B, $addr16 2 6 B ← B − 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0 C, $addr16 2 6 C ← C − 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0 saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

µµµµ

PD78F9328

FlagMnemonic Operand Byte Clock Operation

ZACCY

Remark

The instruction clock cycle is based on the CPU clock (f register (PCC).

CPU

) specified by the processor clock control

Preliminary Product Information U14411EJ1V0PM00

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

Parameter Symbol Conditions Ratings Unit

Supply voltage

Input voltage V

Output current, high I

Operating ambient temperature T Storage temperature T

= 25

LC0

stg

µµµµ

°°°°

0.3 to +6.5 V

−

0.3 to +10.5 V

−

0.3 to +6.5 V

−

Note

0.3 to V

−

0.3 to V

P00 to P03, P10, P11, P 20 to P22,

−

P40 to P43, P60, P61

0.3 to V

COM0 to COM3, S0 to S21,

−

P80/S22 to P85/S17 Pin P60/TO40 Per pin (except P60/TO40) Total for all pins (except P60/TO40) Per pin 30 mAOutput current, low I Total for all pins 80 mA

+ 0.3

Note

+ 0.3

Note

LC0

+ 0.3

30 mA

−

10 mA

−

30 mA

−

40 to +85

−

65 to +150

−

PD78F9328

V VOutput voltage

6.5 V or lower

Note

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

Remark

Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

Main System Clock Oscillator Characteristics

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

X1X2V

C1C2

X1X2IC

C1C2

Oscillation frequency

(f Oscillation

stabilization time

Oscillation frequency

(f Oscillation

stabilization time

X1 input frequency

(f X1 input high-/low-

level width (t

Note 1

)

Note 1

)

Note 1

)

resonator

clock

Notes 1.

Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release.

(TA =

40 to +85°C, VDD = 1.8 to 5.5 V)

−−−−

After VDD has reached the MIN.

Note 2

oscillation voltage range

Note 2

, tXL)

1.0 5.0 MHzCeramic

4ms

1.0 5.0 MHzCrystal

30 ms

1.0 5.0 MHzExternal

85 500 ns

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with other signal lines.

••••

Do not route the wiring near a signal line through which a high fluctuating current flows.

••••

Always make the ground point of the oscillator capacitor the same potential as VSS.

••••

Do not ground the capacitor to a ground pattern through which a high current flows.

••••

Do not fetch signals from the oscillator.

••••

2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

Subsystem Clock Oscillator Characteristics (TA =

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Crystal resonator

clock

Notes 1.

XT2XT1IC

XT1

XT2

Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The time required for oscillation to stabilize after V

Oscillation frequency

Note 1

)

Oscillation stabilization time

XT1 input frequency

Note 1

)

XT1 input high-/lowlevel width (t

XTH

, t

Note 2

XTL

)

40 to +85°C, VDD = 1.8 to 5.5 V)

−−−−

32 32.768 35 kHz

VDD = 4.5 to 5.5 V 1.2 2

32 35 kHzExternal

14.3 15.6

reaches the MIN. oscillation voltage range. Use a

resonator to stabilize oscillation during the oscillation wait time.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

••••

Do not cross the wiring with the other signal lines.

••••

Do not route the wiring near a signal line through which a high fluctuating current flows.

••••

Always make the ground point of the oscillator capacitor the same potential as V

••••

Do not ground the capacitor to a ground pattern through which a high current flows.

••••

Do not fetch signals from the oscillator.

••••

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used.

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

DC Characteristics (TA =

20 to +60°C, VDD = 1.8 to 5.5 V) (1/2)

−−−−

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Per pin 10 mAOutput current, low I Total for all pins 80 mA

Output current, high I

Per pin (except P60/TO40) P60/TO40 VDD = 3.0 V, VOH = 1.0 V

−

Total for all pins (except P60/TO40)

Input voltage, high

Input voltage, low

Output voltage, high

Output voltage, low

V V

OH11

OH12

OH21

OH22

OH31

OH32

IH1

P00 to P03, P10, P11,

VDD = 2.7 to 5.5 V 0.7 V

P21, P22, P60

IH2

RESET, P20, P40 to P43,

VDD = 2.7 to 5.5 V 0.8 V

P61

IH3

X1, X2 VDD − 0.1 V

IH4

XT1, XT2 VDD − 0.1 V

IL1

P00 to P03, P10, P11,

VDD = 2.7 to 5.5 V 0 0.3 V

P21, P22, P60

IL2

RESET, P20, P40 to P43,

VDD = 2.7 to 5.5 V 0 0.2 V

P61

IL3

X1, X2 0 0.1 V

IL4

XT1, XT2 0 0.1 V P00 to P03, P10, P11,

P20 to P22, P40 to P43, P61

P60/TO40

P80/S22 to P85/S17

OL11

P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61

OL12

OL21

P80/S22 to P85/S17

OL22

1.8 ≤ VDD ≤ 5.5 V,

= −100 µA

1.8 ≤ V

≤ 5.5 V,

= −500 µA

1.8 ≤ VDD ≤ 5.5 V,

= −400 µA

1.8 ≤ V

≤ 5.5 V,

= −2 mA

1.8 ≤ VDD ≤ 5.5 V,

= −100 µA

1.8 ≤ V

≤ 5.5 V,

= −500 µA

1.8 ≤ VDD ≤ 5.5 V,

= 400 µA

1.8 ≤ V

≤ 5.5 V,

= 2 mA

LC0

≤ 5.5 V,

= 400 µA

LC0

≤ 5.5 V,

= 2 mA

0.9 V

0 0.1 V

− 0.5 V

− 0.7 V

− 0.5 V

− 0.7 V

LC0

− 0.5 V

LC0

− 0.7 V

1mA

−

24 mA

−

15 mA

−

VV V VV V V V

0.5 V

0.7 V

0.5 V

0.7 V

Remark

Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

Preliminary Product Information U14411EJ1V0PM00

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

high

low

Output leakage current, high

Output leakage current, low

Software pull-up resistors

Supply current

Note 1

Ceramic/crystal oscillation

LIH1

LIH2

I I

LIL1

LIL2

LOH

LOL

DD1

DD2

DD4

DD5

VIN = V

P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET

X1, X2, XT1, XT2 20

VIN = 0 V

P00 to P03, P10, P11, P20 to P22, P40 to P43, P60, P61, RESET

X1, X2, XT1, XT2

OUT

= V

= 0 V

VIN = 0 V P00 to P03, P10,

P11, P20 to P22, P40 to P43

5.0-MHz crystal oscillation operating mode

5.0-MHz crystal oscillation HALT mode

32.768-kHz crystal oscillation HALT mode

Note 4

STOP mode

VDD = 5.5 V

V VDD = 5.5 V 1.2 3.6 mAI

V VDD = 5.5 V 25 55 VDD = 3.3 V 5 25 VDD = 5.5 V 2 30

Note 2

Note 3

= 3.3 V

= 3.3 V 0.5 1.5 mA

= 3.3 V 1 10

50 100 200 k

5.0 15.0 mAI

2.0 5.0 mA

µµµµ

PD78F9328

−

AInput l eakage current,

Ω

Notes 1.

Remark

Current flowing through ports (including current flowing through on-chip pull-up resistors) is not

included.

High-speed operation (when the processor clock control register (PCC) is set to 00H).

Low-speed operation (when PCC is set to 02H)

When the main system clock is stopped.

Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

Preliminary Product Information U14411EJ1V0PM00

AC Characteristics

µµµµ

PD78F9328

(1) Basic operation (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit

(Min. instruction ex ecution time)

Interrupt input high-/low-level width

Key return pin low-level width

RESET low-level width t

40 to +85°C, VDD = 1.8 to 5.5 V)

−−−−

INTH

INTL

KRIL

[ s]

VDD = 2.7 to 5.5 V 0.4 8. 0

INT 10

KR00 to KR03 10

RSL

TCY vs. VDD (Main System Clock)

Guaranteed operation

2.0

range

1.6 8.0

sCycle time

1.0

Cycle time T

0.5

0.4

0.1 123456

Supply voltage VDD (V)

Preliminary Product Information U14411EJ1V0PM00

(2) Serial interface 10 (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

(a) 3-wire serial I/O mode (Internal clock output)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY1

VDD = 2.7 to 5.5 V 800 nsSCK10 cycle time t

KH1

VDD = 2.7 to 5.5 V t

KL1

SIK1

VDD = 2.7 to 5.5 V 150 nsSI10 setup time

KSI1

VDD = 2.7 to 5.5 V 400 nsSI10 hold time

R = 1 kΩ, C = 100 pF

KSO1

Note

VDD = 2.7 to 5.5 V 0 250 nsSO10 output delay tim e

width

(to SCK10 ↑)

(from SCK10 ↑)

from SCK10

Note

↓

R and C are the load resistance and load capacitance of the SO10 output line.

µµµµ

3,200 ns

KCY1

/2 − 50 nsSCK10 high-/low-level

KCY1

/2 − 150 ns

500 ns

800 ns

250 1,000 ns

PD78F9328

(b) 3-wire serial I/O mode (External clock input)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

KCY2

VDD = 2.7 to 5.5 V 900 nsSCK10 cycle time t

3,500 ns

KH2

VDD = 2.7 to 5.5 V 400 nsSCK10 high-/low-lev el

KL2

SIK2

VDD = 2.7 to 5.5 V 100 nsSI10 setup ti m e

KSI2

VDD = 2.7 to 5.5 V 400 nsSI10 hold time

R = 1 kΩ, C = 100 pF

KSO2

Note

1,600 ns

150 ns

600 ns

VDD = 2.7 to 5.5 V 0 300 nsSO10 output delay tim e

250 1,000 ns

width

(to SCK10 ↑)

(from SCK10 ↑)

from SCK10

Note

↓

R and C are the load resistance and load capacitance of the SO10 output line.

Preliminary Product Information U14411EJ1V0PM00

AC Timing Measurement Point (excluding X1, XT1 input)

0.8 V

0.2 V

Test points

Clock Timing

1/f

X1 input

1/f

XTL

µµµµ

PD78F9328

0.8 V

0.2 V

IH3

(MIN.)

IL3

(MAX.)

XTH

XT1 input

Interrupt Input Timing

INT

Key Return Input Timing

KR00 to KR03

RESET Input Timing

INTL

KRIL

INTH

IH4

(MIN.)

IL4

(MAX.)

RESET

RSL

Preliminary Product Information U14411EJ1V0PM00

Serial Transfer Timing

3-wire serial I/O mode:

SCK10

µµµµ

PD78F9328

KCYn

KLn

SIKn

KSIn

KHn

Remark

n = 1, 2

SI10

SO10

KSOn

Input data

Output data

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

LCD Characteristics (TA =

40 to +85°C, VDD = 1.8 to 5.5 V)

−−−−

Parameter Symbol Conditions MIN. TYP. MAX. Unit

LCD drive voltage V

LCD1

LCD division resist ance

LCD output voltage different i al

Note 3

LCD2

LC0

Note 2

ODCIO

VAON0 VAON0 High resistance 50 100 200 k Low resistance 5 10 20 k

= ±5 µA 1/3 bias 0

Note 1

= 1 = 0

1.8 5. 5 V

2.7 5. 5 V

Note 1

(common) LCD output voltage different i al

Note 3

ODSIO

= ±1 µA 1/3 bias 0

(segment)

Notes 1.

Bit 6 of LCD display mode register 0 (LCDM0)

One or the other can be selected when designing

The voltage differential is the difference between the output voltage and the ideal value of the segment

and common signal outputs.

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

40 to +85°C, VDD = 1.8 to 5.5 V)

−−−−

Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V Low voltage detection (POC) v ol t age V Power supply rise tim e t Release signal set tim e t Oscillation stabilization wait time

Note 2

DDDR

SREL

WAIT

1.8 3.6 V

Response time: 2 ms

POC

Pth

VDD: 0 V → 1.8 V 0.01 100 ms

Note 1

1.8 1.9 2.0 V

STOP cancelled by RESET 10 Cancelled by RESET Cancelled by interrupt request

Note 3

0.2 V

Ω Ω

s s

Notes 1.

Remark

The response time is the time until the output is inverted following detection of voltage by POC, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid

unstable operation at the start of oscillation. Program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed.

Selection of 2

stabilization time select register (OSTS) (refer to

/fX, 215/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

7.2 Standby Function Control Register

fX: Main system clock oscillation frequency

Preliminary Product Information U14411EJ1V0PM00

Data Retention Timing

STOP instruction execution

RESET

STOP mode

Data retention mode

DDDR

STOP mode

Internal reset operation

HALT mode

SREL

WAIT

HALT mode

µµµµ

PD78F9328

Operating mode

STOP instruction execution

Standby release signal (interrupt request)

Data retention mode

DDDR

SREL

WAIT

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

APPENDIX A. DIFFERENCES BETWEEN

PD78F9328 AND MASK ROM VERSIONS

µµµµ

The µPD78F9328 is a product provided with flash memory in place of the internal ROM of the mask ROM

versions. Table A-1 shows the differences between the flash memory (µPD78F9328) and the mask ROM versions.

Table A-1. Differences Between

Flash Memory Version Mask ROM VersionItem

PD78F9328

Internal memory

IC0 pin Not provided P rov i ded VPP pin Provided Not provided Electrical speci fications There may be differences between mask ROM and flash memory versions.

ROM 32 Kbytes

(flash memory) High-speed RAM 512 bytes LCD display RAM 24 bytes

PD78F9328 and Mask ROM Versions

µµµµ

PD789322

4 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes

PD789324

PD789326

PD789627

Caution There are differences in the amount of noise tolerance and noise radiation between flash

memory versions and mask ROM versions. When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.

Preliminary Product Information U14411EJ1V0PM00

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for system development using the µPD78F9328.

Language Processing Software

RA78K0S CC78K0S DF789328 CC78K/0S–L

Flash Memory Writing Tools

Notes 1, 2, 3

Notes 1, 2 ,3

Notes 1, 2, 3, 5

Notes 1, 2, 3

Assembler package com m on to 78K/0S Series

C compiler package common t o 78K/0S Series

Device file for µPD789328 Subseries

C compiler library sourc e f ile common to 78K/0S Se ri es

µµµµ

PD78F9328

Flashpro III (Part number: FL-PR3

FA-52GB

Notes 4, 5

Debugging Tools

IE-78K0S-NS In-circuit emulator

IE-70000-MC-PS-B AC adapter

IE-70000-98-IF-C Interface adapter

IE-70000-CD-IF-A PC card interface

IE-70000-PC-IF-C Interface adapter

IE-70000-PCI-IF Interface adapter

IE-789328-NS-EM1 Emulation board

NP-52GB

SM78K0S ID78K0S-NS DF789328

Notes 4, 5

Notes 1, 2

Notes 1, 2, 5

Note 5

Note 4

Dedicated flash memory program m er

, PG-FP3)

Adapter for writing to flas h memory designed for 52-pin plastic LQFP (GB-8ET type)

In-circuit emulator t o debug hardware or software when application systems using the

78K/0S Series are developed. The IE-78K0S-NS supports an integrat ed debugger

(ID78K0S-NS). The IE-78K0S -NS i s used in combination with an interface adapter for

connection to an AC adapter, emul ation probe, or host machine.

AC adapter to supply power from a 100- to 240-V AC outlet.

Interface adapter required when using a P C-9800 S eri es computer (except notebook type)

as the host machine for t he IE-78K0S-NS (C bus supported).

PC card and interface cable required when a not ebook PC is used as the host machine for

the IE-78K0S-NS (PCMCIA socket supported).

Interface adapter required when using an I B M PC/AT™ or compatible as the host machine

for the IE-78K0S-NS (IS A bus supported).

Interface adapter required when using a P C incorporating a PCI bus as the host m achine

for the IE-78K0S-NS.

Emulation board to emulate the peri pheral hardware specific to the devic e. The IE-

789328-NS-EM1 is used in combi nat i on wi th the in-circuit emulator.

Board to connect an in-circ ui t emulator to the target system. This board is dedicated for a

52-pin plastic LQFP (GB-8ET ty pe).

System simulat or common to 78K/0S Series

Integrated debugger common to 78K/ 0S Series

Device file for µPD789328 Subseries

Notes 1.

Remark

Based on the PC-9800 series (MS-DOS™ + Windows™) Based on IBM PC/AT or compatibles (Japanese/English Windows)

Based on the HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), and NEWS™

(NEWS-OS™)

Manufactured by Naito Densei Machida Mfg. Co, Ltd. (+81-44-822-3813). Contact Naito Densei

Machida Mfg. Co, Ltd. regarding the purchase of these products. Under development

The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789328 device file.

Preliminary Product Information U14411EJ1V0PM00

Real-Time OS

MX78K0S

Notes 1, 2

OS for 78K/0S Series

µµµµ

PD78F9328

Notes 1.

Based on the PC-9800 series (MS-DOS + Windows) Based on IBM PC/AT or compatibles (Japanese/English Windows)

Preliminary Product Information U14411EJ1V0PM00

µµµµ

PD78F9328

APPENDIX C. RELATED DOCUMENTS

Documents Related to Devices

Document No.Document Name

Japanese English

PD789322, 789324, 789326, 789327 Preliminary Product Information To be prepared To be prepared

PD78F9328 Preliminary Product Information To be prepared This document

PD789328, 789468 Subseries User’s Manual To be prepared To be prepared

78K/0S Series User’s Manual Instructions U11047J U11047E

Documents Related to Development Tools (User’s Manual)

Document No.Document Name

Japanese English

RA78K0S Assembler Package

SM78K0S System Simulator Windows Based Reference U11489J U11489E SM78K Series System Simulator External Part User Open

ID78K0S-NS Integrated Debugger Windows Based Reference U12901J U12901E IE-78K0S-NS In-circ ui t Emulator U13549J U13549E IE-789328-NS-EM1 Emulation Board To be prepared To be prepared

Operation U11622J U11622E Assembly Language U11599J U11599E Structured Assembl y Language U11623J U11623E Operation U11816J U11816ECC78K0S C Compiler Language U11817J U11817E

U10092J U10092E

Interface Specifi c ations

Documents Related to Embedded Software (User’s Manual)

Document No.Document Name

Japanese English

78K/0S Series OS MX78K 0S Fundamental U12938J U12938E

NEC UPD78F9328 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

ORDERING INFORMATION

78K/0S SERIES LINEUP

OVERVIEW OF FUNCTIONS

1. PIN CONFIGURATION (TOP VIEW)

2. BLOCK DIAGRAM

3. PIN FUNCTIONS

3.1 Port Pins

Non-Port Pins

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

4. CPU ARCHITECTURE

4.1 Memory Space

4.2 Data Memory Addressing

4.3 Processor Registers

4.3.1 Control registers

4.3.2 General-purpose registers

4.3.3 Special function registers (SFRs)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

5.1.1 Port functions

5.1.2 Port configuration

5.1.3 Port function control registers

5.2 Clock Generator

5.2.1 Clock generator function

5.2.2 Clock generator configuration

5.2.3 Clock generator control registers

5.3 8-Bit Timer 30, 40

5.3.1 Functions of 8-bit timer 30, 40

5.3.2 Configuration of 8-bit timer 30, 40

5.3.3 8-bit timer 30, 40 control registers

5.4 Watch Timer

5.4.1 Watch timer functions

5.4.2 Watch timer configuration

5.4.3 Watch timer control register

5.5 Watchdog Timer

5.5.1 Watchdog timer functions

5.5.2 Watchdog timer configuration

5.5.3 Watchdog timer control register

5.6 Serial Interface 10

5.6.1 Functions of serial interface 10

5.6.2 Configuration of serial interface 10

5.6.3 Control register for serial interface 10

5.7 LCD Controller/Driver

5.7.1 LCD controller/driver functions

5.7.2 LCD controller/driver configuration

5.7.3 LCD controller/driver control registers

6. INTERRUPT FUNCTION

6.1 Interrupt Types

6.2 Interrupt Sources and Configuration

6.3 Interrupt Function Control Registers

7. STANDBY FUNCTION

7.1 Standby Function

7.2 Standby Function Control Register

8. RESET FUNCTION

8.1 Reset Function

8.2 Power Failure Detection Function

9. FLASH MEMORY PROGRAMMING

9.1 Selection of Communication Mode

9.2 Flash Memory Programming Functions

9.3 Flashpro III Connection Example

9.4 Setting Example Using Flashpro III (PG-FP3)

10. INSTRUCTION SET OVERVIEW

10.1 Conventions

10.1.1 Operand formats and descriptions

10.1.2 Operation field definitions

10.1.3 Flag operation field definitions

10.2 Operations

11. ELECTRICAL SPECIFICATIONS

APPENDIX B. DEVELOPMENT TOOLS

APPENDIX C. RELATED DOCUMENTS