NEC uPD75P3116 User Manual

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75P3116

4-BIT SINGLE-CHIP MICROCONTROLLER

The µPD75P3116 replaces the µPD753108’s internal mask ROM with a one-time PROM, and features expanded

ROM capacity.

Because the

development stage using the

Detailed information about functions is provided in the following User’s Manual. Be sure to read it before

designing:

PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the

PD753104, 753106, or 753108, and for use in small-scale production.

PD753108 User’s Manual: U10890E

FEATURES

Compatible with µPD753108

Memory capacity:

• PROM: 16384 × 8 bits

• RAM: 512 × 4 bits

Can be operated in same power supply voltage range as the mask version µPD753108

• VDD = 1.8 to 5.5 V

On-chip LCD controller/driver

QTOPTM microcontroller

Remark QTOP microcontrollers are microcontrollers with on-chip one-time PROM that are totally supported by NEC.

This support includes writing application programs, marking, screening, and verification.

ORDERING INFORMATION

Part Number Package

PD75P3116GC-AB8 64-pin plastic QFP (14 × 14)

PD75P3116GK-8A8 64-pin plastic LQFP (12 × 12)

PD75P3116GC-8BS 64-pin plastic LQFP (14 × 14)

Caution This device does not provide an internal pull-up resistor connection function by means of mask

option.

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U11369EJ3V0DS00 (3rd edition) Date Published March 2002 N CP(K) Printed in Japan

The mark shows major revised points.

1994

PD75P3116

FUNCTION OUTLINE

Item Function

Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µs (main system clock: @ 4.19 MHz)

• 0.67, 1.33, 2.67, or 10.7 µs (main system clock: @ 6.0 MHz)

• 122 µs (subsystem clock: @ 32.768 kHz)

Internal memory PROM 16384 × 8 bits

RAM 512 × 4 bits

General-purpose registers • 4-bit manipulation: 8 × 4 banks

• 8-bit manipulation: 4 × 4 banks

I/O ports CMOS input 8 Internal pull-up resistor connection can be specified by software setting: 7

CMOS I/O 20

N-ch open-drain I/O 4 13 V withstanding voltage Total 32

LCD controller/driver • Segment number selection: 16/20/24 segments (switchable to CMOS I/O ports

Timers 5 channels: • 8-bit timer/event counter: 3 channels

Serial interface • 3-wire serial I/O mode ··· MSB/LSB first switchable

Bit sequential buffer (BSB) 16 bits Clock output (PCL) Φ, 524, 262, and 65.5 kHz (main system clock: @ 4.19 MHz)

Buzzer output (BUZ) • 2, 4, and 32 kHz (

Vectored interrupts • External: 3

Test inputs • External: 1

System clock oscillator • Ceramic/crystal oscillator for main system clock

Standby function STOP/HALT mode Power supply voltage VDD = 1.8 to 5.5 V Package • 64-pin plastic QFP (14 × 14)

Internal pull-up resistor connection can be specified by software setting: 12 Shared with segment pins: 8

in a batch of 4 pins, max. 8 pins)

• Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias)

(Can be used as 16-bit timer/event counter, carrier generator,

and timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

• 2-wire serial I/O mode

• SBI mode

Φ, 750, 375, and 93.8 kHz (main system clock: @ 6.0 MHz)

main system clock: @ 4.19 MHz or subsystem clock: @ 32.768 kHz

• 2.93, 5.86, 46.9 kHz (main system clock: @ 6.0 MHz)

• Internal: 5

• Internal: 1

• Crystal oscillator for subsystem clock

• 64-pin plastic LQFP (12 × 12)

• 64-pin plastic LQFP (14 × 14)

)

Data Sheet U11369EJ3V0DS

PD75P3116

CONTENTS

1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 4

2. BLOCK DIAGRAM ............................................................................................................................ 6

3. PIN FUNCTIONS ............................................................................................................................... 7

3.1 Port Pins ................................................................................................................................................... 7

3.2 Non-Port Pins ........................................................................................................................................... 9

3.3 Pin I/O Circuits ......................................................................................................................................... 11

3.4 Recommended Connection of Unused Pins ......................................................................................... 13

4. Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................. 14

4.1 Differences Between Mk I Mode and Mk II Mode................................................................................... 14

4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 15

5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108 ............................... 16

6. MEMORY CONFIGURATION ........................................................................................................... 17

7. INSTRUCTION SET .......................................................................................................................... 19

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 28

8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28

8.2 Program Memory Write Procedure......................................................................................................... 29

8.3 Program Memory Read Procedure ......................................................................................................... 30

8.4 One-Time PROM Screening .................................................................................................................... 31

9. ELECTRICAL SPECIFICATIONS .....................................................................................................32

10. CHARACTERISTIC CURVES (REFERENCE VALUES).................................................................. 47

11. PACKAGE DRAWINGS ................................................................................................................... 49

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 52

APPENDIX A. LIST OF µPD75308B, 753108, AND 75P3116 FUNCTIONS......................................... 54

APPENDIX B. DEVELOPMENT TOOLS................................................................................................ 56

APPENDIX C. RELATED DOCUMENTS ............................................................................................... 65

Data Sheet U11369EJ3V0DS

1. PIN CONFIGURATION (TOP VIEW)

• 64-pin plastic QFP (14 × 14):µPD75P3116GC-AB8

• 64-pin plastic LQFP (12 × 12):

• 64-pin plastic LQFP (14 × 14):

PD75P3116GK-8A8

PD75P3116GC-8BS

COM363COM262COM161COM060S059S158S257S356S455S554S653S752S851S950S1049S11

PD75P3116

BIAS

LC0

LC1

LC2

P30/LCDCL/MD0

P31/SYNC/MD1

P32/MD2 P33/MD3

Vss P50/D4 P51/D5 P52/D6 P53/D7

P60/KR0/D0 P61/KR1/D1 P62/KR2/D2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Note Always connect the V

22X123X224

Note

VPP

VDD

P00/INT4

P01/SCK

P03/SI/SB1

P02/SO/SB0

XT120XT2

RESET

P63/KR3/D3

PP pin directly to VDD during normal operation.

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P13/TI0

P10/INT0

P11/INT1

P12/INT2/TI1/TI2

S12 S13 S14 S15 P93/S16 P92/S17 P91/S18 P90/S19 P83/S20 P82/S21 P81/S22 P80/S23 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0

Data Sheet U11369EJ3V0DS

PD75P3116

PIN IDENTIFICATIONS

P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3 P10 to P13: Port 1 V P20 to P23: Port 2 BIAS: LCD power supply bias control P30 to P33: Port 3 LCDCL: LCD clock P50 to P53: Port 5 SYNC: LCD synchronization P60 to P63: Port 6 TI0 to TI2: Timer input 0 to 2 P80 to P83: Port 8 PTO0 to PTO2: Programmable timer output 0 to 2 P90 to P93: Port 9 BUZ: Buzzer clock KR0 to KR3: Key return 0 to 3 PCL: Programmable clock SCK: Serial clock INT0, 1, 4: External vectored interrupt 0, 1, 4 SI: Serial input INT2: External test input 2 SO: Serial output X1, X2: Main system clock oscillation 1, 2 SB0, SB1: Serial data bus 0, 1 XT1, XT2: Subsystem clock oscillation 1, 2 RESET: Reset V MD0 to MD3: Mode selection 0 to 3 V D0 to D7: Data bus 0 to 7 Vss: Ground S0 to S23: Segment output 0 to 23

LC0 to VLC2: LCD power supply 0 to 2

PP: Programming power supply DD: Positive power supply

Data Sheet U11369EJ3V0DS

2. BLOCK DIAGRAM

PD75P3116

BUZ/P23

PTO0/P20

TI1/TI2/

P12/INT2

PTO1/P21

PTO2/

PCL/P22

TOUT0

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10 INT1/P11 INT4/P00

INT2/P12/TI1/TI2

P60/KR0 to P63/KR3

TI0/P13

timer/event counter #1

timer/event counter #2

INTT1

8-bit

INTT2

Watch timer

INTW f

Basic interval timer/ watchdog timer

INTBT

8-bit timer/event counter #0

INTT0 TOUT0

Cascaded 16-bit timer/ event counter

Clocked serial interface

INTCSI

INT1

Interrupt control

Bit sequential buffer (16)

LCD

TOUT0

Program

counter (14)

Program

memory (PROM)

16384 × 8 bits

Clock

output

control

PCL/PTO2/P22

fx/2

Clock

divider

Decode

control

System clock generator

Main Sub

X2X1 XT2XT1

ALU

and

CPU clock Φ

General-

512 × 4 bits

Standby

control

SP (8)

SBS

Bank

purpose

Data

memory

(RAM)

Port 0

Port 1

Port 2

Port 3

Port 5

Port 6

Port 8

Port 9 P90 to P93

LCD

RESETVss

LCD

controller/driver

P00 to P03

P10 to P13

P20 to P23

P30/MD0 to P33/MD3

P50/D4 to P53/D7

P60/D0 to P63/D3

P80 to P83

S0 to S1516

S16/P93 to S19/P90

S20/P83 to S23/P80

COM0 to COM34 BIAS

LC0

LC1

LC2

SYNC/P31 LCDCL/P30

Data Sheet U11369EJ3V0DS

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

PD75P3116

Pin Name I/O Alternate Function 8-Bit Status I/O Circuit

Function I/O After Reset Type

P00 Input INT4 4-bit input port (Port 0) — Input

Connection of an internal pull-up resistor can be

P01 SCK specified by a software setting in 3-bit units. <F>-A

P02 SO/SB0 <F>-B

P03 SI/SB1 <M>-C

P10 Input INT0 4-bit input port (Port 1) — Input -C

Connection of an internal pull-up resistor can be

P11 INT1 specified by a software setting in 4-bit units.

P10/INT0 can be used to select a noise eliminator.

P12 TI1/TI2/INT2

P13 TI0

P20 I/O PTO0 4-bit I/O port (Port 2) — Input E-B

Connection of an internal pull-up resistor can be

P21 PTO1 specified by a software setting in 4-bit units.

P22 PCL/PTO2

P23 BUZ

P30 I/O LCDCL/MD0 Programmable 4-bit I/O port (Port 3) — Input E-B

Input and output can be specified in 1-bit units.

P31 SYNC/MD1 Connection of an internal pull-up resistor can be

specified by a software setting in 4-bit units.

P32 MD2

Note 1

P33 MD3

Note 2

P50

P51

P52

P53

Note 2

I/O D4 N-ch open-drain 4-bit I/O port (Port 5) — High M-E

When set to open-drain, the withstanding voltage impedance

D5 is 13 V.

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. The low-level input leakage current increases when input instructions or bit manipulation instructions are

executed.

Data Sheet U11369EJ3V0DS

3.1 Port Pins (2/2)

PD75P3116

Pin Name I/O Alternate Function 8-Bit Status I/O Circuit

P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A

P61 KR1/D1 Connection of an internal pull-up resistor can be

P62 KR2/D2

P63 KR3/D3

P80 I/O S23 4-bit I/O port (Port 8) √ Input H

P81 S22 specified by a software setting in 4-bit units

P82 S21

P83 S20

P90 I/O S19 Programmable 4-bit I/O port (Port 9) Input H

P91 S18 specified by a software setting in 4-bit units

P92 S17

P93 S16

Function I/O After Reset Type

Input and output can be specified in 1-bit units.

specified by a software setting in 4-bit units.

Connection of an internal pull-up resistor can be

Note 2

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. Do not connect an internal pull-up resistor by software when these pins are used as segment signal outputs.

Note 1

Data Sheet U11369EJ3V0DS

3.2 Non-Port Pins (1/2)

PD75P3116

Pin Name I/O Alternate Function Status I/O Circuit

Function After Reset Type TI0 Input P13 External event pulse input to timer/event counter Input -C TI1 P12/INT2/TI2 TI2 P12/INT2/TI1 PTO0 Output P20 Timer/event counter output Input E-B PTO1 P21 PTO2 P22/PCL PCL P22/PTO2 Clock output BUZ P23 Frequency output (for buzzer or system clock trimming) SCK I/O P01 Serial clock I/O Input <F>-A SO/SB0 P02 Serial data output <F>-B

Serial data bus I/O

SI/SB1 P03 Serial data input <M>-C

Serial data bus I/O

INT4 Input P00 Edge detection vectored interrupt input

(valid for detecting both rising and falling edges)

INT0 Input P10 Edge detection vectored interrupt

input (detection edge is selectable) asynchronous is

INT0/P10 can be used to select a selectable INT1 P11 INT2 Input P12/TI1/TI2 Rising edge detection testable input Asynchronous KR0 to KR3 I/O P60 to P63 Parallel falling edge detection testable input Input <F>-A X1 Input — Ceramic/crystal resonator connection for main system — —

X2 — XT1 Input — Crystal resonator connection for subsystem clock oscillation. — —

XT2 —

RESET Input — System reset input (low-level active) — MD0 to MD3 Input P30 to P33 Mode selection for program memory (PROM) write/verify Input E-B D0 to D3 I/O D4 to D7 P50 to P53 M-E

Note 2

VPP

VDD — — Positive power supply — — Vss — — Ground potential — —

P60/KR0 to P63/KR3

— — Programmable power supply voltage applied for program — —

noise eliminator.

clock oscillation. If using an external clock, input the signal

to X1 and input the inverted signal to X2.

If using an external clock, input the signal to XT1 and input

the inverted signal to XT2. XT1 can be used as a 1-bit (test)

input.

Data bus for program memory (PROM) write/verify Input <F>-A

memory (PROM) write/verify.

During normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.

With noise eliminator/

Asynchronous

Input -C

Note 1

Notes 1. Circuit types enclosed in angle brackets indicate Schmitt-triggered input.

2. The V

PP pin does not operate correctly when it is not connected to the VDD pin during normal operation.

Data Sheet U11369EJ3V0DS

PD75P3116

3.2 Non-Port Pins (2/2)

Pin Name I/O Alternate Function Status I/O Circuit

Function After Reset Type S0 to S15 S16 to S19 S20 to S23 COM0 to COM3 VLC0 to VLC2 — — Power supply for driving LCD — — BIAS Output — Output for external split resistor cut Note 2 —

Note 3

LCDCL

Note 3

SYNC

Output — Segment signal output Note 1 G-A Output P93 to P90 Segment signal output Input H Output P83 to P80 Segment signal output Input H Output — Common signal output Note 1 G-B

Output P30/MD0 Clock output for driving external expansion driver Input E-B Output P31/MD1 Clock output for synchronization of external expansion driver Input E-B

Notes 1. VLCX (X = 0, 1, 2) is selected as the input source for the display outputs as shown below.

S0 to S23: V

LC1, COM0 to COM2: VLC2, COM3: VLC0

2. When the split resistor is incorporated: Low level When the split resistor is not incorporated: High impedance

3. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

Data Sheet U11369EJ3V0DS

3.3 Pin I/O Circuits

The I/O circuits for the µPD75P3116’s pins are shown in abbreviated form below.

Type A Type D

PD75P3116

P-ch

N-ch

CMOS standard input buffer

Data

Output

disable

Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF).

Type E-BType B

P.U.R. enable

Data

Type D

Output

disable

P-ch

N-ch

OUT

P.U.R.

P-ch

IN/OUT

Schmitt-triggered input with hysteresis characteristics.

Type B-C Type F-A

P.U.R.

P-ch

P.U.R. : Pull-Up Resistor

P.U.R. enable

Data

Output

disable

Type A

P.U.R. : Pull-Up Resistor

P.U.R.

enable

Type D

Type B

P.U.R. : Pull-Up Resistor

P.U.R.

P-ch

IN/OUT

(Continued)

Data Sheet U11369EJ3V0DS

Type F-B Type H

VDD

P.U.R.

PD75P3116

(Continued)

Output

disable

(P)

Data

Output

disable

Output

disable

(N)

P.U.R. : Pull-Up Resistor

VLC0

VLC1

SEG

data

LC2

P-ch N-ch

enable

P-ch N-ch

P.U.R.

VDD

P-ch

N-ch

N-chP-ch

N-ch

P-ch

IN/OUT

OUT

SEG

data

Data

Output

disable

Type M-CType G-A

Output

disable

Data

Type G-A

Type E-B

P.U.R. enable

N-ch

P-ch N-ch

IN/OUT

VDD

P.U.R.

P-ch

IN/OUT

Type G-B

COM

LC0

VLC1

data

VLC2

P-ch N-ch

N-ch

P-ch N-ch

N-ch

P.U.R. : Pull-Up Resistor

Type M-E

IN/OUT

Data

Output

disable

N-chP-ch

P-chN-ch

OUT

Input instruction

Pull-up resistor that operates only when an input

Note

instruction is executed. (The current flows from VDD to a pin when the pin is at low level.)

VDD

P-ch

P.U.R.

N-ch

Note

Voltage

controller

(+13 V withstanding voltage)

Data Sheet U11369EJ3V0DS

3.4 Recommended Connection of Unused Pins

Table 3-1. List of Unused Pin Connections

Pin Recommended Connection

P00/INT4 Connect to Vss or VDD.

P01/SCK Input: Independently connect to Vss or VDD via a resistor.

P02/SO/SB0 Output: Leave open.

P03/SI/SB1 Connect to Vss.

P10/INT0 and P11/INT1 Connect to Vss or VDD.

P12/TI1/TI2/INT2

P13/TI0

P20/PTO0 Input: Independently connect to Vss or VDD via a resistor.

P21/PTO1 Output: Leave open.

P22/PTO2/PCL

P23/BUZ

P30/LCDCL/MD0

P31/SYNC/MD1

P32/MD2

P33/MD3

P50/D4 to P53/D7 Input: Connect to Vss.

P60/KR0/D0 to P63/KR3/D3 Input: Independently connect to Vss or VDD via a resistor.

S0 to S15 Leave open.

COM0 to COM3

S16/P93 to S19/P90 Input: Independently connect to Vss or VDD via a resistor.

S20/P83 to S23/P80 Output: Leave open.

VLC0 to VLC2 Connect to Vss.

BIAS Connect to Vss only when none of VLC0, VLC1 or VLC2 is used.

Note

XT1

Note

XT2

VPP Always connect to VDD directly.

Output: Connect to Vss.

Output: Leave open.

In other cases, leave open.

Connect to Vss.

Leave open.

PD75P3116

Note When the subsystem clock is not used, select SOS.0 = 1 (on-chip feedback

resistor not used).

Data Sheet U11369EJ3V0DS

PD75P3116

4. Mk I AND Mk II MODE SELECTION FUNCTION

Setting the stack bank selection (SBS) register for the µPD75P3116 enables the program memory to be switched

between the Mk I mode and Mk II mode. This function is applicable when using the

PD753104, 753106, or 753108.

When bit 3 of SBS is set to 1: Sets the Mk I mode (supports the Mk I mode for the

When bit 3 of SBS is set to 0: Sets the Mk II mode (supports the Mk II mode for the µPD753104, 753106, and 753108)

4.1 Differences Between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode for the

Table 4-1. Differences Between Mk I Mode and Mk II Mode

Item Mk I Mode Mk II Mode

Program counter PC13-0

Program memory (bytes) 16384

Data memory (bits) 512 × 4

Stack Stack bank Selectable via memory banks 0 and 1

No. of stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 instruction Not available Available

CALLA !addr1 instruction

Instruction CALL !addr instruction 3 machine cycles 4 machine cycles

execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles

Supported mask ROM products When set to Mk I mode: When set to Mk II mode:

PD753104, 753106, and 753108

PD75P3116 to evaluate the

PD753104, 753106, and 753108)

PD75P3116.

PD753104, 753106, and 753108

Caution The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this

mode is effective for enhancing software compatibility with products that have a program area of more

than 16 KB.

With regard to the number of stack bytes during execution of subroutine call instructions, the usable

area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes

longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and

processing performance than on software compatibility, the Mk I mode should be used.

Data Sheet U11369EJ3V0DS

PD75P3116

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format

of the stack bank selection register.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

Note

sure to initialize the stack bank selection register to 100×B

Note

be sure to initialize it to 000×B

at the beginning of the program. When using the Mk II mode,

Note Set the desired value for ×.

Figure 4-1. Format of Stack Bank Selection Register

Address 3 2 1 0

SBS3 SBS2 SBS1 SBS0F84H

Symbol

SBS

Stack area specification

Memory bank 0

Memory bank 1

Setting prohibited

0 Be sure to enter “0” for bit 2.

Mode selection specification

01Mk II mode

Mk I mode

Caution SBS3 is set to 1 after RESET input, and consequently the CPU operates in the Mk I mode. When using

instructions for the Mk II mode, set SBS3 to 0 and set the Mk II mode before using the instructions.

Data Sheet U11369EJ3V0DS

PD75P3116

5. DIFFERENCES BETWEEN µPD75P3116 AND µPD753104, 753106, 753108

The µPD75P3116 replaces the internal mask ROM in the µPD753104, 753106, and 753108 with a one-time PROM

and features expanded ROM capacity. The

and 753108 and the µPD75P3116’s Mk II mode supports the Mk II mode in the µPD753104, 753106, and 753108.

Table 5-1 lists differences between the

differences between these products before using them with PROMs for debugging or prototype testing of application

systems or, later, when using them with a mask ROM for full-scale production.

For details of the CPU functions and internal hardware, refer to the User’s Manual.

Table 5-1. Differences Between

PD75P3116’s Mk I mode supports the Mk I mode in the µPD753104, 753106,

PD75P3116 and the µPD753104, 753106, and 753108. Be sure to check the

PD75P3116 and µPD753104, 753106, and 753108

Item

Program counter 12 bits 13 bits 14 bits

Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

Data memory (× 4 bits) 512

Mask options Pull-up resistor for Available Not available

Port 5 (On chip/not on chip can be specified.) (Not on chip)

Split resistor for LCD driving power supply

Wait time after Available Not available RESET (Selectable between 217/fX and 215/fX)

Feedback resistor Available Not available of subsystem clock (Use/not use can be selected.) (Enable)

Pin configuration Pins 5 to 8 P30 to P33

Pins 10 to 13 P50 to P53 P50/D4 to P53/D7

Pins 14 to 17 P60/KR0 to P63/KR3

Pin 21 IC VPP

Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask

PD753104

4096 6144 8192 16384

layouts.

PD753106

Note

PD753108

(Fixed to 215/fX)

P30/MD0 to P33/MD3

P60/KR0/D0 to P63/KR3/D3

PD75P3116

Note 217/fX: 21.8 ms at 6.0 MHz operation, 31.3 ms at 4.19 MHz operation

215/fX: 5.46 ms at 6.0 MHz operation, 7.81 ms at 4.19 MHz operation

Note

Caution There are differences in the amount of noise tolerance and noise radiation between flash memory

versions and mask ROM versions. When considering changing from a flash memory version to a mask

ROM version during the process from experimental manufacturing to mass production, make sure to

sufficiently evaluate commercial samples (CS) (not engineering samples (ES)) of the mask ROM

versions.

Data Sheet U11369EJ3V0DS

6. MEMORY CONFIGURATION

765 0

MBE

RBE

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE

Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits)

RBE

INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits)

RBE

INT0 start address (higher 6 bits) INT0 start address (lower 8 bits)

RBE

INT1 start address (higher 6 bits) INT1 start address (lower 8 bits)

RBE

INTCSI start address (higher 6 bits) INTCSI start address (lower 8 bits)

RBE

INTT0 start address (higher 6 bits) INTT0 start address (lower 8 bits)

RBE

INTT1/INTT2 start address (higher 6 bits) INTT1/INTT2 start address (lower 8 bits)

Figure 6-1. Program Memory Map

CALLF

!faddr instruction

entry address

BRCB

!caddr instruction

branch address

PD75P3116

Branch addresses for the following instructions

• BR !addr

• CALL !addr

• BRA !addr1

• CALLA !addr1

• BR BCDE

• BR BCXA

Note

Branch/call

0020H

007FH 0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

Reference table for GETI instruction

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

address by GETI

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

Note Can only be used in the Mk II mode.

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

to addresses with changes in the PC’s lower 8 bits only.

Data Sheet U11369EJ3V0DS

Figure 6-2. Data Memory Map

PD75P3116

Data area

static RAM

(512 × 4)

Stack area

Note

Display data memory

General-purpose register area

000H

01FH

020H

0FFH

100H

1DFH

1E0H

1F7H 1F8H

1FFH

Data memory

(32 × 4)

256 × 4

(224 × 4)

256 × 4

(224 × 4)

(24 × 4)

(8 × 4)

Not incorporated

Memory bank

F80H

Peripheral hardware area

FFFH

Note Memory bank 0 or 1 can be selected as the stack area.

128 × 4

Data Sheet U11369EJ3V0DS

PD75P3116

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the

instruction’s operand representations (for further details, refer to the RA75X Assembler Package Language User’s

Manual (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and

+ or – symbols are keywords that should be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further details, refer to the

User’s Manual). The number of labels that can be entered for fmem and pmem are restricted.

Representation Coding Format

reg X, A, B, C, D, E, H, L

reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL

rp1 BC, DE, HL

rp2 BC, DE

rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’

rp’1 BC, DE, HL, XA’, BC’, DE’, HL’

rpa HL, HL+, HL–, DE, DL

rpa1 DE, DL

n4 4-bit immediate data or label

n8 8-bit immediate data or label

mem 8-bit immediate data or label

bit 2-bit immediate data or label

fmem FB0H to FBFH, FF0H to FFFH immediate data or label

pmem FC0H to FFFH immediate data or label

addr 0000H to 3FFFH immediate data or label

addr1 0000H to 3FFFH immediate data or label (Mk II mode only)

caddr 12-bit immediate data or label

faddr 11-bit immediate data or label

taddr 20H to 7FH immediate data (however, bit 0 = 0) or label

PORTn Port 0 to Port 3, Port 5, Port 6, Port 8, Port 9

IE××× IEBT, IECSI, IET0 to IET2, IE0 to IE2, IE4, IEW

RBn RB0 to RB3

MBn MB0, MB1, MB15

Note

Note When processing 8-bit data, only even-numbered addresses can be specified.

Data Sheet U11369EJ3V0DS

(2) Operation conventions

A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA); 8-bit accumulator BC: Register pair (BC) DE: Register pair (DE) HL: Register pair (HL) XA’: Expansion register pair (XA’) BC’: Expansion register pair (BC’) DE’: Expansion register pair (DE’) HL’: Expansion register pair (HL’) PC: Program counter SP: Stack pointer CY: Carry flag; bit accumulator PSW: Program status word MBE: Memory bank enable flag RBE: Register bank enable flag PORTn: Port n (n = 0 to 3, 5, 6, 8, 9) IME: Interrupt master enable flag IPS: Interrupt priority selection register IE×××: Interrupt enable flag RBS: Register bank selection register MBS: Memory bank selection register PCC: Processor clock control register .: Delimiter for address and bit (××): Data addressed with ××

××H: Hexadecimal data

PD75P3116

Data Sheet U11369EJ3V0DS

(3) Description of symbols used in addressing area

MB = MBE • MBS

MB = 0

MBE = 0:

MBE = 1:

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

MB = 15, pmem = FC0H to FFFH

addr = 0000H to 3FFFH

addr, addr1 =*7(Current PC) – 15 to (Current PC) – 1

caddr = 0000H to 0FFFH (PC

MBS = 0, 1, 15

MB = 0 (000H to 07FH)

MB = 15 (F80H to FFFH)

MB = MBS

MBS = 0, 1, 15

(Current PC) + 2 to (Current PC) + 16

13,12

= 00B) or

1000H to 1FFFH (PC

2000H to 2FFFH (PC

3000H to 3FFFH (PC

13,12

= 01B) or

= 10B) or

= 11B)

PD75P3116

Data memory

addressing

Program memory

addressing

faddr = 0000H to 07FFH

taddr = 0020H to 007FH

*10

addr1 = 0000H to 3FFFH (Mk II mode only)

*11

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping skip-specified instructions. The value of S varies as

shown below.

• No skip ..................................................................... S = 0

• Skipped instruction is 1-byte or 2-byte instruction .... S = 1

Note

• Skipped instruction is 3-byte instruction

.............. S = 2

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= t

times.

CY) of the CPU clock Φ. Use the PCC setting to select from among four cycle

Data Sheet U11369EJ3V0DS

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