NEC UPD3747D Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD3747

7400 PIXELS CCD LINEAR IMAGE SENSOR

The µ PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes

optical images to electrical signal.

The

PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the

µ

photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.

FEATURES

• Valid photocell : 7400 pixels
m

• Photocell pitch : 4.7

• Photocell size : 4.7 × 4.7 µ m

• Resolution : 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)

• Data rate : 44 MHz MAX. (22 MHz/1 output)

• Output type : 2 outputs in phase

• High sensitivity : 19.0 V/lx•s TYP. (Light source: Daylight color fluorescent lamp)

• Low image lag : 1 % MAX.

• Power supply : +12 V

• Drive clock level : CMOS output under 5 V operation

• On-chip circuits : Reset feed-through level clamp cir cuit s

: Voltage amplifiers

ORDERING INFORMATION

Part Number Package

PD3747D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))

µ

µ

2

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. S14892EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP (K)
Printed in Japan

©

2000

2

BLOCK DIAGRAM

φ

GND

GND

φ

φ

φ

CP

2L

2

1

· · ·· · ·

D135

13141820

10954

φ

D140

2

12

φ

TG

1121

V

OUT

2 (Even)

Data Sheet S14892EJ1V0DS00

OUT

1 (Odd)

V

22

CCD analog shift register

Transfer gate

Photocell

S2

D33

1

2

φ

OD

V

φ

R

2L

S1

D134

Transfer gate

CCD analog shift register

S7399

S7400

φ

1

µµ

µ

µ

PD3747

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))

• µ PD3747D

V

OUT

1

Output signal 1 (Odd)

1

22

µµµµ

PD3747

V

OUT

2

Output signal 2 (Even)

Output drain voltage

No connection

Reset gate clock

Last stage shift register clock 2

No connection

Shift register clock 1

Ground

V

NC

φ

φ

2L

NCNo connection

NCNo connection

NC

φ

φ

GND

OD

R

1

2

PHOTOCELL STRUCTURE DIAGRAM

10

11

2

3

4

5

6

7

8

9

21

20

19

18

17

16

15

14

13

12

GND

φ

CP

NC

φ

2L

NC

NC

NC

φ

2

φ

1

φ

TG

Ground

Reset feed-through level clamp clock

No connection

Last stage shift register clock 2

No connection

No connection

No connection

Shift register clock 2

Shift register clock 1Shift register clock 2

Transfer gate clock

m

µ

4.7

m1.5

µ

3.2

µ

m

Aluminum
shield

Data Sheet S14892EJ1V0DS00

Channel stopper

3

µµµµ

PD3747

ABSOLUTE MAXIMUM RATINGS (TA = +25

C)

°°°°

Parameter Symbol Ratings Unit
Output drain voltage V
Shift register clock voltage V
Reset gate clock voltage V
Reset feed-through level clamp clock voltage V
Transfer gate clock voltage V
Operating ambient temperature T
Storage temperature T

OD

, V

, V

1

2

φ

R

φ

CP

φ

TG

φ

A

stg

2L

φ

φ

−0.3 to +14 V

−0.3 to +8 V

−0.3 to +8 V

−0.3 to +8 V

−0.3 to +8 V

−25 to +55 °C

−40 to +100 °C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = +25

Parameter Symbol MIN. TYP. MAX. Unit
Output drain voltage V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level V
Reset gate clock low level V
Reset feed-through level clamp clock high level V
Reset feed-through level clamp clock low level V
Transfer gate clock high level V
Transfer gate clock low level V
Data rate 2f

OD

, V

1H

2H

φ

φ

, V

1L

2L

φ

φ

RH

φ

RL

φ

CPH

φ

CPL

φ

TGH

φ

TGL

φ

R

φ

, V

, V

C)

°°°°

11.4 12.0 12.6 V

2LH

φ

2LL

φ

4.5 5.0 5.5 V

−0.3 0 +0.5 V

4.5 5.0 5.5 V

−0.3 0 +0.5 V

4.5 5.0 5.5 V

−0.3 0 +0.5 V

4.5 5.0 5.5 V

−0.3 0 +0.5 V
1244MHz

4

Data Sheet S14892EJ1V0DS00

ELECTRICAL CHARACTERISTICS

µµµµ

PD3747

TA = +25°C, VOD = 12 V, f

= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V

φ

R

p-p

,

light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)

Parameter Symbol Test Conditions MIN. T YP. MAX. Unit

Saturation voltage V

sat

Saturation exposure SE Daylight color fluorescent lamp − 0.10 − lx•s
Photo response non-uniformity PRNU V

= 500 mV − 510%

OUT

Average dark signal ADS Light shielding − 0.5 3.0 mV
Dark signal non-uniformity DSNU Light shielding − 8.0 14.0 mV
Power consumption P
Output impedance Z
Response R
Image lag IL V
Offset level
Output fall delay time

Note 1

Note 2

Register imbalance RI V
Total transfer efficie n c y TTE V

W

O

F

V

OS

t

d

Daylight color fluorescent lamp 13.3 19.0 24.7 V/lx•s

= 500 mV − 0.5 1.0 %

OUT

V

= 500 mV − 14 − ns

OUT

= 500 mV 0 1.0 4.0 %

OUT

= 1 V, data rate = 44 MHz 94 98 − %

OUT

Response peak − 550 − nm

Reset feed-through noise
Random noise

Shot noise

Note 1

DR1 V
DR2 V
RFTN Light shielding −300 +300 +900 mV

bit Light shielding, bit clamp mode − 2.0 − mV

σ

line Light shielding, line clamp mode − 8.0 − mV

σ

shot V

σ

/DSNU − 250 − timesDynamic range

sat

/σ bit − 1000 − times

sat

= 500 mV, bit clamp mode − 8.0 − mV

OUT

1.5 2.0 − V

− 350 600 mW

− 0.2 0.3 kΩ

3.7 4.7 5.7 V

Notes 1. Refer to TIMING CHART 2, 3.

2. When the fall time of

2L (t2’) is the TYP. value (refer to TIMING CHART 2, 3). Note that V

φ

the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.

OUT

1 and V

OUT

2 are

Data Sheet S14892EJ1V0DS00

5

µµµµ

PD3747

INPUT PIN CAPACITANCE (TA = +25

C, VOD = 12 V)

°°°°

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

Shift register clock pin capacitance 1 C

Shift register clock pin capacitance 2 C

Last stage shift register clock pin capacitance C

Reset gate clock pin capacitance C
Reset feed-through level clamp clock pin capacitance C
Transfer gate clock pin capacitance C

1

φ

19− 250 300 pF

φ

13 − 250 300 pF

2

φ

210− 250 300 pF

φ

14 − 250 300 pF

L

φ

2L 5 − 10 20 pF

φ

18 − 10 20 pF

R

φ

CP

φ

TG

φ

R4− 10 20 pF

φ

CP 20 − 10 20 pF

φ

TG 12 − 100 150 pF

φ

6

Data Sheet S14892EJ1V0DS00