NEC UPD3739D Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD3739

5000 PIXELS CCD LINEAR IMAGE SENSOR

The µPD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical

signal.

The µPD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers

the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity

µ

version of the previous device, the
high-end business facsimiles.

FEATURES

• Valid photocell : 5000 pixels

• Photocell’s pitch : 7

• High sensitivity : 9.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp)

• Low image lag : 1 % MAX.

• Peak response wavelength : 550 nm (green)

• Resolution : 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side)

• Data rate : 40 MHz MAX. (20 MHz/1 output)

• Output type : 2 outputs out of phase (2 outputs in phase also supported)

• Power supply : +12 V

• Drive clock level : CMOS output under 5 V operation

• On-chip circuit : Automatic

• Pin assign : Functional compatible with the µPD35H71A

PD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and

µ

m

φ

R level adjuster

ORDERING INFORMATION

Part Number Package

µ

PD3739D CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)

The information in this document is subject to change without notice.

Document No. S12744EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan

©

1997

COMPARISON CHART

µ

PD3739

Item

PIN CONFIGURATION Pin 1 GND DGND

Pin 2 NC TEST
Pin 4 NC VDD
Pin 11 NC VSUB
Pin 21 NC AGND
Pin 22 NC DGND

RECOMMENDED
OPERATING CONDITIONS pin external capacitor (pF)

ELECTRICAL
CHARACTERISTICS

TIMING CHART In phase outputs operating Out of phase outputs

DEFINITIONS OF
CHARACTERISTICS ITEMS

RECOMMENDED SOLDERING CONDITIONS Wave soldering is deleted —

Capacitance of reset gate clock

Data rate MIN. (MHz) 0.5 Unspecified
Saturation exposure TYP. (Ix⋅s)
Photo response TYP. 4 ±5

non-uniformity (%) MAX. 10 ±10
Average dark signal TYP. (mV)
Dark signal MIN. 0 –3

non-uniformity (mV) TYP. 4 –1, +3

MAX. 6 +6
Power consumption MAX. (mW)
Response (V/

Offset level TYP. (V) 3.5 3.0
Shift register clock pin

capacitance (pF)

Dynamic range TYP. DR1 375 500
(times) DR2 2143 Undefined

Reset feed-through MIN. 0 Unspecified
noise (mV) TYP. 400 250

Random noise TYP. (mV) 0.7 Undefined

Photo response non-uniformity
Dark signal non-uniformity Absolute value Minus and plus value
Random noise Standard deviation of signal Undefined

Ix⋅s)

Note

MIN. 7.2 4.15

TYP. 9.0 5.2

MAX. 10.8 6.25

MIN. 250 400

TYP. 350 500

MAX. 500 800

MAX. 600 500

timing is added operation only
Absolute value Minus and plus value

level distribution by scan

µ

PD3739

1000 ± 20 % Unspecified

0.17 0.29

0.3 1.0

400 Unspecified

µ

PD35H71A

Note Due to the changing of measurement conditions, and pin capacitance of each devices is almost the same.

(µPD3739: Power supply = 12 V, µPD35H71A: Power supply = 0 V)

2

BLOCK DIAGRAM

GND 1L2

1

V

OUT

2

20

Automatic R level adjuster

OUT

1

V

3

V

OD

19

φ

φφ φφ

R2
18 17

CCD analog shift register

Transfer gate

5

R1

φφ

6

2L1

D9

. . . . . .

S1

D32

CCD analog shift register

Photocell

S2

Transfer gate

22 12

14 13

S5000

D33

φφ

10

11

S4999

9

21

D34

φ

12 TG

µ

PD3739

3

PIN CONFIGURATION (Top View)

CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)

µ

PD3739

Ground

No connection

Output signal 1

No connection

Reset gate clock 1

Last stage shift register clock 2

No connection

No connection

Shift register clock 2

Shift register clock 1

No connection

GND

122

221

NC

V

320

OUT

1

419

NC

φ

R1

518

617

φ

2L1

716

NC

815

NC

φ

21

914

φ

11

10 13

11 12

NC

NC

NC

V

OUT

2

V

OD

φ

R2

φ

1L2

NC

NC

φ

22

φ

12

φ

TG

No connection

No connection

Output signal 2

Output drain voltage

Reset gate clock 2

Last stage shift register clock 1

No connection

No connection

Shift register clock 2

Shift register clock 1

Transfer gate clock

PHOTOCELL STRUCTURE DIAGRAM

5 m

µ

Aluminum
shield

µ

7 m

2 m

µ

Channel stopper

4

µ

PD3739

ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)

Parameter Symbol Ratings Unit
Output drain voltage VOD –0.3 to +15 V
Shift register clock voltage V
Reset gate clock voltage V
Transfer gate clock voltage V

φ

1, Vφ2 –0.3 to +15 V

φ

R1, VφR2 –0.3 to +15 V

φ

TG –0.3 to +15 V

Operating ambient temperature TA –25 to +55 ˚C
Storage temperature Tstg –40 to +100 ˚C

Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;

exceeding the ratings could cause permanent damage. The parameters apply independently.

RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55 ˚C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
Shift register clock low level V
Reset gate clock high level
Reset gate clock low level V
Capacitance of reset gate clock pin external capacitor
Transfer gate clock high level V
Transfer gate clock low level V
Data rate 2f

φ

1H, Vφ2H 4.5 5.0 5.5 V

φ

1L, Vφ2L –0.3 0 +0.5 V

V

φ

R1H, V

φ

R2H

Note 4.5 5.0 5.5 V

φ

R1L, VφR2L Note –0.3 0 +0.5 V

CEXT

φ

R Non-polar type 800 1000 1200 pF

φ

TGH 4.5 5.0 5.5 V

φ

TGL –0.3 0 +0.5 V

φ

R1, 2fφR2 0.5 2 40 MHz

Note Input the reset gate clocks 1 and 2 (φR1, φR2) to pins 5 and 18, respectively, via an input resistor and a capacitor.

Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies

φ

according to the IC, due to the on-chip automatic

R level adjuster. The recommended operating conditions

of reset gate clocks 1, 2 (φR1, φR2) in the table above are for signals applied to the external capacitor.

φ

Remark

1 in the above tables represents φ11, φ12 and φ1L2. φ2 represents φ21, φ22 and φ2L1.

5

µ

ELECTRICAL CHARACTERISTICS

TA = +25 ˚C, VOD = 12 V, f
light source: 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm), input signal clock = 5 V

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Saturation voltage Vsat 1.0 1.5 V
Saturation exposure SE Daylight color fluorescent lamp 0.17 lx•s
Photo response non-uniformity PRNU VOUT = 500 mV 4 10 %
Average dark signal ADS Light shielding 0.3 3.0 mV
Dark signal non-uniformity DSNU Light shielding 0 4.0 6.0 mV
Power consumption PW 200 400 mW
Output impedance ZO 0.2 0.5 kΩ
Response RF Daylight color fluorescent lamp 7.2 9.0 10.8 V/Ix·s
Response peak wavelength 550 nm
Image lag IL VOUT = 1 V 0.3 1.0 %
Offset level
Output fall delay time
Register imbalance RI VOUT = 500 mV 0 4.0 %
Total transfer efficiency TTE VOUT = 500 mV, data rate = 40 MHz 92 98 %
Dynamic range DR1 Vsat/DSNU 375 times

Reset feed-through noise
Random noise σ Light shielding — 0.7 — mV

Note 1

Note 2

φ

1 = 1 MHz, data rate = 2 MHz, storage time = 10 ms

VOS 2.0 3.5 5.0 V
td VOUT = 1 V 20 ns

DR2 Vsat/σ 2143 times

Note 1

RFTN Light shielding 0 400 600 mV

p-p

PD3739

Notes 1. Refer to TIMING CHART 2, 5.

2. Typical value when the respective fall times of φ1L2 and φ2L1 are t11’, t41’ and t2’, t32’ (refer to TIMING
CHART 2, 5). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in
APPLICATION CIRCUIT EXAMPLE.

6

INPUT PIN CAPACITANCE (TA = +25 °C, VOD = 12 V)

Parameter Symbol Pin name Pin No. MIN. TYP. MAX. Unit

Shift register clock pin capacitance 1 C

Shift register clock pin capacitance 2 C

Last stage shift register clock pin capacitance C

Reset gate clock pin capacitance C

Transfer gate clock pin capacitance C

φ

1

φ

11 10 250 350 500 pF

φ

12 13 250 350 500 pF

φ

2

φ

21 9 250 350 500 pF

φ

22 14 250 350 500 pF

φ

L

φ

1L2 17 40 50 100 pF

φ

2L1 6 40 50 100 pF

φ

R

φ

R1 5 8 10 15 pF

φ

R2 18 8 10 15 pF

φ

TG

φ

TG 12 100 150 200 pF

µ

PD3739

7

8

TIMING CHART 1 (Out of phase operation)

φ

TG

11

φ

21

φ

2L1

φ

R1

φ

1

3

5

7

9

OUT

1

V

12

φ

22

φ

1L2

φ

11

27

29

31

33

35

5029

5031

5033

5035

5037

φ

R2

OUT

2

V

Note Input the

Note

2

4

6

8

10

12

Optical black

(22 pixels)

φ

R1 and φR2 pulses continuously during this period, too.

28

30

Invalid photocell

(2 pixels)

32

34

36

Valid photocell

(5000 pixels)

5030

5032

Invalid photocell

(2 pixels)

5034

5036

5038

µ

PD3739