NEC UPD23C32040AL, UPD23C32080AL DATA SHEET
DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD23C32040AL, 23C32080AL
32M-BIT MASK-PROGRAMMABLE ROM
4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The µPD23C32040AL and µPD23C32080AL are 33,554,432 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
PD23C32040AL and µPD23C32080AL are packed in 48-pin PLASTIC TSOP(I) and 44-pin PLASTIC SOP.
µ
Features
• Word organization
4,194,304 words by 8 bits (BYTE mode)
2,097,152 words by 16 bits (WORD mode)
• Page access mode
PD23C32040AL)
BYTE mode : 8 byte random page access (
16 byte random page access (
WORD mode :4 word random page access (
8 word random page access (
= 2.7 V to 3.6 V
• Operating supply voltage : V
Operating supply Access time / Power supply current (Active mode) Standby current
voltage Page access time mA (MAX.) (CMOS level input)
V
CC
3.0 V ± 0.3 V 100 / 25 40 55 30
3.3 V ± 0.3 V 90 / 25
CC
ns (MAX.)
µ
PD23C32080AL)
µ
PD23C32040AL)
µ
PD23C32080AL)
µ
PD23C32040ALµPD23C32080AL
µ
A (MAX.)
µ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15772EJ3V0DS00 (3rd edition)
Date Published February 2003 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001
µµµµ
PD23C32040AL, 23C32080AL
Ordering Information
Part Number Package
PD23C32040ALGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C32040ALGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C32040ALGX-xxx 44-pin PLASTIC SOP (15.24 mm (600))
µ
PD23C32080ALGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C32080ALGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C32080ALGX-xxx 44-pin PLASTIC SOP (15.24 mm (600))
µ
(xxx : ROM code suffix No.)
2
Data Sheet M15772EJ3V0DS
Pin Configurations
/xxx indicates active low signal.
µµµµ
PD23C32040AL, 23C32080AL
48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µµµµ
[
PD23C32040ALGY-xxx-MJH ]
µµµµ
PD23C32080ALGY-xxx-MJH ]
[
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
CC
V
: Supply voltage
GND : Ground
Note
NC
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15772EJ3V0DS
3
µµµµ
PD23C32040AL, 23C32080AL
48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µµµµ
PD23C32040ALGY-xxx-MKH ]
[
µµµµ
[
PD23C32080ALGY-xxx-MKH ]
Marking Side
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
VCC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
48
47
46
45
44
43
42
41
40
39
CC
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
CC
V
: Supply voltage
GND : Ground
Note
NC
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M15772EJ3V0DS
µµµµ
PD23C32040AL, 23C32080AL
44-pin PLASTIC SOP (15.24 mm (600))
µµµµ
PD23C32040ALGX-xxx ]
[
µµµµ
[
PD23C32080ALGX-xxx ]
Marking Side
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
/OE or OE or DC
O0
O8
O1
O9
O2
O10
O3
O11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WORD, /BYTE
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
CC
V
A0 to A20 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
CC
V
: Supply voltage
GND : Ground
Note
NC
: No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15772EJ3V0DS
5
µµµµ
PD23C32040AL, 23C32080AL
Input / Output Pin Functions
Pin name Input / Output Function
WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.
High level : WORD mode (2M-word by 16-bit)
Low level : BYTE mode (4M-word by 8-bit)
A0 to A20
(Address inputs)
O0 to O7, O8 to O14
(Data outputs)
O15, A−1
(Data output 15,
LSB Address input)
/CE
(Chip Enable)
/OE or OE or DC
(Output Enable, Don't care)
V
CC
GND − Ground
NC − Not internally connected. (The signal can be connected.)
Input Address input pins.
A0 to A20 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
A0 to A20 are used as 21 bits address signals.
BYTE mode (4M-word by 8-bit)
A0 to A20 are used as the upper 21 bits of total 22 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
Output Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (4M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (4M-word by 8-bit)
The least significant address bus (A−1).
Input Chip activating signal.
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
Input Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
− Supply voltage
6
Data Sheet M15772EJ3V0DS
Block Diagram
µµµµ
PD23C32040AL, 23C32080AL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
Y-Decoder
Address Input Buffer
X-Decoder
O0
O8
O10O9
O2
O1
O3 O4
Output Buffer
Y-Selector
Memory Cell Matrix
2,097,152 words by 16 bits /
4,194,304 words by 8 bits
O12O11
O5 O6 O7
O14O13
O15, A−1
Logic/InputInput Buffer
WORD, /BYTE
/OE or OE or DC
/CE
Data Sheet M15772EJ3V0DS
7
µµµµ
PD23C32040AL, 23C32080AL
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among " 0 " " 1 " " x " shown in the table below.
Option /OE or OE or DC OE active level
0/OE L
1OE H
x DC Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE /OE Mode Output state
L L Active Data out
H High-Z
H H or L Standby High-Z
Operation mode (Option : 1)
/CE OE Mode Output state
L L Active High-Z
H Data out
H H or L Standby High-Z
Operation mode (Option : x)
/CE DC Mode Output state
L H or L Active Data out
H H or L Standby High-Z
Remark L : Low level input
H : High level input
8
Data Sheet M15772EJ3V0DS
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