NEC UPD16314GJ-002-8EU Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

PD16314

µ

µ µ

DOT CHARACTER VFD CONTROLLER/DRIVER

DESCRIPTION

The µ PD16314 is a VFD controller/driver capable of displaying a dot matrix VFD. It has 80 anode outputs and 24 grid outputs. A single µ PD16314 can display up to 16C x 2L, 20C x 2L, or 24C x 2L. The µ PD16314 has character generator ROM in which 248 x 5 x 8 dot characters are stored.

FEATURES

Dot matrix VFD controller/driver

•

Capable of driving anodes for cursor display (48 units)

•

80 x 8 bits display RAM incorporated

•

Capable of alphanumeric and symbolic display through internal ROM (5 by 8 dots)

•

240 characters plus 8 user-defined characters Display contents

•

16 columns by 2(1) rows + 32(16) cursors, 20 columns by 2(1) rows + 40(20) cursors, or 24 columns by 2(1) rows + 48(24) cursors. Parallel data input/output (switchable between 4 bits and 8 bits) or serial data input/output can be selected.

•

On-chip oscillator

•

Custom ROM supported

•

ORDERING INFORMATION

Part Number Package

PD16314GJ-001-8EU 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 001)

µ

PD16314GJ-002-8EU 144-PIN PLASTIC LQFP(FINE PITCH)(20x20), Standard ROM (ROM code: 002)

µ

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. S13231EJ1V0DS00 (1st edition) Date Published March 2000 NS CP(K) Printed in Japan

The mark

••••

shows major revised point.

©

1997

2

1. BLOCK DIAGRAM

Remark

TEST

/xxx indicates active low signals.

Data Sheet S13231EJ1V0DS00

TEST

/CS

RS,STB

R,/W(/WR)

E(/RD),SCK

SI,SO

0

to DB

DB

DB4 to DB

/RESET

MPU

DS0 DS1

DLS

R,L1

R,L2

OUT

IM

4

3

4

7

OSC

IN

OSCILATIOR

8 8

7

8

DD1

V

INSTRUCTION

REGISTER

V

DD2

I/O

B U F F E R

RESET

CIRCUIT

OSC

DATA

OUT

X

OUT

SDO

3

SLK /CL LE

ADDRESS COUNTER

7

INSTRUCTION

DECORDER

8

8 7

CHARACTER GENERATOR

RAM (CGRAM)

V

SS1

V

SS2

7

8 x 5 x 8 bits

5 5

P ARALLEL T O SERIAL

DATA CONVERTER

TIMING

GENERATOR

7

DISPLAY DATA

RAM (DDRAM)

80 x 8 bits

8

CHARACTER GENERATOR

ROM (CGROM)

248 x 5 x 8 bits

24

CURSOR BLINK

CONTROL CIRCUIT

ANODE SIGNAL

24-BIT SHIFT

REGISTER

24

GRID SIGNAL

DRIVER

80

80-BIT LATCH

80

80-BIT SHIFT

REGISTER

24

80

G1 to G24

A1 to A80

µ µ

µ

PD16314

2. PIN CONFIGURATION (Top View)

A70

A69

A68

A67

A66

A65

A64

108

N.C.

109

A71 A72 A73 A74 A75 A76 A77 A78 A79

A80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10

G9 G8 G7 G6 G5 G4 G3 G2 G1

144

N.C.

1

IN

SS2

DD2

DD1

OUT

V

X

OSC

/RESET

A63

A62

TEST

A61

DLS

DS1

A60

A59

A58

A57

DS0

RS,STB

R,/W(/WR)

A56

A55

A54

A53

A52

0DB1DB2DB3DB4DB5DB6DB7

DB

SI,SO

E(/RD),SCK

A51

A50

A49

A48

A47

IM

A46

A45

/CS

MPU

A44

A43

R,L1

R,L2

A42

/CL

A41

LE

A40

A39

SLK

SDO

A38

A37

73

36

SS1VSS2

OUT

V

TEST

A36

72

37

A35

DD2

V

N.C. A34 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 N.C.

µ

PD16314

µ µ

Remark

Use all power supply pins. Leave N.C. pins open.

Data Sheet S13231EJ1V0DS00

3

3. PIN FUNCTIONS

3.1 Power System

Pin Symbol Pin Name Pin No. I/O Output Description

µ

PD16314

µ µ

DD1

V

SS1

V

DD2

V

SS2

V

Logic power supply pin Logic ground pin 34 VFD driving power supply pin 1,36 VFD driving ground pin 2,35

3

   

Power supply for logic Ground pin for logic Power supply for VFD driving circ ui t Ground pin for VFD driving

4

Data Sheet S13231EJ1V0DS00

3.2 Logic system (Microprocessor Interface)

Pin Symbol Pi n Name Pin No. I/O Output Description

RS,STB Register

select/strobe

/CS Chip select 26 E(/RD),

SCK

R,/W(/WR) Read/write signal

SI,SO Serial I/O 15

DB0 - DB

/RESET Reset 7

Enable(read)/shift clock

(write)

7

Parallel data I/O 16 to 23

13

14

12

I

I I

I

I/O CMOS-

I



 



3-states



When Parallel data transfer is selected, this pin is Register select. L: Select instruc t i on regi ster(IR). H: Select data regis t er(DR). When serial data t ransfer mode is selected, this pin is the strobe input. Data can be input when this signal goes L. Command processi ng i s performed at the rising edge of thi s signal. When this pin i s L, this device is act i ve.

When M68 parallel data trans fer mode is selected (E), this pin is enabled. Data is written at the falling edge. When i80 parallel data transfer selected (/RD), thi s pin is a read-enable pin. When thi s pi n i s L, data is output to the data bus. When serial data t ransfer is selected, thi s pin is the shift clock input. Data is written at the rising edge. When M68 parallel data trans fer mode is selected (R,/ W), this pin is the data transfer select pin. L: Write H: Read When i80 parallel data transfer mode is select ed (/WR), this pin is written a write-enable pin. Data is writt en at rising edge of this signal. When serial data t ransfer mode is selected this pin is fixed to H or L. When serial data t ransfer mode is selected, this pin is used as an I/O pin. When parallel data t rans fer mode is selected, this pin is

0

7

fixed to H or L. DB When parallel data t rans fer mode is selected, these pins are used as I/O pins. When 4-bits transfer mode is selected, DB used. Data is transferred starting from the most significant bit (MSB) and stored sequentiall y. L: Initializes all t he i nt ernal regi sters and commands. Anode and grid outputs are fixed to V

to DB

SS2

4

to DB7 are

.

µ

PD16314

µ µ

Data Sheet S13231EJ1V0DS00

5

µ

µ µ

3.3 Logic System (Other Logic)

Pin Symbol Pin Name Pin No. I/O Output Description

IN

OSC

OUT

OSC

OUT

X DS0 Duty selector 11 DS1 10

IM Interface select 24

MPU Interface select 25

DLS Dis pl ay l ine select 9

R,L1 Anode output select 27

R,L2 28 The relationship between Ox and Ax (anode) is

TEST Test pin 8

OUT

TEST

Oscillator pin 6

5 is externally attached to this pi n.

Oscillator output 4

Test pin 33



CMOS

I

O



The resister for determining t he oscillation frequency

Oscillator signal output pin. Sets the duty ratio. The dut y ratio is determined by

the number of grids. The relat i onship between the duty ratio and these pins is shown in

RATIO SETTING

Selects the interf ac e mode: Serial transfer or parallel transfer. L: Selects serial data transfer H: Selects parallel dat a transfer (In Parallel data transfer mode, the word length differs depending on the instruction.) Selects the interf ac e mode: i80-type CPU mode or M68-type CPU mode. L: Selects i80-t ype CP U mode. H: Selects M68-type CPU mode. Selects the number of display lines at power ON reset or reset. L: Selects 1 line (N H: Selects 2 lines (N

Sets the anode outputs. The Ox pins are set by these pins.

shown in A pin for testing the IC. L or open: Normal operation mode H: Test mode A pin for testing the IC. Leave this pin open.

.

Note

= 0)

Note

= 1)

5 ANODE SETTING

4 DUTY

.

PD16314

Note

N: Display line selection flag for function setting command.

3.4 Logic System (External Extension Driver)

Pin Symbol Pin Name Pin No. I/O Output Description SDO Serial data output 31 SLK Serial clock output 32 /CL Clear si gnal 29

LE Latch enable 30

6

OCMOS OCMOS OCMOS

OCMOS

Data Sheet S13231EJ1V0DS00

Serial data output for extension grid driver. Shift clock pulse for extension grid driver. Clear signal for extension grid driver.

The signal is active low. The grid data stored in the latch of the extension driver is out put when this signal is H. If thi s signal is L, the extension driver outputs L. Latch enable signal for extension grid driver.

3.5 Output Pins

Pin Symbol Pin Nam e Pin No. I/O Output Description

µ

PD16314

µ µ

G1 - G24 Grid output A1 - A80

(O1 - O80)

Note

Refer to

Anode output

4 DUTY RATIO SETTING

Note Note

.

OCMOS OCMOS

Grid signal output pins. Anode signal output pins.

Data Sheet S13231EJ1V0DS00

7

4. DUTY RATIO SETTING

µ

PD16314

µ µ

The duty ratio of the µ PD16314 is set by DS0 and DS1 as shown in Table 4

Table 4

DS0 DS1 Duty ratio

L L 1/16 (# of grids = 16) L H 1/20 (# of grids = 20) H L 1/24 (# of grids = 24) HH

Note

When to set to 1/40 duty mode, the external extension grid driver can be used.

1. Duty Ratio Setting

−−−−

1/40 (# of grids = 40)

Note

5. ANODE SETTING

The anode pins are set by R,L1 and R,L2 as shown in Table 5

Table 5

R,L1 R,L2 Table No.

LL

LH HL HH

1. Anode Setting: 2 Line Display (N=1)

−−−−

Table 5 Table 5 Table 5 Table 5

−−−−

−2

−3

−4

1 below.

1 below

−−−−

.

8

Data Sheet S13231EJ1V0DS00

µ

PD16314

µ µ

Table 5

2

. Anode Pin Layout (When R,L1 = L, R,L2 = L)

−−−−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A35 109 N.C. 38 A1 74 A36 110 A71 39 A2 75 A37 111 A72 40 A3 76 A38 112 A73 41 A4 77 A39 113 A74

42 A5 78 A40 114 A75 7 /RESET 43 A6 79 A41 115 A76 8 TEST 44 A7 80 A42 116 A77 9 DLS 45 A8 81 A43 117 A78

10 DS1 46 A9 82 A44 118 A79 11 DS0 47 A10 83 A45 119 A80 12 R,/W(/WR) 48 A11 84 A46 120 G24 13 RS,STB 49 A12 85 A47 121 G23 14 E(/RD),SCK 50 A13 86 A48 122 G22 15 SI,SO 51 A14 87 A49 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A15 88 A50 124 G20

53 A16 89 A51 125 G19

54 A17 90 A52 126 G18

55 A18 91 A53 127 G17

56 A19 92 A54 128 G16

57 A20 93 A55 129 G15

58 A21 94 A56 130 G14

59 A22 95 A57 131 G13

24 IM 60 A23 96 A58 132 G12 25 MPU 61 A24 97 A59 133 G11 26 /CS 62 A25 98 A60 134 G10 27 R,L1 63 A26 99 A61 135 G9 28 R,L2 64 A27 100 A62 136 G8 29 /CL 65 A28 101 A63 137 G7 30 LE 66 A29 102 A64 138 G6 31 SDO 67 A30 103 A65 139 G5 32 SLK 68 A31 104 A66 140 G4 33 TEST 34 V 35 V 36 V

SS1

SS2

DD2

OUT

69 A32 105 A67 141 G3

70 A33 106 A68 142 G2

71 A34 107 A69 143 G1

72 N.C. 108 A70 144 N.C.

Data Sheet S13231EJ1V0DS00

9

µ

PD16314

µ µ

Table 5

3

. Anode Pin Layout (When R,L1 = L, R,L2 = H)

−−−−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A6 109 N.C.

38 A40 74 A5 110 A71

39 A39 75 A4 111 A72

40 A38 76 A3 112 A73

41 A37 77 A2 113 A74

42 A36 78 A1 114 A75 7 /RESET 43 A35 79 A41 115 A76 8 TEST 44 A34 80 A42 116 A77 9 DLS 45 A33 81 A43 117 A78

10 DS 11 DS

1

0

46 A32 82 A44 118 A79

47 A31 83 A45 119 A80

12 R,/W(/WR) 48 A30 84 A46 120 G24 13 RS,STB 49 A29 85 A47 121 G23 14 E(/RD),SCK 50 A28 86 A48 122 G22 15 SI,SO 51 A27 87 A49 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A26 88 A50 124 G20

53 A25 89 A51 125 G19

54 A24 90 A52 126 G18

55 A23 91 A53 127 G17

56 A22 92 A54 128 G16

57 A21 93 A55 129 G15

58 A20 94 A56 130 G14

59 A19 95 A57 131 G13

24 IM 60 A18 96 A58 132 G12 25 MPU 61 A17 97 A59 133 G11 26 /CS 62 A16 98 A60 134 G10 27 R,L1 63 A15 99 A61 135 G9 28 R,L2 64 A14 100 A62 136 G8 29 /CL 65 A13 101 A63 137 G7 30 LE 66 A12 102 A64 138 G6 31 SDO 67 A11 103 A65 139 G5 32 SLK 68 A10 104 A66 140 G4

SS1

SS2

DD2

OUT

69 A9 105 A67 141 G3

70 A8 106 A68 142 G2

71 A7 107 A69 143 G1

72 N.C. 108 A70 144 N.C.

33 TEST 34 V 35 V 36 V

10

Data Sheet S13231EJ1V0DS00

µ

PD16314

µ µ

Table 5

4

. Anode Pin Layout (When R,L1 = H, R,L2 = L)

−−−−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A75 109 N.C.

38 A41 74 A76 110 A10

39 A42 75 A77 111 A9

40 A43 76 A78 112 A8

41 A44 77 A79 113 A7

42 A45 78 A80 114 A6 7 /RESET 43 A46 79 A40 115 A5 8 TEST 44 A47 80 A39 116 A4 9 DLS 45 A48 81 A38 117 A3

10 DS1 46 A49 82 A37 118 A2 11 DS0 47 A50 83 A36 119 A1 12 R,/W(/WR) 48 A51 84 A35 120 G24 13 RS,STB 49 A52 85 A34 121 G23 14 E(/RD),SCK 50 A53 86 A33 122 G22 15 SI,SO 51 A54 87 A32 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A55 88 A31 124 G20

53 A56 89 A30 125 G19

54 A57 90 A29 126 G18

55 A58 91 A28 127 G17

56 A59 92 A27 128 G16

57 A60 93 A26 129 G15

58 A61 94 A25 130 G14

59 A62 95 A24 131 G13

24 IM 60 A63 96 A23 132 G12 25 MPU 61 A64 97 A22 133 G11 26 /CS 62 A65 98 A21 134 G10 27 R,L1 63 A66 99 A20 135 G9 28 R,L2 64 A67 100 A19 136 G8 29 /CL 65 A68 101 A18 137 G7 30 LE 66 A69 102 A17 138 G6 31 SDO 67 A70 103 A16 139 G5 32 SLK 68 A71 104 A15 140 G4

SS1

SS2

DD2

OUT

69 A72 105 A14 141 G3

70 A73 106 A13 142 G2

71 A74 107 A12 143 G1

72 N.C. 108 A11 144 N.C.

33 TEST 34 V 35 V 36 V

Data Sheet S13231EJ1V0DS00

11

µ

PD16314

µ µ

•

Table 5

5

. Anode Pin Layout (When R,L1 = H, R,L2 = H)

−−−−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A46 109 N.C.

38 A80 74 A45 110 A10

39 A79 75 A44 111 A9

40 A78 76 A43 112 A8

41 A77 77 A42 113 A7

42 A76 78 A41 114 A6 7 /RESET 43 A75 79 A40 115 A5 8 TEST 44 A74 80 A39 116 A4 9 DLS 45 A73 81 A38 117 A3

10 DS1 46 A72 82 A37 118 A2 11 DS0 47 A71 83 A36 119 A1 12 R,/W 48 A70 84 A35 120 G24 13 RS,STB 49 A69 85 A34 121 G23 14 E(/RD),SCK 50 A68 86 A33 122 G22 15 SI,SO 51 A67 87 A32 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A66 88 A31 124 G20

53 A65 89 A30 125 G19

54 A64 90 A29 126 G18

55 A63 91 A28 127 G17

56 A62 92 A27 128 G16

57 A61 93 A26 129 G15

58 A60 94 A25 130 G14

59 A59 95 A24 131 G13

24 IM 60 A58 96 A23 132 G12 25 MPU 61 A57 97 A22 133 G11 26 /CS 62 A56 98 A21 134 G10 27 R,L1 63 A55 99 A20 135 G9 28 R,L2 64 A54 100 A19 136 G8 29 /CL 65 A53 101 A18 137 G7 30 LE 66 A52 102 A17 138 G6 31 SDO 67 A51 103 A16 139 G5 32 SLK 68 A50 104 A15 140 G4

SS1

SS2

DD2

OUT

69 A49 105 A14 141 G3

70 A48 106 A13 142 G2

71 A47 107 A12 143 G1

72 N.C. 108 A11 144 N.C.

33 TEST 34 V 35 V 36 V

12

Data Sheet S13231EJ1V0DS00

µ

PD16314

µ µ

Table 5

6

. Anode Setting: 1 Line Display (N=0)

−−−−

R,L1 R,L2 Table No.

Don’t care Don’t care

Table 5

L Tabl e 5

H Table 5

7

. Anode Pin Layout (When R,L2 = L)

−−−−

7

−

8

−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A35 109 N.C.

38 A1 74 A36 110 Unused

39 A2 75 A37 111

40 A3 76 A38 112

41 A4 77 A39 113

42 A5 78 A40 114 7 /RESET 43 A6 79 Unused 115 8 TEST 44 A7 80 116 9 DLS 45 A8 81 117

10 DS1 46 A9 82 118 11 DS0 47 A10 83 119 12 R,/W 48 A11 84 120 G24 13 RS,STB 49 A12 85 121 G23 14 E(/RD),SCK 50 A13 86 122 G22 15 SI,SO 51 A14 87 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A15 88 124 G20

53 A16 89 125 G19

54 A17 90 126 G18

55 A18 91 127 G17

56 A19 92 128 G16

57 A20 93 129 G15

58 A21 94 130 G14

59 A22 95 131 G13

24 IM 60 A23 96 132 G12 25 MPU 61 A24 97 133 G11 26 /CS 62 A25 98 134 G10 27 R,L1 63 A26 99 135 G9 28 R,L2 64 A27 100 136 G8 29 /CL 65 A28 101 137 G7 30 LE 66 A29 102 138 G6 31 SDO 67 A30 103 139 G5 32 SLK 68 A31 104 140 G4

SS1

SS2

DD2

OUT

69 A32 105 141 G3

70 A33 106 142 G2

71 A34 107 143 G1

72 N.C. 108 144 N.C.

33 TEST 34 V 35 V 36 V

Data Sheet S13231EJ1V0DS00

13

µ

PD16314

µ µ

Table 5

8

. Anode Pin Layout (When R,L2 = H)

−−−−

No. Name No. Name No. Name No. Name

1V 2V 3V 4X 5OSC 6OSC

DD2

SS2

DD1

OUT

IN

37 N.C. 73 A6 109 N.C.

38 A40 74 A5 110 Unused

39 A39 75 A4 111

40 A38 76 A3 112

41 A37 77 A2 113

42 A36 78 A1 114 7 /RESET 43 A35 79 Unused 115 8 TEST 44 A34 80 116 9 DLS 45 A33 81 117

10 DS1 46 A32 82 118 11 DS0 47 A31 83 119 12 R,/W 48 A30 84 120 G24 13 RS,STB 49 A29 85 121 G23 14 E(/RD),SCK 50 A28 86 122 G22 15 SI,SO 51 A27 87 123 G21 16 DB 17 DB 18 DB 19 DB 20 DB 21 DB 22 DB 23 DB

0

1

2

3

4

5

6

7

52 A26 88 124 G20

53 A25 89 125 G19

54 A24 90 126 G18

55 A23 91 127 G17

56 A22 92 128 G16

57 A21 93 129 G15

58 A20 94 130 G14

59 A19 95 131 G13

24 IM 60 A18 96 132 G12 25 MPU 61 A17 97 133 G11 26 /CS 62 A16 98 134 G10 27 R,L1 63 A15 99 135 G9 28 R,L2 64 A14 100 136 G8 29 /CL 65 A13 101 137 G7 30 LE 66 A12 102 138 G6 31 SDO 67 A11 103 139 G5 32 SLK 68 A10 104 140 G4

SS1

SS2

DD2

OUT

69 A9 105 141 G3

70 A8 106 142 G2

71 A7 107 143 G1

72 N.C. 108 144 N.C.

33 TEST 34 V 35 V 36 V

14

Data Sheet S13231EJ1V0DS00

µ

PD16314

µ µ

6. VFD DISPLAY

The µ PD16314 can display 24 characters x 2 lines, and a VFD can be connected as shown in the figure below.

A1

A40

A41

PD16314

µ

A80

G1

G2

Figure 6

1. VFD Display

−−−−

G24

A10

A71 A75

A76 A80

A1 A5

A6

Data Sheet S13231EJ1V0DS00

15