NEC UPD16311GC-AB6 Datasheet
DATA SHEET
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16311
1/8- to 1/16-DUTY FIPTM (VFD) CONTROLLER/DRIVER
The
PD16311 is a FIP (Fluorescent Indicator Panel or Vacuum Fluorescent Display) controller/driver that is
driven on a 1/8- to 1/16 duty factor. It consists of 12 segment output lines, 8 grid output lines, 8 segment/grid output
drive lines, a display memory, a control circuit, and a key scan circuit. Serial data is input to the PD16311 through a
three-line serial interface. This FIP controller/driver is ideal as a peripheral device of a single-chip microcomputer.
FEATURES
• Many display modes (12-segment & 16-digit to 20-segment & 8-digit)
• Key scanning (12 4 matrices)
• Dimming circuit (eight steps)
• High-voltage output (VDD 35 V max).
• LED ports (5 chs., 20 mA max).
• General-purpose input port (4 bits)
• No external resistor necessary for driver outputs (P-ch open-drain + pull-down resistor output)
• Serial interface (CLK, STB, DIN, D
OUT
)
ORDERING INFORMATION
Part Number Package
PD16311GC-AB6 52-pin plastic QFP ( 14)
Document No. IC-3306 (1st edition)
Date Published March 1997 P
Printed in Japan
1993©
BLOCK DIAGRAM
PD16311
DOUT
CLK
STB
V
DD
Key
Key
SW1
SW
DIN
Command decoder
Serial I/F
Display memory
20 bit × 16 Word
R
OSC
Timing generator
key scan
Key data memory (4 × 12)
Dimming
circuit
20 12
20-bit output latch
8
8
8
Data selector
Seg
Seg12
Seg13/Grid16
driver
Segment/grid
Seg20/Grid9
1
Grid1
1
to
4
4
16 8
16-bit shift register
Grid driver Segment driver
Grid8
5-bit latch
to
4
4
4-bit latch
LED1 LED5
VDD
(+5 V)
SS
V
(0 V)
EE
V
(−30 V)
2
PIN CONFIGURATION (Top View)
52 OSC
51 VSS50 LED1
PD16311
49 LED2
48 LED3
47 LED4
46 LED5
45 VDD
44 Grid1
43 Grid2
42 Grid3
41 Grid4
40 Grid5
1SW1
2SW2
3SW3
4SW4
5DOUT
6DIN
7IC
8CLK
9STB
10KEY
1
11KEY2
12KEY3
13KEY4
39 Grid6
38 Grid7
37 Grid8
36 Seg20/Grid9
35 Seg19/Grid10
34 VEE
33 VDD
32 Seg18/Grid11
31 Seg17/Grid12
30 Seg16/Grid13
29 Seg15/Grid14
28 Seg14/Grid15
27 Seg13/Grid16
14VDD
15Seg1/KS1
16Seg2/KS2
17Seg3/KS3
18Seg4/KS4
Use all the power pins. Leave the IC pin open.
19Seg5/KS5
20Seg6/KS6
21Seg7/KS7
22Seg8/KS8
23Seg9/KS9
24Seg10/KS10
25Seg11/KS11
26Seg12/KS12
3
Pin Function
Pin No. Symbol Pin Name Description
6DINData input Inputs serial data at rising edge of shift clock, starting from lower
bit.
5D
9 STB Strobe Initializes serial interface at rising or falling edge to make
8 CLK Clock input Reads serial data at rising edge, and outputs data at falling edge.
52 OSC Oscillator pin Connect resistor for determining oscillation frequency to this pin.
15 to 26 Seg1/KS1 to
44 to 37 Grid1 to Grid
27 to 32
35 to 36
50 to 46 LED1 to LED
10 to 13 Key1 to Key
1 to 4 SW1 to SW
14, 33, 45 V
51 V
34 V
7 IC Internally connected Be sure to leave this pin open (this pin is at VDD level).
OUT
12
12
/KS
Seg
Seg13/Grid16 to
20
9
/Grid
Seg
DD
SS
EE
Data output Outputs serial data at falling edge of shift clock, starting from
lower bit. This is N-ch open-drain output pin.
PD16311 waiting for reception of command. Data input after
STB has fallen is processed as command. While command data
is processed, current processing is stopped, and serial interface
is initialized. While STB is high, CLK is ignored.
High-voltage output
Segment output pins (Dual function as key source)
(segment)
6
High-voltage output (grid) Grid output pins
High-voltage output
These pins are selectable for segment or grid output.
(segment/grid)
5
LED output CMOS output. +20 mA max.
4
Key data input Data input to these pins is latched at end of display cycle.
4
Switch input These pins constitute 4-bit general-purpose input port.
Logic power 5 V 10 %
Logic ground Connect this pin to GND of system.
Pull-down level VDD 35 V max.
PD16311
4
PD16311
Display RAM Address and Display Mode
The display RAM stores the data transmitted from an external device to the PD16311 through the serial interface,
and is assigned addresses as follows, in units of 8 bits:
Seg
1
00 H
03 H
06 H
09 H
0 CH
0 FH
12 H
15 H
18 H
1 BH
1 EH
21 H
24 H
27 H
2 AH
2 DH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Seg
4
00 H
03 H
06 H
09 H
0 CH
0 FH
12 H
15 H
18 H
1 BH
1 EH
21 H
24 H
27 H
2 AH
2 DH
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Seg
8
01 H
04 H
07 H
0 AH
0 DH
10 H
13 H
16 H
19 H
1 CH
1 FH
22 H
25 H
28 H
2 BH
2 EH
Seg
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
12
01 H
04 H
07 H
0 AH
0 DH
10 H
13 H
16 H
19 H
1 CH
1 FH
22 H
25 H
28 H
2 BH
2 EH
Seg
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
02 H
05 H
08 H
0 BH
0 EH
11 H
14 H
17 H
1 AH
1 DH
20 H
23 H
26 H
29 H
2 CH
2 FH
Seg
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
20
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG1
DIG
DIG
DIG
DIG
1
2
3
4
5
6
7
8
9
10
11
2
13
14
15
16
0
b
XX H
4
b3b
L
XX H
7
b
U
Lower 4 bits Higher 4 bits
Only the lower 4 bits of the addresses assigned to Seg17 through Seg20 are valid, and the higher 4 bits are
ignored.
5
PD16311
Key Matrix and Key-Input Data Storage RAM
The key matrix is of 12 4 configuration, as shown below.
KEY
1
KEY
2
KEY
3
KEY
4
1
2
3
4
5
6
7
8
9
10
11
/KS
1
Seg
/KS
2
Seg
/KS
3
Seg
/KS
4
Seg
/KS
5
Seg
/KS
6
Seg
/KS
7
Seg
/KS
8
Seg
/KS
9
Seg
/KS
10
Seg
/KS
11
Seg
12
/KS
12
Seg
The data of each key is stored as illustrated below, and is read by a read command, starting from the least
significant bit.
KEY1…KEY4KEY1…KEY
4
Seg1/KS
Seg3/KS
Seg5/KS
Seg7/KS
Seg9/KS
Seg11/KS
1
3
5
7
9
11
Seg2/KS
Seg4/KS
Seg6/KS
Seg8/KS
Seg10/KS
Seg12/KS
2
4
6
8
10
12
Reading sequence
b0------------b3 b4------------b7
When the most significant bit of data (Seg12 b7) has been read, the least significant bit of the next data (Seg1 b0) is
read.
LED Port
Data is written to the LED port by a write command, starting from the least significant bit of the port. When a bit of
this port is 0, the corresponding LED lights; when the bit is 1, the LED goes off. The data of bits 6 through 8 is
ignored.
MSB
−−−b4 b3 b2 b1 b0
Don't care
LSB
LED1
LED2
LED3
LED4
LED5
On power application, all the LEDs remain dark.
6
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