NEC UPC8110GR-E1, UPC8110GR Datasheet

DATA SHEET

BIPOLAR ANALOG INTEGRATED CI RCUIT

PC8110GR

µµµµ

1 GHz DIRECT QUADRATURE MODULATOR

FOR DIGITAL MOBILE COMMUNICATION

DESCRIPTION

The

PC8110GR is a sillicon monolithic integrated circuit designed as 1 GHz direct quadrature modulator for

µ

digital mobile communication systems. This modulator housed in a 20 pin plastic SSOP that easy to install and contributes to miniaturizing the system.

The device has power save function and can operates 2.7 to 3.6 V supply voltage to realize low power

consumption.

FEATURES

• Direct modulation range : 800 MHz to 1 GHz

• Supply voltage range : VCC = 2.7 to 3.6 V

• Low operation current : ICC = 24 mA typical @ VCC = 3 V

• Low phase difference due to digital phase shifter is adopted.

• 20 pin SSOP suitable for high density surface mounting.

• Low current sleep mode

APPLICATION

• Digital cellular phone (PDC, IS-54/IS-136, GSM etc..)

ORDERING INFORMATION

PART NUMBER PACKAGE PACKING FORM

µ

PC8110GR-E1 20 pin plastic SSOP Carrier tape width 12 mm. Q’ty 2.5 kp/Reel Pin 1 indicated pull -out

direction of tape.

Remark

For evaluation sample order, please contact your local NEC sales office. (Order number:

Caution electro-static sensitive device

PC8110GR)

µ

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. P11074EJ3V0DS00 (3rd edition) Date Published October 1999 N CP(K) Printed in Japan

The mark shows major revised points.

©

1996, 1999

INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS

(Top View)

µµµµ

PC8110GR

SERIES PRODUCTS

SERIES TYPE

10

1

20

90˚

2

3

4

5

6

7

8

9

Phase Sitter

REG.

19

18

17

16

15

14

13

12

LO

1. GND

2. LO

3. GND

4. Q-INPUT

5. Q-INPUT

6. I-INPUT

7. I-INPUT

8. GND

9. GND

10. RF

11. GND

12. GND

13.

CC

V

14. GND

15. GND

16. Power Save (V

17. GND

18.

CC

V

19. GND

20.

in

out

PS)

11

PART NUMBER

f LO1 (MHz)

in

f MOD (MHz)

out

f I/Q (MHz)

Up-Converter

out

f RF

(MHz)

APPLICATION

150 MHz Quadrature MOD

PC8101GR 100 t o 300 50 to 150 DC to

µ

0.5

External CT2, Digital Comm.

Up-Con+Quadrature MODµPC8104GR 100 to 400 DC to 10 900 to 1900 PHS, PDC etc.. 400 MHz Quadrature

MOD 1 GHz direct Quad MOD

Remark

As for detail information of series products, please refer to each data sheet.

PC8105GR 100 to 400 DC to 10 External PDC, IS-136, GSM,

µ

PHS

PC8110GR 800 to 1000 DC to 10 Direct PDC, IS-136, GSM etc .

µ

2

Data Sheet P11074EJ3V0DS00

APPLICATION EXAMPLE

PDC 900 MHz (Direct Modulation Type)

µµµµ

PC8110GR

ANT

RX

SW

TX

PA

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT TEST CONDITIONS Supply Voltage V Power Save Voltage V Power Dissipation P Operating Temperature T Storage Temperature T

DEMO

I Q

RSSI OUT

RSSI

PLL

I

Q

BPF

0˚

F/F

90˚

900 MHz Direct Quadrature Modulator PC8110GR

µ

CC

PS

D

opt

stg

4.0 V TA = +25 °C

430 mW

40 to +85 °C

−

55 to +150 °C

−

T

A

= +85 °C

Note 1

Note 1.

Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS Supply Voltage V Operating Temperature T LO Input Frequency fL LO Input Power Level PL I/Q Input Frequency f I/Q Input Voltage V

CC

opt

Oin

I/Qin

2.7 3.0 3.6 V 40 +25 +85 °C

−

800 900 1000 MHz

15

−

10

−

7dBm

−

DC 10 MHz

500 mV 250 Differenti al i nput

Data Sheet P11074EJ3V0DS00

p-p

Single ended input

3

µµµµ

PC8110GR

ELECTRICAL CHARACTERISTICS (TA = 25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS Circuit Current I Circuit Current at Power Save Mode I Maximum Output Power P LO Carrier Leak LoL Image Rejection (Side Band Leak ) ImR I/Q 3rd Order Intermodulation

Distortion Power Save Rise Time T Power Save Fall Time T

CC

CC(PS)

o(sat)

3I/Q

IM

PS(RISE)

PS(FALL)

20 24 33 m A No input signal

10 uA VPS ≤ 0.5 V (Low)

LOin

f

13

−

10 dBM

−

35

−

40

−

45

−

30 dBc

−

30 dBc

−

30 dBc

−

= 948 MHz

LOin

= −10 dBm

P

I/Q

= 2.625 kHz

f I/Q (DC) = V

I/Qin

= 500 mV

V (Single ended)

35 25

sVPS: Low → High

µ

sVPS: High → Low

µ

CC

STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25 °C, VCC = 3.0 V, Unless Otherwise Specified VPS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS I/Q Input Impeadance Z LO Input VSWR VSWR (Lo) 1.5 : 1 RF Output VSWR VSWR

I/Qin

(RF)

2.2 V (Hgih))

≥≥≥≥

150 k

1.5 : 1

Ω

−

I/Q

f

= DC to 10 MHz fLO = 948 MHz fLO = 948 MHz

2.2 V (High))

≥≥≥≥

/2

p-p

4

Data Sheet P11074EJ3V0DS00

PIN EXPLANATION

5 6

8 7

µµµµ

PC8110GR

ASSIGNMENT

No.

1L

2

Oin

GND

SUPPLY VOL. (V)



0

(for Local

18

3L

5Q V

6Q V

7I V

8I V

9

Amp. Block)

Oin

GND



CC

/2

0

(for Quadrature

13

Modulator Block)

16

PIN VOL. (V)

2.6 L

FUNCTION AND APPLICATION EQUIVALENT CIRCUIT

O

input for phase shifter. Connect around 50 Ω between 1 and 3 pin to match to 50 Ω.



Connect to the ground with minimum inductance. Track length should be kept as short as possible.

2.6 Bypass of L This pin is grounded through around 33 pF capacitor.



Input for Q signal. This input impedance is 150 kΩ. In case of that I/Q i nput signals are single ended, amplitude of the signal is 500 mVp-p max .



Input for Q signal. This input impedance is 150 kΩ. In case of that I/Q i nput signals are single ended, V DC signal should be input. In case of that I/Q i nput signals are differential, amplit ude of the signal is 250 mVp-p max.



Input for I signal. This input impedance is 150 kΩ. In case of that I/Q i nput signals are single ended, V DC signal should be input. In case of that I/Q i nput signals are differential, amplit ude of the signal is 250 mVp-p max.



Input for I signal. This input impedance is 150 kΩ. In case of that I/Q i nput signals are single ended, amplitude of the signal is 500 mVp-p max .



Connect to the ground with minimum inductance. Track length should be kept as short as possible.

O

input.

CC

/2 biased

CC

/2 biased

1

3

Note 2



Data Sheet P11074EJ3V0DS00

5

µµµµ

PC8110GR

ASSIGNMENT

No.

11 RF

12

out

GND

SUPPLY VOL. (V)

(for Output Push-pull Amplifier)

CC

14

V

2.7 to 3.6 (for Output Amplifier of Modulator)

17 Power Save V

PIN VOL. (V)



1.6 Output from modulator.

FUNCTION AND APPLICATION EQUIVALENT CIRCUIT

This is single-end push-pull amplifier. So this output impedance is Low.

0



Connect to the ground with minimum inductance. Track length should be kept as

From Modulator

11

short as possible.



Supply voltage pin for Output Amplifier of modulator. Internal regulator can be kept stable condition of supply bias agai nst

CC

.

P/S



the variable temperature or V Power save control pin can be

controlled ON/SLEEP state with bias as follows;

P/S

V

STATE

17

2.2 to 3.6 ON 0 to 0.5 SLEEP

19 V

4 10 15 20

Note 2.

Relations between amplitude and V

Supply Voltage

VCC (V)

2.7 to 3.6 1.35 to 1.8

CC

2.7 to 3.6

GND 0



I/Q DC Voltage (V)

CC

/2 = I = I = Q = Q

V

Supply voltage pin for modulator except output Amplifier. Internal regulator can be kept stable condition of supply bias agai nst

CC

the variable temperature or V

.

Connect to the ground with minimum inductance. Track length should be kept as short as possible.

CC

/2 bias of input signal are following.

I/Qin

P

- I/Q Input Signal - mVp-p

Single ended input

I = Q

500

≤



Differential input

I = I = Q = Q

250

≤

6

Data Sheet P11074EJ3V0DS00

EXPLANATION OF INTERNAL FUNCTION

BLOCK FUNCTION/OPERATION BLOCK DIAGRAM

from LO

90 ° PHASE SHIFTER

BUFFER AMP.

Input signal from LO is send to digital ci rc ui t of T-type flip-flop through frequency doubler. Output signal from T-type F/F i s changed to

O

same frequency as L quadrature phase shift, 0 °, 90 °, 180 °, 270 °. These circuits have f unction of self phase correction to make correc tly quadrature signals.

Buffer amplifiers f or each phase signals to send to each mixers.

input and that have

in

× 2

÷ 2 F/F

µµµµ

PC8110GR

MIXER E ac h signals from buffer amp. are quadrat ure

modulated with two double-balanced mi x ers. High accurate phase and amplitude i nput s are realized to good performance for image rejection.

ADDER Output s i gnal s from each mixers are added with

adder and send to final amplifier.

I I

Q Q

to MOD

out

Data Sheet P11074EJ3V0DS00

7

TYPICAL CHARACTERISTICS

Unless otherwise specified T

500 mV

p-p

(Single ended), f

I/Q

= 2.625 kHz, f

RNYQ: a = 0.5.

µµµµ

PC8110GR

A

= +25 °C, VCC = VPS = 3 V, I/Q DC/offset = I/Q DC offset = 1.5 V, I/Q Input signal =

LOin

= 948 MHz, P

LOin

= −10 dBm, <PDC> Transmission speed: 42 kbps,

CIRCUIT CURRENT vs SUPPLY VOLTAGE

30

TA = +25 ˚C

A

= –40 ˚C

T T

A

25

= +85 ˚C

CC

= V

V

PS

I/Q (DC) = VCC/2 RF None

20

15

- Circuit Current - mA

CC

I

10

5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VCC - Supply Voltage - V

CIRCUIT CURRENT vs POWER SAVE VOLTAGE

30

TA = +25 ˚C

A

= –40 ˚C

T

A

= +85 ˚C

25

T V

CC

= 3 V I/Q (DC) = 1.5 V RF None

20

15

- Circuit Current - mA

CC

I

10

5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VPS - Power Save Voltage - V

8

Data Sheet P11074EJ3V0DS00

µµµµ

PC8110GR

RF OUTPUT POWER vs I/Q INPUT SIGNAL

A

= –40 ˚C)

(at T

0

VCC = 3.0 V V

CC

= 2.7 V

CC

= 3.6 V

V

Single ended

–5

–10

–15

- RF Output Power - dBm

RFout

P

–20

–25

100 200 300 400 500

RF OUTPUT POWER vs I/Q INPUT SIGNAL

A

= +25 ˚C)

(at T

0

VCC = 3.0 V V

CC

= 2.7 V

CC

= 3.6 V

V

Single ended

–5

–10

–15

- RF Output Power - dBm

RFout

P

–20

–25

100 200 300 400 500

P

I/Qin

- I/Q Input Signal - mVp-p

RF OUTPUT POWER vs I/Q INPUT SIGNAL

A

= +85 ˚C)

(at T

0

VCC = 3.0 V

CC

= 2.7 V

V

CC

= 3.6 V

V

Single ended

–5

–10

–15

- RF Output Power - dBm

RFout

P

–20

P

I/Qin

- I/Q Input Signal - mVp-p

–25

100 200 300 400 500

P

I/Qin

- I/Q Input Signal - mVp-p

Data Sheet P11074EJ3V0DS00

9