NEC UPC8105GR-E1, UPC8105GR Datasheet

DATA SHEET

BIPOLAR ANALOG INTEGRATED CI RCUIT

PC8105GR

µµµµ

400 MHz QUADRATURE MODULATOR

FOR DIGITAL MOBILE COMMUNICATION

DESCRIPTION

The µPC8105GR is a sillicon monolithic integrated circuit designed as quadrature modulator for digital mobile communication systems. This modulator housed in a 16 pin plastic SSOP that is easy to install and contributes to miniaturizing the system.

The device has power save function and can operates 2.7 to 5.5 V supply voltage to realize low power consumption.

FEATURES

•

Internal 90° phase shifter is accurate over an IF range from 100 MHz to 400 MHz.

•

Wide supply voltage range: VCC = 2.7 to 5.5 V.

•

Low operation current: ICC = 16 mA (typ.).

•

16 pin plastic SSOP suitable for high density surface mounting.

•

Low current in sleep mode

APPLICATION

•

IF modulator for Digital cellular phone (PDC, IS-54, GSM etc..)

•

IF modulator for Digital cordless phone (PHS, PCS etc..)

ORDERING INFORMATION

PART NUMBER PACKAGE SUPPLYING FORM

µ

PC8105GR-E1 16 pin plastic SSOP (225 m i l ) Carrier tape width 12 mm. Q’ty 2. 5 kp/Reel

Pin 1 indicated pull-out direc tion of tape.

To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:

PC8105GR)

µ

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. P10807EJ3V0DS00 (3rd edition) Date Published October 1999 N CP(K) Printed in Japan

Caution electro-static sensitive device

The mark shows major revised points.

©

1995, 1999

SERIES PRODUCTS

µµµµ

PC8105GR

SERIES TYPE

150 MHz Quadrature MOD

Up-Con + Quadrature MOD 400 MHz Quadrature MOD

Remark:

As for detail information of series products, please refer to each data sheet.

PART NUMBER

PC8101GR 100 to

µ

PC8104GR 100 to 400 DC to 10 800 to 1900 Digital Comm.

µ

PC8105GR 100 to 400 DC to 10 External Digital Comm.

µ

f LO1 in

(MHz)

300

f MODout

(MHz)

50 to 150 DC to 0.5 External CT2, Digital Comm.

f I/Q

(MHz)

INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)

LO

GND

I-INPUT

Q-INPUT

1

in

90˚

in

2

3

4

5

6

Phase Sifter

REG.

V

16

CC

15

Power Save

14

GND

13

GND

12

MOD

11

N.C.

Up-Converter f RFout (MHz)

out

APPLICATIONS

Q-INPUT

GND

APPLICATION EXAMPLE

[Digital cellular hand-held phone]

Low-noise transistor

RX

SW

TX

PA

10

7

8

÷N

VCO

PLL

µ

Phase shifter

µ

PC8106T

N.C.

9

N.C.

PC8105GR

0˚

90˚

DEMO

PLL

I

Q

I

Q

2

Data Sheet P10807EJ3V0DS00

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT TEST CONDITIONS

µµµµ

PC8105GR

Supply Voltage V Power Save Voltage V Power Dissipation P Operating Temperature T Storage Temperature T

: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board

*1

CC

PS

D

op

stg

6.0 V TA = +25 °C

310 mW

40 to +85

−

55 to +150

−

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS Supply Voltage V Operating Temperature T Modulator Output Frequency f LO1 Input Frequency f I/Q Input Frequency f

ELECTRICAL CHARACTERISTICS (TA = +25

CC

A

MODout

LO1in

I/Qin

2.7 3.0 5.5 V 40 +25 +85

−

100 400 MHz

DC 10 MHz P

C, VCC = 3.0 V, Unless Otherwise Specified VPS

°°°°

A

T

= +85 °C

C

°

C

°

C

°

LOin

P

= −10 dBm

I/Qin

= 600 mV

*1

p-p

MAX (Single ended)

1.8 V)

≥≥≥≥

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS Circuit Current I Circuit Current at Power

CC

10 16 21 m A No input signal

ICC(PS) 0.1 5

AVPS ≤ 1.0 V

µ

Save Mode Output Power P LO Carrier Leak LOL Image Rejection

MODout

ImR

−

21.0

−

16.5 40

−

40

−

12.0 dBm

−

30 dBc

−

30 dBc

−

I/Q DC = 1.5 V

I/Qin

= 500 mV

P

(Side Band Leak)

p-p

(Single ended)

Data Sheet P10807EJ3V0DS00

3

STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25

C, VCC = 3.0 V, Unless Otherwise Specified VPS

°°°°

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS

1.8 V)

≥≥≥≥

µµµµ

PC8105GR

I/Q 3rd Order

IM

Intermodulation Distort i on I/Q Input Impedance Z I/Q Bias Current I LO1 Input VSWR Z Power Save Rise Time T Power Save Fall Time T

3I/Q

I/Q

LO

PS(RISE)

PS(FALL)

50

−

30 dBc I/Q DC = 1.5 V

−

20 k

5

1.2:1 25 25

Ω

A

µ

I/Qin

= 500 mV

P I/Q DC = 1.5 V

I/Qin

= 500 mV

P (I → I, Q → Q)

p-p

−

sVPS(OFF) → VPS(ON)

µ

sVPS(ON) → VPS(OFF)

µ

(Single ended)

4

Data Sheet P10807EJ3V0DS00

PIN EXPLANATION

µµµµ

PC8105GR

PIN NO.

ASSIGNMENT

1LOin

2LOin

SUPPLY VOL. (V)

−

3GND0

8

4IV

CC

PIN VOL.(V)

FUNCTION AND APPLICATION EQUIPMENT CIRCUIT

0 LO input for phase shifter.

This input impedance is 50 matched internally.

Ω

1

50 Ω

2.4 Bypass of LO input. This pin is grounded through

2

internal capacitor. Open in case of single ended.

−

Connect to the ground with minimum inductance. Track length should be kept as short as possible.

/2

Input for I signal. This in put

−

impedance is larger than 20 kΩ. Relations between amplitude and

CC

/2 bias of input signal are

V following.

VCC/2 (v) Amp. (mV

1.35 400

≥

1.5 600

≥

1.75 1000

≥

p-p

)

*1

4 5

5IV

6QV

7QV

12 MODout

CC

/2

CC

/2

CC

/2

−

Input for I signal. This in put

−

impedance is larger than 20 kΩ.

CC

/2 biased DC signal should be

V input.

Input for Q signal. This i n put

−

impedance is larger than 20 kΩ.

CC

/2 biased DC signal should be

V input.

Input for Q signal. This i n put

−

impedance is larger than 20 kΩ. Relations between amplitude and

CC

/2 bias of input signal are

V following.

VCC/2 (v) Amp. (mV

1.35 400

≥

1.5 600

≥

1.75 1000

≥

1.5 Output from modulator. This is emitter follower output.

7 6

p-p

)

*1

12

In case of that I/Q input signals are single ended.

*1:

Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.

Data Sheet P10807EJ3V0DS00

5