NL6448BC33-31 is a TFT (thin film transistor) active matrix color liquid crystal display (LCD) comprising
amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. NL6448BC33-31 has a
built-in backlight. Backlight includes long-life-lamps and the lamps are replaceable.
The 26 cm (10.4 inches) diagonal display area contains 640 × 480 pixels and can display 262,144 colors
simultaneously.
NL6448BC33-31 is suitable for industrial application use because of the wide viewing angle and the high
luminance. Also, the viewing direction is selectable either upper or lower side by changing scan direction.
NL6448BC33-31 interface is compatible with NL6448AC33-18, -18A, -18B and -27.
FEATURES
• Wide viewing angle (with Retardation Film)
• Smooth polarizer surface (No antiglare treatment)
• High luminance (350 cd/m2, typ.: saturated value, at
room temp.)
• Low reflection
• 6-bit digital RGB signals
• Data enable function
• Backlight with two long-life-time lamps (one lamp
holder, inverter-less)
• Lamp holder replaceable (Type No.: 104LHS31)
• Reversible scan direction (with DPS pin)
• Replaceable lamp holders (Type No.: 104LHS31)
• Recommended inverter (Part No.: 104PWRI)
• Best viewing angle select function (with MVA terminal)
• Luminance control
• Easy to attach a touch panel
APPLICATIONS
• Display terminals for control system
• Monitors for process controller
• Industrial PCs
The information in this document is subject to change without notice.
Document No. EN0443EJ1V0DS00 (1st edition)
Date Published July 1999 P
Printed in Japan
A color TFT (thin film transistor) LCD module is comprised of a TFT liquid crystal panel structure, LSIs for driving
the TFT array, and a backlight assembly. The TFT panel structure is created by sandwiching liquid crystal material
in the narrow gap between a TFT array glass substrate and a color filter glass substrate. After the driver LSIs are
connected to the panel, the backlight assembly is attached to the backside of the panel.
RGB (red, green, blue) data signals from a source system is modulated into a form suitable for active matrix
addressing by the onboard signal processor and sent to the driver LSIs which in turn addresses the individual TFT
cells.
Acting as an electro-optical switch, each TFT cell regulates light transmission from the backlight assembly when
activated by the data source. By regulating the amount of light passing through the array of red, green, and blue
dots, color images are created with clarity.
Viewing angle (more than the contrast ratio of 10 : 1)
Horizontal : 50° (typ., left side, right side)
Vertical: 40° (typ., up side), 45° (typ, down side)
Designed viewing directionWider viewing angle without image reversal: up side (12 o’clock normal scan)
down side (6 o’clock reverse scan)
Wider viewing angle with contrast ratio: down side (6 o’clock normal scan)
up side (12 o’clo ck re vers e scan )
Optimum grayscale (
Polarizer pencil-hardness 2H (Min., at JIS K5400)
Color gamut43% (typ. at center, to NTSC)
Response time15 ms (typ.), white to black
Luminance350 cd/m
Signal system6-bit digital signals for each of RGB primary colors, synchronous signals
(Hsync, Vsync), dot clock (CLK)
Supply voltages3.3 V [5.0 V] (Logic, LCD driving), 12.0 V (Backlight)
BacklightEdge light type, two cold cathode fluorescent lamps (cold cathode type)
[Replaceable parts]
Lamp holder: type No.104LHS31
Power consumption6.8 W (typ., at 3.3 V, 12.0 V)
If Ft is out of the recommended value, interference between Ft frequency and Hsync frequency may cause
beat on the display.
SUPPLY VOLTAGE SEQUENCE
Signals
Backlight
V
Notes 1, 2, 3
Note 4
3.0 V (4.75 V)
CC
0 V
0 V
0 < t < 35 ms0 < t < 35 ms
ONOFF
thn: Hsync period
: a natural number (1, 2, 3, ····)
3.0 V (4.75 V)
VALID
2tV < t
0 < t
Time
otes 1.
Signals: CLK, Hsync, Vsync, DE,
DATA (R0-R5, G0-G5, B0-B5)
The supply voltage for input signals
2.
CC
should be the same as V
Apply VDDB within the LCD operation
3.
.
period. When the backlight turns on
before LCD operation or the LCD
operation turns off before the backlight
turns off, the display may momentarily
become white.
While the power is off, please keep
4.
whole signals at low level or high
impedance.
6
Data Sheet EN0443EJ1V0DS00
NL6448BC33-31
INTERFACE PIN CONNECTIONS
(1) Interface signals, power supply
Module side connectorMating connector
CN1 ··· DF9C-31P-1V (No.1 to 30) DF9-31S-1V or DF9M-31S-1R ...... (1)
IL-310-T31S-VF...... (2)
Supplier: (1) HIROSE ELECTRIC CO., LTD., (2) Japan Aviation Electronics Industry Limited (JAE)
Pin No.SymbolsFunctionsPin No.SymbolsFunctions
1GNDGround19GNDGround
2CLKDot clock20B0Blue data (LSB)
3HsyncHorizontal sync.21B1Blue data
4VsyncVertical sync.22B2Blue data
5GNDGround23B3Blue data
6R0Red data (LSB)24B4Blue data
7R1Red data25B5Blue data (MSB)
8R2Red data26GNDGround
9R3Red data27DEData enable
10R4Red data28V
11R5Red data (MSB)29V
12GNDGround30MVABest Viewing Select
13G0Green data (LSB)31DPSScan direction select
CC
CC
Power supply
Power supply
14G1Green data
15G2Green data
16G3Green data
17G4Green data
18G5Green data (MSB)
CC
: All VCC terminals should be connected to 3.3V or 5.0 V.
Notes 1.
V
GND is connected to the frame of the LCD module.
2.
DE: DE/Fixed mode select is as follows.
3.
Data enable signal = DE mode
CC
or Open = Fixed mode
V
MVA: MVA changes best viewing angle at gray scale screen.
4.
CC
or Open = Perpendiculer (best viewing angle: 0°)
V
GND = down side (best viewing angle: −10°)
DPS: DPS changes display scan direction.
5.
GND or Open = Scan direction will be decided by the setting of SW1.
CC
= Reverse scan
V
DISPLAY POSITION about another way for reversible scan.
CC
When DPS is V
, reverse scan is selected even if SW1 is set at normal scan.
LSB : Least Significant Bit
MSB : Most Significant Bit
Data Sheet EN0443EJ1V0DS00
7
(2) Backlight
• Lamp side connectorMating connector
CN2 ··· BHR-03VS-1SM03 (4.0)B-BHS-TB
Supplier: J.S.T TRADING COMPANY, LTD.
Pin No.SymbolsFunc tions
NL6448BC33-31
1V
2V
3V
L
H
H
(3) Connector locations
<Connector locations>
CN2
NEC
Recommended
inverter
CN1
CN3
Power supply (low)
Power supply (high)
Power supply (high)
1
2
1
2
3
Upper side
LCD Module
<Rear view>
Lower side
CN1
1
3
•
•
•
•
•
1
2
3
31
<Pin arrangement of CN1>
2
4
•
•
•
•
•
30
3
<Pin arrangement of CN3>
<Pin arrangement of CN2>
Incase of connecting NEC recommended inverter
8
4
5
<Pin arrangement of CN1>
Data Sheet EN0443EJ1V0DS00
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