NEC NL3224AC35-13, NL3224AC35-01 Datasheet

DATA SHEET

TFT COLOR LCD MODULE

NL3224AC35-01, 13

14 cm (5.5 inches), 320 × 240 Pixels, Full color

NTSC/PAL mode, Wide temperature range

DESCRIPTION

NL3224AC35-01 and NL3224AC35-13 are TFT (thin film transistor) active matrix color liquid crystal displays (LCD)
comprising amorphous silicon TFT attached to each signal electrode, a driving circuit and a backlight. Both the
products have a built-in backlight.

Their 14 cm diagonal display area contain 320 × 240 pixels and can display full-color simultaneously.

The difference between NL3224AC35-01 and NL3224AC35-13 is as follows:

• NL3224AC35-01: Antiglare polarizer surface

• NL3224AC35-13: Smoth polarizer surface

FEATURES

• High luminance

• NTSC/PAL mode

• Reversible horizontal and vertical scanning

• 234/240 line display

• Wide temparature range

• Analog RGB interface

• Incorporated edge type backlight

APPLICATIONS

• Car navigations

• TV monitors

• Video games

• Monitors for process controller

Document No. EN0495EJ1V1DS00
Date Published April 2000 P
Printed in Japan

The information in this document is subject to change without notice.
Please confirm with the delivery specification before statting to design the system.

2000

NL3224AC35-01, 13

STRUCTURE AND FUNCTIONS

A TFT color LCD module comprised a TFT LCD panel, LSIs for driving liquid crystal, and a backlight. The
TFT LCD panel is composed of a TFT array glass substrate superimposed on a color filter glass substrate with
liquid crystal filled in the narrow gap between two substrates. The backlight apparatus is located on the backside
of the LCD panel.

RGB (Red, Green, Blue) data signals are sent to LCD panel drivers after modulation into suitable forms for
active matrix addressing through signal processor.

Each of the liquid crystal cells acts as an electro-optical switch that controls the light transmission from the
backlight by a signal applied to a signal electrode through the TFT switch.

OUTLINE OF CHARACTERISTICS (at room temperature)

Items Description

Display area 111.36 (H) × 83.52 (V) mm

Drive system a-Si TFT active matrix

Display colors Full-color

Number of pixels 320 × 240

Pixel arrangement RGB vertical stripe

Pixel pitch 0.348 (H) × 0.348 (V) mm

Module size 134.0 (H) × 110.0 (V) × 23.0 max. (D) mm

Weight 315 g (typ.)

Contrast ratio 85:1 (typ.)

Viewing angle

(more than the contrast

ratio of 10:1)

Designed viewing direction • wider viewing angle with contrast ratio : up side (12 o’clock)

Color gamut 50 % (typ. center, to NTSC)

Response time 16 ms (typ.), “white” to “black”

Luminance 250 cd/m2 (typ.)

Signal system Analog RGB signals, synchronous signals (CLK, HS, VS)

Backlight Edge light type, one fluorescent lamp (cold cathode type)

Supply voltage 9.5 V (LCD power supply), 9.5 V (Backlight power supply)

Power consumption 6.6 W (typ.)

• Horizontal: 45° (typ. left side, right side)

• Vertical: 30° (typ. up side), 15° (typ. down side)

• wider viewing angle without image reversal : down side (6 o’clock)

• optimum grayscale (γ = 2.2) : perpendicular

Back-Light Unit. (Parts No.: 55LHS-1)

2

Data Sheet EN0495EJ1V1DS00

BLOCK DIAGRAM OF BASIC STRUCTURE

Video circuit board

NL3224AC35-01, 13

Analog RGB

HS
VS

234/240 select
Reversible select

• horizontal

• vertical
NTSC/PAL select

DC
clamp

Analog
SW

Gamma
correction
AMP

MUTE
Video
select

DC
shift

Clamp pulse

COM

signal

H-Driver

V-Driver

Panel

+

Controller

Luminance control

V

V

DCB

GNDA
GNDD

DC

DC/DC
converter

IC

S

Drivers

Note 1. Frame is contacted with both GNDA and GNDD

Inverter backlight

Data Sheet EN0495EJ1V1DS00

3

NL3224AC35-01, 13

GENERAL SPECIFICATIONS

Items Description Unit
Module size 134.0 ± 0.5 (H) × 110.0 ± 0.5 (V) × 23.0 max. (D) mm
Display area 111.36 (H) × 83.52 (V) mm
Number of dots 320 × 3 (H) × 240 (V) dot
Dot pitch 0.116 (H) × 0.348 (V) mm
Pixel pitch 0.348 (H) × 0.348 (V) mm
Pixel arrangement RGB (Red, Green, Blue) vertical stripe –
Display colors Full-color color
Weight 330 (max.) g

Note An inverter is incorporated with the module.

ABSOLUTE MAXIMUM RATINGS

Parameters Symbols Ratings Unit Remarks

Supply voltage VDC –0.5 to 20.0 V Ta = 25˚C

VDCB –0.5 to 20.0 V

Analog RGB VIN1 –2.5 to 2.5 V Ta = 25˚C
input signal VDC = 9.5 V

Logic input voltage VIN2 –0.5 to 5.5 V
Storage temp. TST –40 to 95 ˚C –
Operating temp. TOP –30 to 85 ˚C Note 1
Relative humidity (RH)

Absolute humidity Absolute humidity shall not g/m

exceed Ta = 50˚C, RH = 85%

<

95 % Ta

=
<

85 % 40 < Ta

=

3

<

40˚C no

=

<

50˚C

=

Ta > 50˚C

condensation

Note 1. Module surface: measured at the display center.

4

Data Sheet EN0495EJ1V1DS00

NL3224AC35-01, 13

ELECTRICAL CHARACTERISTICS

(1) Power supply, logic input

Parameters Symbol Min. Typ. Max. Unit Remarks

Supply voltage VDC 8.0 9.5 13.0 V For processor,

controller and driver

VDCB 8.0 9.5 13.0 V For backlight
Logic input “L” voltage VIL 0 – 0.9 V –
Logic input “H” voltage VIH 3.15 – 5.0 V
Logic output “L” voltage VOL 0 – 0.3 V
Logic output “H” voltage VOH 4.5 – 5.0 V
Supply current IDC – 147 200 mA At dot-checkered pattern

(VDC = 9.5 V)

IDCB – 541 600 mA Maximum luminance

(VDCB = 9.5 V)

Ta = 25˚C

(2) Analog RGB signals

Ta = 25˚C

Parameters Min. Typ. Max. Unit Remarks
Analog RGB input voltage (white - black) 0 – 0.7 Vp-p Zi = 75 Ω
DC input level (black level) –1.0 – 1.0 V

SUPPLY VOLTAGE SEQUENCE

Note1

V

DCB

Note2

Note3

V

DC

0 < < 30 ms time

0 < < 200 ms

Note4

0 < < 30 ms

0 < < 200 ms

Logic signals

Note4

Notes1. Apply VDCB within the LCD operation period. When the backlight turns on before LCD operation or the

LCD operation turns off before the backlight turns off, the display may momentarily become white.

2. When the VDC is off, please keep whole logic signals at “0 V.” In case of the signal more than “0.3 V,”
internal circuit may get damaged.

3. Please turn off V

DC when the signals are put off. If the signals are put off without keep VDC, the display

may be un-uniformity.

4. Reference value.

5. While the power is off, please keep whole signals (HS, VS, EXTCLK) at low level or high impedance.

6. Wrong power sequence may damage to the module.

Data Sheet EN0495EJ1V1DS00

5

INTERFACE PIN CONFIGURATION
(1) Connector (CN1)

Part no. : 52610-3090
Supplier : Molex
Adaptable cable : SUMI-CARD 1.0 mm pitch 30 wick 85°C quality
Supplier : SUMITOMO ELECTRIC INDUSTRIES, LTD.

Pin No. Symbol Pin No. Symbol Pin No. Symbol

1 GNDD 11 EXTCSL 21 GNDD
2 EXTCLK 12 GNDD 22 GNDD
3 GNDD 13 N/P 23 GNDD
4 HS 14 MTSL 24 GNDA
5 VS 15 U/D 25 R
6HOUT 16 R/L 26 GNDA
7VOUT 17 GNDD 27 G
8BPLS 18 VDCB 28 GNDA

9 GNDD 19 VDCB 29 B

10 GNDD 20 VDC 30 GNDA

NL3224AC35-01, 13

<Connector location>

CN1

30

1

Upper side

<Rear view>

Lower side

6

Data Sheet EN0495EJ1V1DS00

NL3224AC35-01, 13

PIN DESCRIPTION

Symbols In/Out Logics Description

EXTCLK In Note 1 – External clock

EXTCLK becomes active, when EXTCSL is “H“

EXTCSL In Note 1 Positive Clock select signal H: External clock

Default value is L L: Internal clock
HS In Note 1 Negative Horizontal synchronous signal
VS In Note 1 Negative Vertical synchronous signal
HOUT Out Note 1 Negative Horizontal synchronous signal output
VOUT Out Note 1 Negative Vertical synchronous signal output
R In – Analog Red signal 0.7 Vp-p Zi = 75 Ω
G In – Analog Green signal 0.7 Vp-p Zi = 75 Ω
B In – Analog Blue signal 0.7 Vp-p Zi = 75 Ω

R/L In Note 1 – Horizontal scanning select signal H: Right scanning

Default value is L L: Left scanning
U/D In Note 1 – Vertical scanning select signal H: down scanning

Default value is L L: up scanning
N/P In Note 1 – Display mode select H: PAL mode

Default value is L L: NTSC mode
MTSL In Note 1 – Vertical display area select signal H: 240 lines

Default value is L L: 234 lines
BPLS In Note 1 – Luminance control signal (pulse input)

Luminance is controlled by the pulse width.

Duty 100%: luminance Max. Refer to P17 (note 8).
VDC In – Power supply for processor, controller and driver (+9.5 V)
VDCB In – Power supply for backlight (+9.5 V)
GNDA – Note 2 – Ground for analog RGB signal
GNDD – Note 2 – Ground for logic (V DC) and backlight (VDCB)

Notes 1. CMOS level

2. GNDA should be separated from GNDD to aboid display noise.

Data Sheet EN0495EJ1V1DS00

7

SIGNALS

No. Functions Description

1 Reversible horizontal scanning R/L signal is able to reverse scanning direction.

(Right → Left or Left → Right)

2 Reversible vertical scanning U/D signal is able to reverse scanning direction.

(Up → Down or Down → Up)

3 NTSC/PAL mode N/P signal is able to change operating mode.

(NTSC → PAL or PAL → NTSC)
Scanning line is thinned out at the rate of seven to six lines in the PAL mode.

4 234/240 line display MTSL signal is able to change scanning line.

(234 lines → 240 lines or 240 lines → 234 lines)

NL3224AC35-01, 13

8

Data Sheet EN0495EJ1V1DS00

NL3224AC35-01, 13

INPUT SIGNAL TIMING

(1) mode
(a) NTSC, internal CLK

Parameters Symbols Min. Typ. Max. Unit Remarks

Internal-CLK Frequency 1/tc – 6.36 – MHz –

– 157.32 – ns
Rise/fall tcrf – – 70 ns –
Duty tch/tc 0.4 0.5 0.6 – –

HS Frequency th 60.38 63.56 66.74

– 404 – CLK (typ.)
Display thd – 50.34 –

– 320 – CLK
Pulse-width thp 1.0 4.7 –

– 30 – CLK
Pulse-width thpb – 11.01 –

+back-porch – 70 – CLK

– 12.11 –

– 77 – CLK
CLK-Hsync timing thch 10.0 – – ns –

hold/setup time

V-Hsync timing thvh 1 – – CLK –
hold/setup time

Rise/fall thrf – – 10.0 ns –

VS Frequency tv 15.85 16.68 17.51 ms 59.94 Hz

Display tvd – 14.87 – ms 234 line

Pulse-width tvp 158.89 190.67 –

Pulse-width tvpb – 1.33 – ms –
+back-porch – 21 – H

Rise/fall tvrf – – 10.0 ns –

thcs 10.0 – – ns –

thvs 10.0 – – ns –

– 262.5 – H (typ.)

– 234 – H

– 15.25 – ms 240 line

– 240 – H

–3–H

µ

s 15.734 kHz

µ

s–

µ

s–

µ

s 234 line

µ

s 240 line

µ

s–

Note In the display start period (pulse-width + back-porch), analog RGB signals should be blanking level.

Data Sheet EN0495EJ1V1DS00

9