NEC NL204153BM21-05 Specification
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TFT MONOCHROME LCD MODULE
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NL204153BM21-05
54cm (21.3 Type)
QXGA
PRELIMINARY DATA SHEET
DOD-PD-0418 (6th edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PD-0246(5).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-0418 (6th edition)
Published date: March 2004 CP(N)
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ã NEC LCD Technologies, Ltd.
2003, 2004 All rights reserved.
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No part of this document shall be copied in any form or by any means without the prior written consent
of NEC LCD Technologies, Ltd. (hereinafter called "NEC").
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a product described herein or any other liability arising
from use of such application. No license, express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC or of others.
While NEC has been making continuous effort to enhance the reliability of its products, the possibility
of failures cannot be eliminated entirely. To minimize risks of damage to property or injury to person
arising from a failure in an NEC product, customers must incorporate sufficient safety measures in their
design, such as redundancy, fire-containment and anti-failure features.
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NL204153BM21-05
INTRODUCTION
NEC products are classified into the following three quality grades:
"Standard", "Special", "Specific"
The "Specific" quality grade applies only to applications developed based on a customer designated
"quality assurance program" for a specific application. The recommended applications of a product
depend on its quality grade, as indicated below. Customers must check the quality grade of each
application before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically
designed for life support)
Specific: Military systems, aircraft, aerospace equipment, submersible repeaters, nuclear reactor control
systems, life support systems (medical equipment, etc.) and any other equipment
The quality grade of this product is "Standard" unless otherwise specified in this document. If
customers intend to use this product for applications other than those specified for "Standard" quality
grade, they should contact NEC sales representative in advance.
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INTRODUCTION.......................................................................................................................................... 2
1. OUTLINE ................................................................................................................................................... 4
1.1 STRUCTURE AND PRINCIPLE.......................................................................................................... 4
1.2 APPLICATION ...................................................................................................................................... 4
1.3 FEATURES............................................................................................................................................ 4
2. GENERAL SPECIFICATIONS................................................................................................................ 5
3. BLOCK DIAGRAM .................................................................................................................................. 6
4. DETAILED SPECIFICATIONS............................................................................................................... 7
4.1 MECHANICAL SPECIFICATIONS ..................................................................................................... 7
4.2 ABSOLUTE MAXIMUM RATINGS....................................................................................................7
4.3 ELECTRICAL CHARACTERISTICS ..................................................................................................8
4.3.1 LCD panel signal processing board .............................................................................................. 8
4.3.2 Backlight lamp .............................................................................................................................. 9
4.3.4 Power supply voltage ripple........................................................................................................ 10
4.3.5 Fuse ............................................................................................................................................. 10
4.4 POWER SUPPLY VOLTAGE SEQUENCE.........................................................................................11
4.5 CONNECTIONS AND FUNCTIONS FOR INTERFACE PINS........................................................ 12
4.5.1 LCD panel signal processing board ............................................................................................ 12
4.5.2 Backlight lamp ............................................................................................................................ 14
4.5.3 Positions of plugs and sockets..................................................................................................... 15
4.6 METHOD OF CONNECTION FOR LVDS TRANSMITTER ........................................................... 16
4.7 TEN-bit LOOK UP TABLE FOR GAMMA ADJUSTMENT ............................................................. 18
4.8 LUT SERIAL COMMUCATION TIMINGS....................................................................................... 21
4.9 DISPLAY GRAY SCALE AND INPUT DATA SIGNALS ................................................................. 23
4.10 DISPLAY POSITIONS ...................................................................................................................... 24
4.11 PIXEL ARRANGNMENT................................................................................................................. 24
4.12 LVDS DATA TARANSMISSION METHOD.................................................................................... 25
4.13 INPUT SIGNAL TIMINGS............................................................................................................... 26
4.13.1 Timing characteristics ............................................................................................................... 26
4.13.2 Input signals timing chart.......................................................................................................... 26
4.14 OPTICS.............................................................................................................................................. 27
4.14.1 Optical characteristics ............................................................................................................... 27
4.14.2 Definition of contrast ratio ........................................................................................................ 28
4.14.3 Definition of luminance uniformity........................................................................................... 28
4.14.4 Definition of response times...................................................................................................... 28
4.14.5 Definition of viewing angles..................................................................................................... 28
5. RELIABILITY TESTS............................................................................................................................ 29
6. PRECAUTIONS....................................................................................................................................... 30
6.1 MEANING OF CAUTION SIGNS ..................................................................................................... 30
6.2 CAUTIONS ......................................................................................................................................... 30
6.3 ATTENTIONS...................................................................................................................................... 30
6.3.1 Handling of the product............................................................................................................... 30
6.3.2 Environment................................................................................................................................ 31
6.3.3 Characteristics ............................................................................................................................. 31
6.3.4 Other............................................................................................................................................ 31
7. OUTLINE DRAWINGS .......................................................................................................................... 32
7.1 FRONT VIEW ..................................................................................................................................... 32
7.2 REAR VIEW........................................................................................................................................ 33
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NL204153BM21-05
CONTENTS
REVISION HISTORY................................................................................................................................. 34
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1. OUTLINE
1.1 STRUCTURE AND PRINCIPLE
Monochrome LCD module NL204153BM21-01 is composed of the amorphous silicon thin film
transistor liquid crystal display (a-Si TFT LCD) panel structure with driver LSIs for driving the TFT
(Thin Film Transistor) array and a backlight.
The a-Si TFT LCD panel structure is injected liquid crystal material into a narrow gap between the TFT
array glass substrate and a monochrome-filter glass substrate.
Grayscale data signals from a host system (e.g. PC, signal generator, etc.) are modulated into best form
for active matrix system by a signal processing board, and sent to the driver LSIs which drive the
individual TFT arrays.
The TFT array as an electro-optical switch regulates the amount of transmitted light from the backlight
assembly, when it is controlled by data signals. Monochrome images are created by regulating the
amount of transmitted light through the TFT array.
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NL204153BM21-05
1.2 APPLICATION
• Monochrome monitor system
1.3 FEATURES
• Ultra-wide viewing angle (with lateral electric field)
• High luminance
• High contrast
• Low reflection
• High resolution
• 256 gray scale per 1 dot (8-bit)
• 4 ports LVDS interface
• Adjustable gamma characteristics by using built-in 10-bit LUT (look up table)
• Selectable LVDS data input map
• Small foot print
• Incorporated edge light type backlight (without inverter)
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2. GENERAL SPECIFICATIONS
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NL204153BM21-05
Display area
Diagonal size of display
Drive system
Display grayscale
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
433.152 (H) × 324.864 (V) mm (typ.)
54 cm (21.3 inches)
a-Si TFT active matrix
256 gray scale per 1 dot (8-bit)
(1 pixel consists of 3 dots (766 gray scale).)
2,048 (H) × 1,536 (V) pixels
Sub-pixel vertical stripe
0.0705 (H) × 0.2115 (V) mm
0.2115 (H) × 0.2115 (V) mm
457.0 (W) × 350.0 (H) × 25.0 (D) mm (typ.)
3,800 g (typ.)
700:1 (typ.)
≥
At the contrast ratio
10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ=DICOM): normal axis
Antiglare
6
6
Polarizer pencil-hardness
Response time
Luminance
Signal system
Power supply voltage
Backlight
Power consumption
2H (min.) [by JIS K5400]
←→
Ton+Toff (10%
90%)
(35) ms (typ.)
At IBL= 6.0mArms / lamp
2
800 cd/m
(typ.)
4 ports LVDS interface (THC63LVD824×2 pcs, THine Electronics, Inc.
or equivalent)
LCR 8-bit signals, Data enable signal (DE), Dot clock (CLK)
LCD panel signal processing board: 12.0V
Edge light type: 6 cold cathode fluorescent lamps (without inverter)
At checkered flag pattern and IBL= 6.0mArms / lamp
34.2 W (typ.)
6
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–
t
N
N
N
3. BLOCK DIAGRAM
I/F LCD module (Product)
DA0+/–
DA1+/–
DA2+/–
CKA+/–
DA3+/–
DB0+/–
DB1+/–
DB2+/–
CKB+/–
DB3+/–
DC0+/
DC1+/–
DC2+/–
CKC+/–
DC3+/–
Equivalent of
THC63LVD824 (THine)
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Controller
V-d riv er
1536 lines
NL204153BM21-05
H-driver
6144 lines
TFT LCD panel
V-d riv er
DD0+/–
DD1+/–
DD2+/–
CKD+/–
DD3+/–
SCLK
SDAT
BSEL0
BSEL1
VDD
GND
ote1, Note2
FG
ote1, Note2
VBLH
CS
Fuse
Equivalent of
THC63LVD824 (THine)
DC/DC
Converter
Power supply
for drivers
H: 2048 × 3 (L, C, R)
V: 1536
Lamp
Lamp
Lamp
Backligh
(Edge light type)
VBLC
ote1
Note1: Connections between GND (Signal ground), FG (Frame ground) and VBLC (Lamp low voltage terminal)
in the LCD module
GND - FG Connected
GND - VBLC Not connected
FG - VBLC Not connected
Note2: GND and FG must be connected to customer equipment's ground, and it is recommended that GND,
FG and customer inverter ground are connected together in customer equipment.
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4. DETAILED SPECIFICATIONS
4.1 MECHANICAL SPECIFICATIONS
Parameter Specification Unit
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NL204153BM21-05
Module size
Display area
Weight 3,800 (typ.), 4,000 (max.) g
Note1: See "7. OUTLINE DRAWINGS".
4.2 ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit Remarks
Power supply
voltage
Operating temperature
LCD panel signal processing board VDD -0.3 to +14.0 V
Lamp voltage VBLH 2,000 Vrms
Input signal voltage
Note1
Storage temperature Tst -20 to +60
Front surface TopF 0 to +55
Rear surface TopR 0 to + (60)
457.0 ± 0.5 (W) × 350.0 ± 0.5 (H) ×
433.152 (W) × 324.864 (H)
Vi -0.3 to +2.8 V
25.0±0.5
(D)
Note1 mm
Note1 mm
°C
°C
°C
Ta = 2 5°C
6
Ta = 2 5°C
VDD=12.0V
-
Note2
Note3
%
%
%
g/m
40 < Ta ≤ 50°C
50 < Ta ≤ 55°C
3
Ta ≤ 40°C
Ta > 5 5°C
Relative humidity
Note4
Absolute humidity
Note4
RH
AH
≤ 95
≤ 85
≤ 70
≤ 73
Note5
Note1:DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-, DC0+/-,
DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/-,
CS, SCLK, SDAT, BSEL0, BSEL1
Note2: Measured at center of LCD panel surface (including self-heat)
Note3: Measured at center of LCD module's rear shield surface (including self-heat)
Note4: No condensation
Note5:Ta = 55°C, RH = 70%
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4.3 ELECTRICAL CHARACTERISTICS
4.3.1 LCD panel signal processing board
Parameter Symbol min. typ. max. Unit Remarks
Supply voltage VDD 10.8 12.0 13.2 V -
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NL204153BM21-05
(Ta = 25°C)
Supply current IDD -
Ripple voltage VRP - - 100 mVp-p for VDD
Differential input threshold
voltage
Input voltage swing VI 0 - 2.4 V -
Terminating resistance RT - 100 -
Control signal input
threshold voltage
Control signal input current Low IIL -10 - 10
High VTH - - +100 mV
Low VTL -100 - - mV
High VIH High must be Open. V
Low VIL 0 - 0.5 V
High V+ - 1.4 1.9 V
600
Note1
1,100
Note2
mA at VDD=12.0V
at VCM= 1.2V
Note3, Note4
Ω
μA
-
Note5
Serial communication
signal input threshold
Low V- 0.4 0.7 - V
Note6
voltage
Hysteresis VH 0.3 - - V
Note1: Checkered flag pattern (by EIAJ ED-2522)
Note2: Pattern for maximum current
Note3: Common mode voltage for LVDS driver
Note4: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-,
DC0+/-, DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/Note5: BSEL0, BSEL1
Note6: CS, SCLK, SDAT
6
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4.3.2 Backlight lamp
Parameter Symbol min. typ. max. Unit Remarks
Lamp current IBL 3.0 6.0 7.0 mArms
Lamp voltage VBLH - 750 - Vrms Note2, Note3
Lamp starting voltage VS
Lamp oscillation frequency FO 50 58 60 kHz Note4
Note1: This product consists of 6 backlight lamps, and these specifications are for each lamp.
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1,220 - - Vrms
1,460 - - Vrms
NL204153BM21-05
Note1)
25°C,
(Ta=
At IBL= 6.0mArms:
800 cd/m
Ta = 2 5°C
Note2, Note3
Ta = 0 °C
Note2, Note3
2
Note3
6
Note2: The lamp voltage cycle between lamps should be kept on a same phase. "VS" and "VBLH"
are the voltage value between low voltage side (Cold) and high voltage side (Hot).
Note3: The asymmetric ratio of working waveform for lamps (Lamp voltage peak ratio, Lamp
current peak ratio and waveform space ratio) should be less than 5 % (See the following
figure.). If the waveform is asymmetric, DC (Direct current) element apply into the lamp. In
this case, a lamp lifetime may be shortened, because a distribution of a lamp enclosure
substance inclines toward one side between low voltage terminal (Cold terminal) and high
voltage terminal (Hot terminal).
Pa
Pb
0
Sa
Sb
⏐Pa - Pb⏐
Pb
⏐Sa - Sb⏐
Sb
× 100 ≤ 5 %
× 100 ≤ 5 %
Pa: Supply voltage/current peak for positive, Pb: Supply voltage/current peak for negative
Sa: Waveform space for positive part, Sb: Waveform space for negative part
Note4: In case "FO" is not the recommended value, beat noise may display on the screen, because
of interference between "FO" and "1/th". Recommended value of "FO" is as following.
FO
1
=
4
1
(2n-1)
×
×
th
th: Horizontal cycle period (See "4.13.1 Timing characteristics".)
n: Natural number (1, 2, 3 ⋅⋅⋅⋅⋅⋅⋅⋅)
Note5: Method of lamp cable installation may invite fluctuation of lamp current and voltage or
asymmetric of lamp working waveform. When designing method of lamp cable installation,
evaluate the fluctuation of lamp current, voltage and working waveform sufficiently.
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4.3.3 Power supply voltage ripple
This product works, even if the ripple voltage levels are beyond the permissible values as following
the table, but there might be noise on the display image.
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NL204153BM21-05
Note1: The permissible ripple voltage includes spike noise.
4.3.4 Fuse
Note1: The power supply capacity should be more than the fusing current. If the power
Parameter Power supply voltage
VDD 12.0 V
Parameter
VDD
Type Supplier
FCC16202AB
(Measure at input terminal of power supply)
Fuse
KAMYA ELECTRIC
Co., Ltd.
Ripple voltage Note1
≤ 100
Rating Fusing current Remarks
2.0 A
4.0 A
32 V
supply capacity is less than the fusing current, the fuse may not blow for a short
time, and then nasty smell, smoking and so on may occur.
Unit
mVp-p
Note1
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4.4 POWER SUPPLY VOLTAGE SEQUENCE
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NL204153BM21-05
VDD
ote1, Note2
0V
VDD ON
10.8V
9.6V
VDD dip < 20ms
5ms < Tr < 80ms
VDD OFF
10.8V
Toff > 200ms
LV D S Si gn a ls * 1, * 2
Note3
CS, SCLK, SDAT
Note3
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/-, CKB+/-,
DC0+/-, DC1+/-, DC2+/-, DC3+/-, CKC+/-, DD0+/-, DD1+/-, DD2+/-, DD3+/-, CKD+/-
*2: LVDS signals should be measured at the terminal of 100Ω resistor.
0V
10ms < t < 35ms
t≥20ms
VA L I D p er i od
Note4
VA L I D p er i od
0ms < t < 35ms
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a
protection circuit may work, and then this product may not work.
Note2: VDD should be 10.8V or more during VDD ON period.
Note3: LVDS signals and CS, SCLK, SDAT must be Low or High-impedance, exclude the
VALID period (See above sequence diagram), in order to avoid that internal circuits is
damaged.
If some of signals are cut while this product is working, even if the signal input to it once
again, it might not work normally. If customer stops the display and function signals,
they should be cut VDD.
Note4: At the beginning of the serial communication mode, take 20ms or more after the LVDS
signal input. When writing the LUT data, see “4.7 TEN-bit LOOK UP TABLE FOR
GAMMA ADJUSTMENT”.
Note5: The backlight inverter voltage should be inputted within the valid period of LVDS signals,
in order to avoid unstable data display.
10.8V
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