NEC NE321000 Datasheet

DATA SHEET

HETERO JUNCTION FIELDEFFECT TRANSISTOR

NE321000

C to Ka BAND SUPER LOW NOISE AMPLIFIER

N-CHANNEL HJ-FET CHIP

DESCRIPTION

The NE321000 is Hetero Junction FET that utilizes the hetero junction to create high mobility electrons. Its
excellent low noise and associated gain make it suitable for DBS and another commercial systems, industrial and
space applications.

FEATURES

• Super Low Noise Figure & High Associated Gain

NF = 0.35 dB TYP. Ga = 13.5 dB TYP. @ f = 12 GHz

• Gate Length: Lg ≤ 0.20 µm

• Gate Width : Wg = 160 µm

ORDERING INFORMATION (PLAN)

Part Number Quality Grade

NE321000 Standard (Grade D)

Remark

To order evaluation samples, please contact your local NEC sales office. (Part number for sample order:
NE321000)

ABSOLUTE MAXIMUM RATINGS (TA = +25°C)

Parameter Symbol Ratings Unit
Drain to Source Voltage V
Gate to Source Voltage V
Drain Current I
Gate Current I
Total Power Dissipat i on
Channel Temperature T
Storage Temperature T

DS

GS

D

G

Note

tot

P

ch

stg

4.0 V

–3.0 V

DSS

I
100
200 mW
175 °C

–65 to +175 °C

mA

µ

A

Chip mounted on an Alumina heatsink (size: 3 × 3 × 0.6 t)

Note

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. P14270EJ2V0DS00 (2nd edition)
Date Published November 1999 N CP(K)
Printed in Japan

The mark shows major revised points.

1999©

RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)

Parameter Symbol MIN. TYP. MAX. Unit

NE321000

Drain to Source Voltage V
Drain Current I
Input Power P

DS

D

in

123V
51015mA
––0dBm

ELECTRICAL CHARACTERISTICS (TA = +25 °C)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Gate to Source Leak Current I
Saturated Drain Current I
Gate to Source Cut Off Voltage V
Transconductance g
Noise Figure NF – 0.35 0.45 dB
NF Associated Gain G

Remark

RF performance is determined by packaging and testing 10 chips per wafer.
Wafer rejection criteria for standard devices is 2 rejects per 10 samples.

GSO

DSS

GS(off)

m

a

VGS = –3 V – 0.5 10
VDS = 2 V, VGS = 0 V 154070mA
VDS = 2 V, IDS = 100 µA –0.2 –0.7 –2.0 V
VDS = 2 V, IDS = 10 mA 40 55 – mS
VDS = 2 V, IDS = 10 mA

f = 12 GHz

12.0 13.5 – dB

µ

A

2

Data Sheet P14270EJ2V0DS00

TYPICAL CHARACTERISTICS (TA = +25 °C)

NE321000

TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE

250

200

(mW)

tot

150

100

50

Total Power Dissipation P

0 50 100 150 200 250

A

Ambient Temperature T

(°C)

DRAIN CURRENT vs.
GATE TO SOURCE VOLTAGE

VDS = 2 V

60

(mA)

D

40

DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE

100

80

(mA)

D

60

40

Drain Current I

20

0 2.01.0

Drain to Source Voltage V

MAXIMUM AVAILABLE GAIN, FORWARD
INSERTION GAIN vs. FREQUENCY

24

(dB)

2

|

21s

20

MSG.

16

VGS = 0 V

–0.2 V

–0.4 V
–0.6 V

DS

(V)

VDS = 2 V

D

= 10 mA

I

20

Drain Current I

0

–2.0 –1.0 0

GS

Gate to Source Voltage V

(V)

12

8

Maximum Stable Gain MSG. (dB)

Maximum Available Gain MAG. (dB)

Forward Insertion Gain |S

4

13024 206 8 10 14

2

|S

21S

|

Frequency f (GHz)

Data Sheet P14270EJ2V0DS00

3

GAIN CALCULATIONS

NE321000

S21
MSG. =
S

S21
MAG. =
S

1.0

Noise Figure NF (dB)

0.5

12

k ±

12

NOISE FIGURE, NF ASSOCIATED GAIN vs.
FREQUENCY

0

1302

k2 – 1 = S11·S22 – S21·S12

a

G

NF

4206 8 10 14

Frequency f (GHz)

1 + | |2 – |S11 |2 – |S22|
K =
2 |S

∆

12| |S21|

∆

24

VDS = 2 V

D

= 10 mA

I

20

(dB)

a

16

12

NF Associated Gain G

8

4

2

NOISE FIGURE, NF ASSOCIATED GAIN vs.
DRAIN CURRENT

VDS = 2 V
f = 12 GHz

2.0

1.5

Noise Figure NF (dB)

1.0

0.5

a

G

NF

Drain Current ID (mA)

15

14

(dB)

a

13

12

11

NF Associated Gain G

3020100

4

Data Sheet P14270EJ2V0DS00