NEC MuPD78F0132H, MuPD78F0138H, MuPD78F0136H, MuPD78F0134H, MuPD78F0138HD User Manual

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User’s Manual

78K0/KE1+

8-Bit Single-Chip Microcontrollers

PD78F0132H

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H

PD78F0138HD

Document No. U16899EJ2V0UD00 (2nd edition) Date Published April 2005 N CP(K)

Printed in Japan

2003

[MEMO]

User’s Manual U16899EJ2V0UD

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distor tion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

User’s Manual U16899EJ2V0UD

EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash



is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

Caution: This product uses SuperFlash

technology licensed from Silicon Storage Technology, Inc.

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The information in this document is current as of October, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

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NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative

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purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

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While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

User’s Manual U16899EJ2V0UD

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:

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Device availability

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Ordering information

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Product release schedule

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Availability of related technical literature

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Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

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Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

[GLOBAL SUPPORT] http://www.necel.com/en/support/support.html

NEC Electronics America, Inc. (U.S.)

Santa Clara, California Tel: 408-588-6000 800-366-9782

EC Electronics (Europe) GmbH

Duesseldorf, Germany Tel: 0211-65030

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Sucursal en España

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NEC Electronics Taiwan Ltd.

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NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore Tel: 6253-8311

J04.1

User’s Manual U16899EJ2V0UD

INTRODUCTION

Readers This manual is intended for user engineers who wish to un derstand the functions of the

78K0/KE1+ and design and develop application systems and programs for these devices.

The target products are as follows.

78K0/KE1+:

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The 78K0/KE1+ manual is separated into two parts: this manu al and the instructions

edition (common to the 78K/0 Series).

PD78F0132H, 78F0133H, 78F0134H, 78F0136H, 78F0138H,

78F0138HD

78K0/KE1+

User’s Manual

(This Manual)

78K/0 Series

User’s Manual

Instructions

• Pin functions

• Internal block functions

• Interrupts

• CPU functions

• Instruction set

• Explanation of each instruction

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• To gain a general understanding of functions: → Read this manual in the order of the CONTENTS. The mark

shows major

revised points.

• How to interpret the register format: → For a bit number encl osed in brackets, the b it name is d efined as a r eserv ed wor d

in the RA78K0, and is defined as an sfr variable by #pr agma sfr directive in the CC78K0.

• To check the details of a register when you know the register name: → Refer to APPENDIX C REGISTER INDEX.

• To know details of the 78K/0 Series instructions: → Refer to the separate document 78K/0 Series Instructions User’s Manual

(U12326E).

User’s Manual U16899EJ2V0UD

Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text. Caution: Information requiring particular attention Remark: Supplementary information Numerical representations: Binary Decimal Hexadecimal

...

×××× or ××××B

...

××××

...

××××H

Differences Between 78K0/KE1+ and 78K0/KE1

Series Name

Item Mask ROM version None Available Flash

memory version

Version with on-chip debug function Available (µPD78F0138HD) None Regulator None Available Power-on clear function 2.1 V ±0.1 V (fixed) 2.85 V ±0.15 V or 3.5 V ±0.2 V selectable Minimum instruction execution time 0.125 µs (at 16 MHz operation) 0.166 µs (at 12 MHz operation)

Power supply Single power supply Two power supplies Self-programming function Available None Option byte

Ring-OSC can be stopped/cannot be stopped selectable

78K0/KE1+ 78K0/KE1

None

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No. 78K0/KE1+ User’s Manual This manual 78K0/KE1 User’s Manual U16228E 78K/0 Series Instructions User’s Manual U12326E 78K0/Kx1+ Flash Memory Self Programming User’s Manual Under preparation

Documents Related to Development Tools (Software) (User’s Manuals)

Document Name Document No. RA78K0 Ver. 3.80 Assembler Package

ID78K0-QB Ver. 2.81 Integrated Debugger Operation U16996E PM plus Ver. 5.20 U16934E

Operation U17199E Language U17198E Structured Assembly Language U17197E Operation U17201E CC78K0 Ver. 3.70 C Compiler Language U17200E Operation U17246E SM+ System Simulator User Open Interface U17247E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

User’s Manual U16899EJ2V0UD

Documents Related to Development Tools (Hardware) (User’s Manuals)

Document Name Document No. QB-78K0KX1H In-Circuit Emulator U17081E QB-78K0MINI On-Chip Debug Emulator U17029E

Documents Related to Flash Memory Programming

Document Name Document No. PG-FP4 Flash Memory Programmer User’s Manual U15260E

Other Documents

Document Name Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

User’s Manual U16899EJ2V0UD

CONTENTS

CHAPTER 1 OUTLINE ............................................................................................................................ 16

1.1 Features...................................................................................................................................... 16

1.2 Applications................................................................................................................................ 17

1.3 Ordering Information................................................................................................................. 18

1.4 Pin Configuration (Top View).................................................................................................... 19

1.5 Kx1 Series Lineup...................................................................................................................... 22

1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup.............................................................................................22

1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup ...................................................................................25

1.6 Block Diagram............................................................................................................................ 28

1.7 Outline of Functions.................................................................................................................. 29

CHAPTER 2 PIN FUNCTIONS............................................................................................................... 32

2.1 Pin Function List........................................................................................................................ 32

2.2 Description of Pin Functions.................................................................................................... 36

2.2.1 P00 to P06 (port 0).........................................................................................................................36

2.2.2 P10 to P17 (port 1).........................................................................................................................37

2.2.3 P20 to P27 (port 2).........................................................................................................................38

2.2.4 P30 to P33 (port 3).........................................................................................................................38

2.2.5 P40 to P43 (port 4).........................................................................................................................38

2.2.6 P50 to P53 (port 5).........................................................................................................................38

2.2.7 P60 to P63 (port 6).........................................................................................................................39

2.2.8 P70 to P77 (port 7).........................................................................................................................39

2.2.9 P120 (port 12).................................................................................................................................39

2.2.10 P130 (port 13).................................................................................................................................39

2.2.11 P140 and P141 (port 14)................................................................................................................39

2.2.12 AVREF .............................................................................................................................................40

2.2.13 AVSS ..............................................................................................................................................40

2.2.14 RESET ...........................................................................................................................................40

2.2.15 X1 and X2.......................................................................................................................................40

2.2.16 XT1 and XT2 ..................................................................................................................................40

2.2.17 VDD and EVDD ................................................................................................................................40

2.2.18 VSS and EVSS .................................................................................................................................40

2.2.19 FLMD0 and FLMD1........................................................................................................................40

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 41

CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 45

3.1 Memory Space............................................................................................................................ 45

3.1.1 Internal program memory space.....................................................................................................52

3.1.2 Internal data memory space...........................................................................................................53

3.1.3 Special function register (SFR) area...............................................................................................54

3.1.4 Data memory addressing ...............................................................................................................54

3.2 Processor Registers.................................................................................................................. 60

3.2.1 Control registers.............................................................................................................................60

3.2.2 General-purpose registers..............................................................................................................64

3.2.3 Special function registers (SFRs)...................................................................................................65

User’s Manual U16899EJ2V0UD

3.3 Instruction Address Addressing..............................................................................................70

3.3.1 Relative addressing....................................................................................................................... 70

3.3.2 Immediate addressing ................................................................................................................... 71

3.3.3 Table indirect addressing............................................................................................................... 72

3.3.4 Register addressing....................................................................................................................... 72

3.4 Operand Address Addressing..................................................................................................73

3.4.1 Implied addressing......................................................................................................................... 73

3.4.2 Register addressing....................................................................................................................... 74

3.4.3 Direct addressing........................................................................................................................... 75

3.4.4 Short direct addressing.................................................................................................................. 76

3.4.5 Special function register (SFR) addressing.................................................................................... 77

3.4.6 Register indirect addressing .......................................................................................................... 78

3.4.7 Based addressing.......................................................................................................................... 79

3.4.8 Based indexed addressing............................................................................................................. 80

3.4.9 Stack addressing........................................................................................................................... 81

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 82

4.1 Port Functions............................................................................................................................ 82

4.2 Port Configuration...................................................................................................................... 84

4.2.1 Port 0............................................................................................................................................. 85

4.2.2 Port 1............................................................................................................................................. 89

4.2.3 Port 2............................................................................................................................................. 94

4.2.4 Port 3............................................................................................................................................. 95

4.2.5 Port 4............................................................................................................................................. 97

4.2.6 Port 5............................................................................................................................................. 98

4.2.7 Port 6............................................................................................................................................. 99

4.2.8 Port 7............................................................................................................................................100

4.2.9 Port 12..........................................................................................................................................101

4.2.10 Port 13..........................................................................................................................................102

4.2.11 Port 14..........................................................................................................................................103

4.3 Registers Controlling Port Func tion...................................................................................... 104

4.4 Port Function Operations........................................................................................................ 108

4.4.1 Writing to I/O port..........................................................................................................................108

4.4.2 Reading from I/O port...................................................................................................................108

4.4.3 Operations on I/O port ..................................................................................................................108

CHAPTER 5 CLOCK GENERATOR ....................................................................................................109

5.1 Functions of Clock Generator.................................................................................................109

5.2 Configuration of Clock Generator.......................................................................................... 109

5.3 Registers Controlling Clock Generator ................................................................................. 111

5.4 System Clock Oscillator.......................................................................................................... 118

5.4.1 High-speed system clock oscillator...............................................................................................118

5.4.2 Subsystem clock oscillator............................................................................................................118

5.4.3 When subsystem clock is not used...............................................................................................121

5.4.4 Ring-OSC oscillator......................................................................................................................121

5.4.5 Prescaler.......................................................................................................................................121

5.5 Clock Generator Operation..................................................................................................... 122

5.6 Time Requir ed to Switch Between Ring-OSC Clock and High-Speed System Clock.......129

User’s Manual U16899EJ2V0UD

5.7 Time Required for CPU Clock Switchover............................................................................ 130

5.8 Clock Switching Flowchart and Register Setting................................................................. 131

5.8.1 Switching from Ring-OSC clock to high-speed system clock........................................................131

5.8.2 Switching from high-speed system clock to Ring-OSC clock........................................................132

5.8.3 Switching from high-speed system clock to subsystem clock.......................................................133

5.8.4 Switching from subsystem clock to high-speed system clock.......................................................134

5.8.5 Register settings........................................................................................................ ...................135

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 ........................................................ 136

6.1 Functions of 16-Bit Timer/Event Counters 00 and 01.......................................................... 136

6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01.................................................... 137

6.3 Registers Controlling 16-Bit Timer/E vent Counters 00 and 01 ........................................... 142

6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 .......................................................... 153

6.4.1 Interval timer operation.................................................................................................................153

6.4.2 PPG output operations.................................................................................................................156

6.4.3 Pulse width measurement operations...........................................................................................159

6.4.4 External event counter operation..................................................................................................167

6.4.5 Square-wave output operation......................................................................................................170

6.4.6 One-shot pulse output operation ..................................................................................................172

6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01........................................................... 177

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 .......................................................... 180

7.1 Functions of 8-Bit Timer/ Event Counters 50 and 51 ............................................................ 180

7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51...................................................... 182

7.3 Registers Controlling 8- Bit Timer/Event Counters 50 and 51 ............................................. 184

7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 .......................................................... 189

7.4.1 Operation as interval timer ...........................................................................................................189

7.4.2 Operation as external event counter.............................................................................................191

7.4.3 Square-wave output operation......................................................................................................192

7.4.4 PWM output operation..................................................................................................................193

7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................. 197

CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 198

8.1 Functions of 8-Bit Timers H0 and H1..................................................................................... 198

8.2 Configuration of 8-Bit Timers H0 and H1.............................................................................. 198

8.3 Registers Controlling 8-Bit Timers H0 and H1...................................................................... 202

8.4 Operation of 8-Bit Timers H0 and H1..................................................................................... 208

8.4.1 Operation as interval timer/square-wave output...........................................................................208

8.4.2 Operation as PWM output mode ..................................................................................................211

8.4.3 Carrier generator mode operation (8-bit timer H1 only)................................................................217

CHAPTER 9 WATCH TIMER ............................................................................................................... 224

9.1 Functions of Watch Timer....................................................................................................... 224

9.2 Configuration of Watch Timer................................................................................................ 226

9.3 Register Controlling Watch Timer.......................................................................................... 226

9.4 Watch Timer Operations......................................................................................................... 228

9.4.1 Watch timer operation ..................................................................................................................228

9.4.2 Interval timer operation.................................................................................................................229

User’s Manual U16899EJ2V0UD

9.5 Cautions for Watch Timer ....................................................................................................... 230

CHAPTER 10 WATCHDOG TIMER .....................................................................................................231

10.1 Functions of Watchdog Timer ................................................................................................231

10.2 Configuration of Watchdog Timer.......................................................................................... 233

10.3 Registers Controlling Watchdog Timer ................................................................................. 234

10.4 Operation of Watchdog Timer................................................................................................. 237

10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by option byte........237

10.4.2 Watchdog timer operation when “Ring-OSC can be stopped

by software” is selected by option byte.........................................................................................238

10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped

by software” is selected by option byte)........................................................................................239

10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped

by software” is selected by option byte)........................................................................................241

CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 242

11.1 Functions of Clock Output/Buzzer Output Controller.......................................................... 242

11.2 Configuration of Clock Output/Buzzer Output Controller ................................................... 243

11.3 Register Controlling Clock Output/Buzzer Output Controller............................................. 243

11.4 Clock Output/Buzzer Output Controller Operations............................................................. 245

11.4.1 Clock output operation..................................................................................................................245

11.4.2 Operation as buzzer output...........................................................................................................245

CHAPTER 12 A/D CONVERTER .........................................................................................................246

12.1 Functions of A/D Converter ....................................................................................................246

12.2 Configuration of A/D Converter..............................................................................................247

12.3 Registers Used in A/D Converter............................................................................................ 249

12.4 A/D Converter Operations.......................................................................................................254

12.4.1 Basic operations of A/D converter ................................................................................................254

12.4.2 Input voltage and conversion results ............................................................................................256

12.4.3 A/D converter operation mode......................................................................................................257

12.5 How to Read A/D Converter Characteristics Table............................................................... 260

12.6 Cautions for A/D Converter..................................................................................................... 262

CHAPTER 13 SERIAL INTERFACE UART0 ......................................................................................267

13.1 Functions of Serial Interface UART0...................................................................................... 267

13.2 Configuration of Serial Interface UART0 ...............................................................................268

13.3 Registers Controlling Serial Interface UART0....................................................................... 271

13.4 Operation of Serial Interface UART0...................................................................................... 276

13.4.1 Operation stop mode ....................................................................................................................276

13.4.2 Asynchronous serial interface (UART) mode............................................................................... .277

13.4.3 Dedicated baud rate generator .....................................................................................................283

CHAPTER 14 SERIAL INTERFACE UART6 ......................................................................................288

14.1 Functions of Serial Interface UART6...................................................................................... 288

14.2 Configuration of Serial Interface UART6 ...............................................................................292

14.3 Registers Controlling Serial Interface UART6....................................................................... 295

14.4 Operation of Serial Interface UART6...................................................................................... 304

User’s Manual U16899EJ2V0UD

14.4.1 Operation stop mode....................................................................................................................304

14.4.2 Asynchronous serial interface (UART) mode................................................................................305

14.4.3 Dedicated baud rate generator.....................................................................................................319

CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11................................................................ 326

15.1 Functions of Serial Interfaces CSI10 and CSI11................................................................... 326

15.2 Configuration of Serial Interfaces CSI10 and CSI11 ............................................................ 327

15.3 Registers Controlling Serial Interfaces CSI10 and CSI11.................................................... 329

15.4 Operation of Serial Interfaces CSI10 and CSI11................................................................... 335

15.4.1 Operation stop mode....................................................................................................................335

15.4.2 3-wire serial I/O mode ..................................................................................................................336

CHAPTER 16 MULTIPLIER/DIVIDER................................................................................................... 346

16.1 Functions of Multiplier/Divider............................................................................................... 346

16.2 Configuration of Multiplier/Divider......................................................................................... 346

16.3 Register Controlling Multiplier/Divider.................................................................................. 350

16.4 Operations of Multiplier/Divider ............................................................................................. 351

16.4.1 Multiplication operation................................................................................................................. 351

16.4.2 Division operation.........................................................................................................................353

CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................ 355

17.1 Interrupt Function Types......................................................................................................... 355

17.2 Interrupt Sources and Configuration..................................................................................... 355

17.3 Registers Controlling Interrupt Functions ............................................................................ 359

17.4 Interrupt Servicing Operations............................................................................................... 367

17.4.1 Maskable interrupt acknowledgement ..........................................................................................367

17.4.2 Software interrupt request acknowledgement...............................................................................369

17.4.3 Multiple interrupt servicing............................................................................................................370

17.4.4 Interrupt request hold ...................................................................................................................373

CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 374

18.1 Functions of Key Interrupt...................................................................................................... 374

18.2 Configuration of Key Interrupt................................................................................................ 374

18.3 Register Controlling Key Interrupt......................................................................................... 375

CHAPTER 19 STANDBY FUNCTION.................................................................................................. 376

19.1 Standby Function and Configuration .................................................................................... 376

19.1.1 Standby function...........................................................................................................................376

19.1.2 Registers controlling standby function..........................................................................................378

19.2 Standby Function Operation................................................................................................... 380

19.2.1 HALT mode ..................................................................................................................................380

19.2.2 STOP mode..................................................................................................................................385

CHAPTER 20 RESET FUNCTION ....................................................................................................... 389

20.1 Register for Confirming Reset Source .................................................................................. 396

CHAPTER 21 CLOCK MONITOR........................................................................................................ 397

21.1 Functions of Clock Monitor .................................................................................................... 397

User’s Manual U16899EJ2V0UD

21.2 Configuration of Clock Monitor.............................................................................................. 397

21.3 Registers Controlling Clock Monitor...................................................................................... 398

21.4 Operation of Clock Monitor..................................................................................................... 399

CHAPTER 22 POWER-ON-CLEAR CIRCUIT...................................................................................... 404

22.1 Functions of Power-on-Clear Circuit...................................................................................... 404

22.2 Configuration of Power-on-Clear Circuit............................................................................... 405

22.3 Operation of Power-on-Clear Circuit......................................................................................405

22.4 Cautions for Power-on-Clear Circuit......................................................................................406

CHAPTER 23 LOW-VOLTAGE DETECTOR ....................................................................................... 408

23.1 Functions of Low-Voltage Detector........................................................................................ 408

23.2 Configuration of Low-Voltage Detector.................................................................................408

23.3 Registers Controlling Low-Voltage Detector ........................................................................409

23.4 Operation of Low-Voltage Detector........................................................................................411

23.5 Cautions for Low-Voltage Detector........................................................................................415

CHAPTER 24 OPTION BYTE............................................................................................................... 418

CHAPTER 25 ROM CORRECTION...................................................................................................... 419

25.1 Functions of ROM Correction.................................................................................................419

25.2 Configuration of ROM Correction........................................................................................... 419

25.3 Register Controlling ROM Correction.................................................................................... 421

25.4 ROM Correction Usage Example............................................................................................ 422

25.5 ROM Correction Application...................................................................................................423

25.6 Program Execution Flow.........................................................................................................426

25.7 Cautions for ROM Correction ................................................................................................. 428

CHAPTER 26 FLASH MEMORY..........................................................................................................429

26.1 Internal Memory Size Switching Register.............................................................................. 430

26.2 Internal Expansion RAM Size Switching Register................................................................ 431

26.3 Writing with Flash Programmer..............................................................................................432

26.4 Programming Environment..................................................................................................... 436

26.5 Communication Mode.............................................................................................................. 436

26.6 Connection of Pins on Board.................................................................................................. 439

26.6.1 FLMD0 pin....................................................................................................................................439

26.6.2 FLMD1 pin....................................................................................................................................439

26.6.3 Serial interface pins ......................................................................................................................440

26.6.4 RESET pin....................................................................................................................................442

26.6.5 Port pins........................................................................................................................................442

26.6.6 Other signal pins...........................................................................................................................442

26.6.7 Power supply................................................................................................................................442

26.7 Programming Method..............................................................................................................443

26.7.1 Controlling flash memory..............................................................................................................443

26.7.2 Flash memory programming mode...............................................................................................444

26.7.3 Selecting communication mode....................................................................................................445

26.7.4 Communication commands ..........................................................................................................446

26.8 Flash Memory Programming by Self-Writing........................................................................ 447

User’s Manual U16899EJ2V0UD

26.8.1 Registers used for self-programming function ..............................................................................448

26.9 Boot Swap Function ................................................................................................................ 452

26.9.1 Outline of boot swap function .......................................................................................................452

26.9.2 Memory map and boot area..........................................................................................................453

CHAPTER 27 ON-CHIP DEBUG FUNCTION (µPD78F0138HD ONLY).......................................... 459

CHAPTER 28 INSTRUCTION SET ...................................................................................................... 460

28.1 Conventions Used in Operation List...................................................................................... 460

28.1.1 Operand identifiers and specification methods.............................................................................460

28.1.2 Description of operation column ...................................................................................................461

28.1.3 Description of flag operation column ............................................................................................461

28.2 Operation List........................................................................................................................... 462

28.3 Instructions Listed by Addressing Type ............................................................................... 470

CHAPTER 29 ELECTRICAL SPECIFICATIONS................................................................................. 473

CHAPTER 30 PACKAGE DRAWINGS................................................................................................ 489

CHAPTER 31 RECOMMENDED SOLDERING CONDITIONS........................................................... 494

CHAPTER 32 CAUTIONS FOR WAIT ................................................................................................ 495

32.1 Cautions for Wait ..................................................................................................................... 495

32.2 Peripheral Hardware That Generates Wait............................................................................ 496

32.3 Example of Wait Occurrence.................................................................................................. 497

APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 498

A.1 Software Package.................................................................................................................... 501

A.2 Language Processing Software ............................................................................................. 501

A.3 Control Software...................................................................................................................... 502

A.4 Flash Memory Writing Tools................................................................................................... 502

A.5 Debugging Tools (Hardware).................................................................................................. 503

A.5.1 When using in-circuit emulator QB-78K0KX1H ............................................................................503

A.5.2 When using on-chip debug emulator QB-78K0MINI.....................................................................504

A.6 Debugging Tools (Software)................................................................................................... 504

APPENDIX B NOTES ON TARGET SYSTEM DESIGN................................................................... 505

APPENDIX C REGISTER INDEX......................................................................................................... 507

C.1 Register Index (In Alphabetical Order with Respect to Register Names).......................... 507

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)......................... 511

APPENDIX D LIST OF CAUTIONS..................................................................................................... 515

APPENDIX E REVISION HISTORY ..................................................................................................... 539

E.1 Major Revisions in This Edition ............................................................................................. 539

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

1.1 Features

{ Minimum instruction execution time can be changed from high speed (0.125

speed system clock) to ultra low-speed (122

{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) { ROM, RAM capacities

s: @ 32.768 kHz operation with subsystem clock)

s: @ 16 MHz operation with high-

Program Memory

Part Number

PD78F0132H 16 KB 512 bytes

PD78F0133H 24 KB

PD78F0134H 32 KB

PD78F0136H 48 KB

PD78F0138H, 78F0138HD

Flash memory

(ROM)

Note

Internal High-Speed RAM

1024 bytes

1024 bytes 1024 bytes

60 KB

Data Memory Item

Note

Internal Expansion RAM

−

Note The internal flash memory, internal hi gh-speed RAM capacities, and internal expansio n RAM capacities

can be changed using the internal memory size switching r egister (IMS) and the internal expansion RA M size switching register (IXS).

{ On-chip single-power-supply flash memory { Self-programming (with boot swap function) { On-chip debug function (

PD78F0138HD only)

{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) { Short startup is possible via the CPU default start using the on-chip Ring-OSC { On-chip clock monitor function using on-chip Ring-OSC { On-chip watchdog timer (operable with Ring-OSC clock) { On-chip multiplier/divider { On-chip key interrupt function { On-chip clock output/buzzer output controller { I/O ports: 51 (N-ch open drain: 4) { Timer

PD78F0132H: 7 channels

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD: 8 channels

{ Serial interface

PD78F0132H: 2 channels

(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, 78F0138HD: 3 channels

(UART (LIN (Local Interconnect Network)-bus supported: 1 channel, CSI/UART

Note

: 1 channel)

Note

: 1 channel, CSI: 1 channel)

Note Select either of the functions of these alternate-function pins.

{ 10-bit resolution A/D converter: 8 channels { Supply voltage: V

DD = 2.5 to 5.5 V (with Ring-OSC clock or subsystem clock: VDD = 2.0 to 5.5 V

{ Operating ambient temperature: T

A = −40 to +85°C

Note

)

Note Use the product in a voltage range of 2.2 to 5.5 V bec ause the detection voltage (V

POC) of the power-on-

clear (POC) circuit is 2.1 V ±0.1 V.

Note

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

1.2 Applications

{ Automotive equipment

• System control for body electricals (power windows, keyless entry reception, etc.)

• Sub-microcontrollers for control

{ Home audio, car audio { AV equipment { PC peripheral equipment (keyboards, etc.) { Household electrical appliances

• Outdoor air conditioner units

• Microwave ovens, electric rice cookers { Industrial equipment

• Pumps

• Vending machines

• FA (Factory Automation)

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

1.3 Ordering Information

Part Number Package

PD78F0132HGB-8EU 64-pin plastic LQFP (10 × 10)

PD78F0132HGC-8BS 64-pin plastic LQFP (14 × 14)

PD78F0132HGK-9ET 64-pin plastic TQFP (12 × 12)

PD78F0133HGB-8EU 64-pin plastic LQFP (10 × 10)

PD78F0133HGC-8BS 64-pin plastic LQFP (14 × 14)

PD78F0133HGK-9ET 64-pin plastic TQFP (12 × 12)

PD78F0134HGB-8EU 64-pin plastic LQFP (10 × 10)

PD78F0134HGC-8BS 64-pin plastic LQFP (14 × 14)

PD78F0134HGK-9ET 64-pin plastic TQFP (12 × 12)

PD78F0136HGB-8EU 64-pin plastic LQFP (10 × 10)

PD78F0136HGC-8BS 64-pin plastic LQFP (14 × 14)

PD78F0136HGK-9ET 64-pin plastic TQFP (12 × 12)

PD78F0138HGB-8EU 64-pin plastic LQFP (10 × 10)

PD78F0138HGC-8BS 64-pin plastic LQFP (14 × 14)

PD78F0138HGK-9ET 64-pin plastic TQFP (12 × 12)

PD78F0138HF1-BA2

PD78F0138HDGB-8EU

PD78F0138HDGC-8BS

PD78F0138HDGK-8A8

PD78F0138HDF1-BA2

Notes 1. Under development

2. Only the ES (emulation sample) version is available. Use this product for program evaluation.

Note 1

64-pin plastic FBGA (6 × 6)

Note 2

64-pin plastic LQFP (10 × 10)

Note 2

64-pin plastic LQFP (14 × 14)

Notes 1, 2

64-pin plastic LQFP (12 × 12)

Notes 1, 2

64-pin plastic FBGA (6 × 6)

User’s Manual U16899EJ2V0UD

1.4 Pin Configuration (Top View)

• 64-pin plastic LQFP (10 × 10)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic LQFP (12 × 12)

P20/ANI0

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

REF

FLMD0

X1 X2

RESET

XT1 XT2

P130

P120/INTP0

P33/TI51/TO51/INTP4

P32/INTP3 P31/INTP2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P21/ANI1

P22/ANI2

P23/ANI3

CHAPTER 1 OUTLINE

P24/ANI4

P25/ANI5

P26/ANI6

P27/ANI7

P70/KR0

P71/KR1

P72/KR2

P73/KR3

P74/KR4

P75/KR5

P76/KR6

P77/KR7

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P40 P41 P42 P43 P50 P51 P52 P53 P00/TI000 P01/TI010/TO00 P02/SO11 P03/SI11 P04/SCK11 P05/SSI11 P06/TI011 EV

Note

/TI001

Note

/TO01

Note

P62

P63

P30/INTP1

P140/PCL/INTP6

P141/BUZ/INTP7

P13/TxD6

P14/RxD6

P15/TOH0

P12/SO10

P16/TOH1/INTP5

P60

P61

P11/SI10/RxD0

P10/SCK10/TxD0

P17/TI50/TO50/FLMD1

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the

78F0136H, 78F0138H, and 78F0138HD.

Caution Connect the AV

SS pin to VSS.

User’s Manual U16899EJ2V0UD

PD78F0133H, 78F0134H,

CHAPTER 1 OUTLINE

• 64-pin plastic FBGA (6 × 6) (µPD78F0138H and 78F0138HD only)

Top View Bottom View

8 7 6 5 4 3 2 1

HGFEDCBA ABCDEFGH

Index mark

Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name

A1 P31/INTP2 C1 P30/INTP1 E1 P12/SO10 G1 P63 A2 P32/INTP3 C2 P17/TI50/TO50/FLMD1 E2 P11/SI10/RxD0 G2 P05/SSI11/TI001 A3 XT2 C3 P141/BUZ/INTP7 E3 P10/SCK10/TxD0 G3 P04/SCK11 A4 X2 C4 P130 E4 P62 G4 P01/TI010/TO00 A5 VSS C5 RESET E5 P52 G5 P50 A6 FLMD0 C6 P23/ANI3 E6 P70/KR0 G6 P42 A7 AVSS C7 P22/ANI2 E7 P71/KR1 G7 P76/KR6 A8 AVREF C8 P24/ANI4 E8 P73/KR3 G8 P77/KR7 B1 P140/PCL/INTP6 D1 P14/RxD6 F1 P61 H1 EVSS B2 P33/TI51/TO51/INTP4 D2 P13/TxD6 F2 P60 H2 EVDD B3 P120/INTP0 D3 P15/TOH0 F3 P02/SO11 H3 P03/SI11 B4 XT1 D4 P16/TOH1/INTP5 F4 P53 H4 P06/TI011/TO01 B5 X1 D5 NC F5 P43 H5 P00/TI000 B6 VDD D6 P25/ANI5 F6 P75/KR5 H6 P51 B7 P20/ANI0 D7 P26/ANI6 F7 P72/KR2 H7 P41 B8 P21/ANI1 D8 P27/ANI7 F8 P74/KR4 H8 P40

Caution Connect the AV

SS pin to VSS.

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

Pin Identification

ANI0 to ANI7: Analog input AV

REF: Analog reference voltage

SS: Analog ground

BUZ: Buzzer output EV

DD: Power supply for port

SS: Ground for port

FLMD0, FLMD1: Flash programming mode INTP0 to INTP7: External interrupt input KR0 to KR7: Key return NC: Non-connection P00 to P06: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P33: Port 3 P40 to P43: Port 4 P50 to P53: Port 5 P60 to P63: Port 6 P70 to P77: Port 7 P120: Port 12

P140, P141: Port 14 PCL: Programmable clock output RESET: Reset RxD0, RxD6: Receive data SCK10, SCK11 SI10, SI11 SO10, SO11

Note

SSI11

Note

: Serial clock input/output

Note

: Serial data input

Note

: Serial data output

: Serial interface chip select input TI000, TI010, TI001

Note

, TI011

Note

, TI50, TI51: Timer input TO00, TO01

Note

, TO50, TO51, TOH0, TOH1: Timer output TxD0, TxD6: Transmit data V

DD: Power supply

SS: Ground

X1, X2: Crystal oscillator (high-speed system clock) XT1, XT2: Crystal oscillator (subsystem clock)

P130: Port 13

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the µPD78F0133H, 78F0134H,

78F0136H, 78F0138H, and 78F0138HD.

User’s Manual U16899EJ2V0UD

1.5 Kx1 Series Lineup

1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup

Note Product with on-chip debug function

•

30-pin SSOP (7.62 mm 0.65 mm pitch)

78K0/KB1

PD78F0103

Two-power-supply flash memory: 24 KB, RAM: 768 B

•

44-pin LQFP (10 × 10 mm 0.8 mm pitch)

78K0/KC1

PD78F0114

Two-power-supply flash memory: 32 KB, RAM: 1 KB

52-pin LQFP (10 × 10 mm 0.65 mm pitch)

•

78K0/KD1

PD78F0124

Two-power-supply flash memory: 32 KB, RAM: 1 KB

•

64-pin LQFP, TQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)

78K0/KE1

PD78F0138

Two-power-supply flash memory: 60 KB, RAM: 2 KB

PD78F0134

Two-power-supply flash memory: 32 KB, RAM: 1 KB

80-pin TQFP, QFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)

•

78K0/KF1

PD78F0148

µµ

Two-power-supply flash memory: 60 KB, RAM: 2 KB

CHAPTER 1 OUTLINE

78K0/KB1+

PD780103

µµ

Mask ROM: 24 KB, RAM: 768 B

PD780102

Mask ROM: 16 KB, RAM: 768 B

PD780101

Mask ROM: 8 KB, RAM: 512 B

PD78F0103H

Single-power-supply flash memory: 24 KB, RAM: 768 B

PD78F0102H

Single-power-supply flash memory: 16 KB, RAM: 768 B

PD78F0101H

Single-power-supply flash memory: 8 KB, RAM: 512 B

78K0/KC1+

PD780114

Mask ROM: 32 KB, RAM: 1 KB

PD780113

Mask ROM: 24 KB, RAM: 1 KB

PD780112

Mask ROM: 16 KB, RAM: 512 B

PD780111

Mask ROM: 8 KB, RAM: 512 B

PD78F0114H/HD

Single-power-supply flash memory: 32 KB, RAM: 1 KB

PD78F0113H

Single-power-supply flash memory: 24 KB, RAM: 1 KB

PD78F0112H

Single-power-supply flash memory: 16 KB, RAM: 512 B

Note

78K0/KD1+

PD780124

Mask ROM: 32 KB, RAM: 1 KB

PD780123

Mask ROM: 24 KB, RAM: 1 KB

PD780122

Mask ROM: 16 KB, RAM: 512 B

PD780121

Mask ROM: 8 KB, RAM: 512 B

PD78F0124H/HD

Single-power-supply flash memory: 32 KB, RAM: 1 KB

PD78F0123H

Single-power-supply flash memory: 24 KB, RAM: 1 KB

PD78F0122H

Single-power-supply flash memory: 16 KB, RAM: 512 B

Note

78K0/KE1+

PD780138

Mask ROM: 60 KB, RAM: 2 KB

PD780136

Mask ROM: 48 KB, RAM: 2 KB

PD780134

Mask ROM: 32 KB, RAM: 1 KB

PD780133

Mask ROM: 24 KB, RAM: 1 KB

PD780132

Mask ROM: 16 KB, RAM: 512 B

PD780131

Mask ROM: 8 KB, RAM: 512 B

PD78F0138H/HD

Single-power-supply flash memory: 60 KB, RAM: 2 KB

PD78F0136H

Single-power-supply flash memory: 48 KB, RAM: 2 KB

PD78F0134H

Single-power-supply flash memory: 32 KB, RAM: 1 KB

PD78F0133H

Single-power-supply flash memory: 24 KB, RAM: 1 KB

PD78F0132H

Single-power-supply flash memory: 16 KB, RAM: 512 B

Note

78K0/KF1+

PD780148

Mask ROM: 60 KB, RAM: 2 KB

PD780146

Mask ROM: 48 KB, RAM: 2 KB

PD780144

Mask ROM: 32 KB, RAM: 1 KB

PD780143

Mask ROM: 24 KB, RAM: 1 KB

PD78F0148H/HD

Single-power-supply flash memory: 60 KB, RAM: 2 KB

Note

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

The list of functions in the 78K0/Kx1 is shown below.

Part Number

78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins Internal

memory (KB)

Mask ROM 8

Flash memory

16/

− 8/

−

24/

− 8/

−

24/

− 8/

−

24/

− 48/

−

− 24/

48/

−

RAM 0.5 0.75 0.5 1 0.5 1 0.5 1 2 1 2 Power supply voltage VDD = 2.5 to 5.5 V Minimum instruction execution time

0.166

s (when 12 MHz, VDD =

4.0 to 5.5 V)

0.2

s (when 10 MHz, VDD =

3.5 to 5.5 V)

0.238

s (when 8.38 MHz, VDD

<Connect REGC pin to V

0.166

s (when 12 MHz, VDD = 4.0 to 5.5 V)

0.2

s (when 10 MHz, VDD = 3.5 to 5.5 V)

0.238

s (when 8.38 MHz, VDD = 3.0 to 5.5 V)

0.4

s (when 5 MHz, VDD = 2.5 to 5.5 V)

Notes 1, 2

DD>

= 3.0 to 5.5 V)

0.4

s (when 5 MHz, VDD = 2.5

to 5.5 V)

Clock

X1 input 2 to 12 MHz

Subclock

−

32.768 kHz

Ring-OSC 240 kHz (TYP.) Port

CMOS I/O 17 19 26 38 54

CMOS input 4 8

CMOS output 1

Timer

N-ch open-drain I/O

−

16 bits (TM0) 1 ch 2 ch 1 ch 2 ch

8 bits (TM5) 1 ch 2 ch

8 bits (TMH) 2 ch

For watch

−

1 ch

WDT 1 ch Serial

interface

3-wire CSI

Automatic transmit/

Note 3

1 ch 2 ch 1 ch 2 ch

−

1 ch

receive 3-wire CSI

Note 3

UART

−

1 ch

UART supporting LIN-bus 1 ch 10-bit A/D converter 4 ch 8 ch

External 6 7 8 9 9 Interrupt

Internal 11 12 15 16 19 17 20 Key return input Reset

RESET pin Provided

−

4 ch 8 ch

POC 2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)

LVI 2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)

Clock monitor Provided

WDT Provided Clock output/buzzer output

− Clock output

Provided

only Multiplier/divider ROM correction

−

16 bits × 16 bits, 32 bits ÷ 16 bits

Provided

− Standby function HALT/STOP mode Operating ambient temperature

Standard and special (A) grade products: −40 to +85°C Special (A1) grade products: −40 to +110°C (mask ROM version),

−40 to +105°C (flash memory version) Special (A2) grade products: −40 to +125°C (mask ROM version)

Notes 1. If the POC circuit detection voltage (VPOC) is used wit h 2.85 V ±0.15 V, then use the products in the volt age

range of 3.0 to 5.5 V.

2. If the POC circuit detection voltage (V

POC) is used with 3.5 V ±0.2 V, then use the products in the voltage

range of 3.7 to 5.5 V.

3. Select either of the functions of these alternate-function pins.

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

The list of functions in the 78K0/Kx1+ is shown below.

Part Number

Item Number of pins 30 pins 44 pins 52 pins 64 pins 80 pins

Flash memory 8 16/24 16 24/32 16 24/32 16 24/32 48/60 60 Internal memory (KB)

RAM 0.5 0.75 0.5 1 0.5 1 0.5 1 2 2 Power supply voltage VDD = 2.5 to 5.5 V (with Ring-OSC clock or subclock: VDD = 2.0 to 5.5 V

Minimum instruction execution time 0.125 µs (when 16 MHz, VDD = 4.0 to 5.5 V), 0.2 µs (when 10 MHz, VDD = 3.5 to 5.5 V),

Clock

Crystal/ceramic 2 to 16 MHz

RC 3 to 4 MHz

Subclock

Ring-OSC 240 kHz (TYP.) Ports

CMOS I/O 17 19 26 38 54

CMOS input 4 8

CMOS output 1

N-ch open-drain I/O Timer

16 bits (TM0) 1 ch 2 ch

8 bits (TM5) 1 ch 2 ch

8 bits (TMH) 2 ch

For watch

WDT 1 ch Serial

interface

3-wire CSI

Automatic transmit/

Note 2

1 ch 2 ch

receive 3-wire CSI

Note 2

UART

UART supporting LIN-bus 1 ch 10-bit A/D converter 4 ch 8 ch Interrupts

External 6 7 8 9 9

Internal 11 12 15 16 19 20 Key return input Reset

RESET pin Provided

POC 2.1 V ±0.1 V (detection voltage is fixed)

LVI 2.35 V/2.6 V/2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V

Clock monitor Provided

WDT Provided Clock output/buzzer output

External bus interface Multiplier/divider ROM correction Self-programming function Provided

Product with on-chip debug

function Standby function HALT/STOP mode Operating ambient temperature TA = −40 to +85°C

78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+

Note 1

)

0.238

s (when 8.38 MHz, VDD = 3.0 to 5.5 V), 0.4 µs (when 5 MHz, VDD = 2.5 to 5.5 V)

−

4 ch 8 ch

32.768 kHz

1 ch

(selectable by software)

−

Clock output

Provided

only

−

PD78F0114HD, 78F0124HD, 78F0138HD, 78F0148HD

16 bits × 16 bits, 32 bits ÷ 16 bits

Provided

−

Notes 1. Because the POC circuit dete ction voltage (VPOC) is 2.1 V ±0.1 V, use the products in the voltag e range of

2.2 to 5.5 V.

2. Select either of the functions of these alternate-function pins.

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup

•

64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch)

•

64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch)

•

64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch)

V850ES/KE1

PD70F3207HY

PD70F3207H

Single-power-supply flash memory: 128 KB, RAM: 4 KB

•

80-pin plastic TQFP (12 × 12 mm, 0.5 mm pitch)

•

80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch)

V850ES/KF1

PD70F3211HY

PD70F3211H

Single-power-supply flash memory: 256 KB, RAM: 12 KB

PD70F3210HY

PD70F3210H

Single-power-supply flash memory: 128 KB, RAM: 6 KB

PD70F3210Y

PD70F3210

Two-power-supply flash memory: 128 KB, RAM: 6 KB

•

100-pin plastic LQFP (14 × 14 mm, 0.5 mm pitch)

•

100-pin plastic QFP (14 × 20 mm, 0.65 mm pitch)

V850ES/KG1

PD70F3215HY

PD70F3215H

Single-power-supply flash memory: 256 KB, RAM: 16 KB

PD70F3214HY

PD70F3214H

Single-power-supply flash memory: 128 KB, RAM: 6 KB

PD70F3214Y

PD70F3214

Two-power-supply flash memory: 128 KB, RAM: 6 KB

•

144-pin plastic LQFP (20 × 20 mm, 0.5 mm pitch)

V850ES/KJ1

PD70F3218HY

PD70F3218H

Single-power-supply flash memory: 256 KB, RAM: 16 KB

PD70F3217HY

PD70F3217H

Single-power-supply flash memory: 128 KB, RAM: 6 KB

PD70F3217Y

PD70F3217

Two-power-supply flash memory: 128 KB, RAM: 6 KB

PD703207Y

PD703207

Mask ROM: 128 KB, RAM: 4 KB

PD703206Y

PD703206

Mask ROM: 96 KB, RAM: 4 KB

PD703211Y

PD703211

Mask ROM: 256 KB, RAM: 12 KB

PD703210Y

PD703210

Mask ROM: 128 KB, RAM: 4 KB

PD703209Y

PD703209

Mask ROM: 96 KB, RAM: 4 KB

PD703208Y

PD703208

Mask ROM: 64 KB, RAM: 4 KB

PD703215Y

PD703215

Mask ROM: 256 KB, RAM: 16 KB

PD703214Y

PD703214

Mask ROM: 128 KB, RAM: 6 KB

PD703213Y

PD703213

Mask ROM: 96 KB, RAM: 4 KB

PD703212Y

PD703212

Mask ROM: 64 KB, RAM: 4 KB

PD703218Y

PD703218

Mask ROM: 256 KB, RAM: 16 KB

PD703217Y

PD703217

Mask ROM: 128 KB, RAM: 6 KB

PD703216Y

PD703216

Mask ROM: 96 KB, RAM: 4 KB

V850ES/KE1+

PD70F3302Y

PD70F3302

Single-power-supply flash memory: 128 KB, RAM: 4 KB

Mask ROM: 128 KB, RAM: 4 KB

Mask ROM: 96 KB, RAM: 4 KB

V850ES/KF1+

PD70F3308Y

PD70F3308

Single-power-supply flash memory: 256 KB, RAM: 12 KB

PD70F3306Y

PD70F3306

Single-power-supply flash memory: 128 KB, RAM: 6 KB

Mask ROM: 256 KB, RAM: 12 KB

V850ES/KG1+

PD70F3313Y

PD70F3313

Single-power-supply flash memory: 256 KB, RAM: 16 KB

PD70F3311Y

PD70F3311

Single-power-supply flash memory: 128 KB, RAM: 6 KB

Mask ROM: 256 KB, RAM: 16 KB

V850ES/KJ1+

PD70F3318Y

PD70F3318

Single-power-supply flash memory: 256 KB, RAM: 16 KB

PD70F3316Y

PD70F3316

Single-power-supply flash memory: 128 KB, RAM: 6 KB

Mask ROM: 256 KB, RAM: 16 KB

PD703302Y

PD703302

PD703301Y

PD703301

PD703308Y

PD703308

PD703313Y

PD703313

PD703318Y

PD703318

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

The list of functions in the V850ES/Kx1 is shown below.

Part Number

Item Number of pins 64 pins 80 pins 100 pins 144 pins Internal

memory (bytes)

Power supply voltage VDD = 2.7 to 5.5 V Minimum instruction execution time 50 ns @ 20 MHz Clock

Ports

Timer

RTO 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch Serial

interface

External bus

DMA controller 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter Interrupts

Key return input 8 ch 8 ch 8 ch 8 ch Reset

ROM correction 4 points Regulator Not provided Provided Standby function HALT/IDLE/STOP/sub-IDLE mode Operating ambient temperature TA = −40 to +85°C

Mask ROM 96/128

Flash memory RAM 4 4 6 12 4 6 16 6 16

X1 input 2 to 10 MHz Subclock 32.768 kHz Ring-OSC CMOS input 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O 1 2 4 6 16 bits (TMP) 1 ch 16 bits (TM0) 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch WDT2 1 ch 1 ch 1 ch 1 ch

CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit/

receive 3-wire CSI UART 2 ch 2 ch 2 ch 3 ch UART supporting LIN-bus

2CNote

1 ch 1 ch 1 ch 2 ch

I Address space Address bus Mode

External 8 8 8 8 Internal 26 26 29 31 34 40 43

RESET pin Provided POC Not provided LVI Not provided Clock monitor Not provided WDT1 Provided WDT2 Provided

V850ES/KE1 V850ES/KF1 V850ES/KG1 V850ES/KJ1

64/

−

128

−

− − − −

−

− − − −

− −

128

− −

−

Multiplexed mode only Multiplexed/separate mode

256

−

128

−

1 ch 2 ch 2 ch

128 KB 3 MB 15 MB

16 bits 22 bits 24 bits

1 ch

−

256

64/

−

− −

128

−

256

−

128

−

1 ch

2 ch 2 ch

−

256

96/

128

256

−

128

−

1 ch

Note Provided in the Y version only.

−

256

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

The list of functions in the V850ES/Kx1+ is shown below.

Part Number

Item Number of pins 64 pins 80 pins 100 pins 144 pins Internal

memory (bytes)

Power supply voltage VDD = 2.7 to 5.5 V Minimum instruction execution time 50 ns @ 20 MHz Clock

Ports

Timer

RTO 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch Serial

interface

External bus

DMA controller 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter Interrupts

Key return input 8 ch 8 ch 8 ch 8 ch Reset

ROM correction 4 points Regulator Not provided Provided Standby function HALT/IDLE/STOP/sub-IDLE mode Operating ambient temperature TA = −40 to +85°C

Mask ROM 96/128 Flash memory RAM 4 6 12 6 16 6 16

X1 input 2 to 10 MHz Subclock 32.768 kHz Ring-OSC 240 kHz (TYP.) CMOS input 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O 1 2 4 6 16 bits (TMP) 1 ch 1 ch 1 ch 1 ch 16 bits (TM0) 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch WDT2 1 ch 1 ch 1 ch 1 ch

CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit/

receive 3-wire CSI UART 1 ch 1 ch 1 ch 2 ch UART supporting LIN-bus 1 ch 1 ch 1 ch 1 ch

2CNote

1 ch 1 ch 1 ch 2 ch

I Address space Address bus Mode

External 9 9 9 9 Internal 27 30 42 48

RESET pin Provided POC Fixed to 2.7 V or lower LVI 3.1 V/3.3 V ±0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software) Clock monitor Provided (monitoring by Ring-OSC) WDT1 Provided WDT2 Provided

V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+

−

128

−

− −

128 256

− −

1 ch 2 ch 2 ch

128 KB 3 MB 15 MB

16 bits 22 bits 24 bits

Multiplexed mode only Multiplexed/separate mode

−

256

128/256

−

256

4 ch 4 ch

2 ch 2 ch

128/256

−

256

Note Provided in the Y version only.

User’s Manual U16899EJ2V0UD

1.6 Block Diagram

CHAPTER 1 OUTLINE

TO01

TO00/TI010/P01

TI000/P00

Note 1

/TI011

TI001

Note 1 Note 1

TOH0/P15

TOH1/P16

TI50/TO50/P17

TI51/TO51/P33

RxD0/P11

TxD0/P10

/P06 /P05

16-bit timer/ event counter 00

16-bit timer/

Note 1

event counter 01

8-bit timer H0

8-bit timer H1

8-bit timer/ event counter 50

8-bit timer/ event counter 51

Watch timer

Watchdog timer

Serial interface UART0

78K/0

CPU core

Flash

memory

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 12

P00 to P06

P10 to P17

P20 to P27

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P77

P120

Port 13 P130

Port 14 P140, P141

Buzzer output

BUZ/P141

Notes 1.

RxD6/P14

TxD6/P13

SI10/P11

SO10/P12

SCK10/P10

Note 1

SI11

Note 1

SO11

Note 1

SCK11

Note 1

SSI11

ANI0/P20 to

ANI7/P27

INTP0/P120

INTP1/P30 to

INTP4/P33 INTP5/P16

INTP6/P140, INTP7/P141

Serial interface UART6

Serial interface CSI10

Internal

high-speed

RAM

Internal

expansion

Note 2

RAM

Clock output control

/P03 /P02

/P04

Serial interface

Note 1

CSI11

/P05

REF

A/D converter

Interrupt control

ROM correction

VSS,

Multiplier & divider

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD only.

PD78F0136H, 78F0138H, and 78F0138HD only

VDD,

FLMD0,

FLMD1

Clock monitor

Power on clear/

low voltage

indicator

Key return

Reset control

Ring-OSC

System control

Note 2

PCL/P140

POC/LVI

control

KR0/P70 to

KR7/P77

RESET X1

X2 XT1 XT2

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

1.7 Outline of Functions

(1/2)

Item

Internal memory (bytes)

Flash memory (self-programming supported)

Note 1

High-speed RAM

Expansion RAM Memory space 64 KB High-speed system clock

(oscillation frequency)

Ring-OSC clock (oscillation frequency)

Subsystem clock (oscillation frequency)

General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 ba nks) Minimum instruction execution

time

Instruction set

I/O ports

Timers

Timer outputs

Clock output

Buzzer output 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: @10 MHz operation) A/D converter 10-bit resolution × 8 channels

Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM

capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS).

2. Use the product in a voltage range of 2.2 to 5.5 V b ecause the detection voltage (V clear (POC) circuit is 2.1 V ±0.1 V.

PD78F0132HµPD78F0133HµPD78F0134HµPD78F0136H µPD78F0138HµPD78F0138HD

16 K 24 K 32 K 48 K 60 K 60 K

Note 1

512 1 K

Note 1

Crystal/ceramic/external clock oscillation (2 to 16 MHz: V 2 to 8.38 MHz: V

On-chip Ring oscillation (240 kHz (TYP.): V

Crystal/external clock oscillation (32.768 kHz: V

0.125 µs/0.25 µs/0.5 µs/1.0 µs/2.0 µs (high-speed system clock: @ fXP = 16 MHz operation)

8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.) operation)

s (subsystem clock: when operating at fXT = 32.768 kHz)

122

• 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation)

• BCD adjust, etc. Total: 51 CMOS I/O 38

CMOS input 8 CMOS output 1 N-ch open-drain I/O 4

• 16-bit timer/event counter: 2 channels (1 channel only in the

• 8-bit timer/event counter: 2 channels

• 8-bit timer: 2 channels

• Watch timer 1 channel

• Watchdog timer: 1 channel 5 (PWM

output: 4)

• 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (high-speed system clock: @10 MHz operation)

• 32.768 kHz (subsystem clock: @32.768 kHz operation)

−

DD = 4.0 to 5.5 V, 2 to 10 MHz: VDD = 3.5 to 5.5 V,

DD = 3.0 to 5.5 V, 2 to 5 MHz: VDD = 2.5 to 5.5 V)

1 K

DD = 2.0 to 5.5 V

Note 2

)

6 (PWM output: 4)

Note 2

)

PD78F0132H)

POC) of the power-on-

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

(2/2)

Item

Serial interface

Multiplier/divider

Vectored interrupt sources

Internal 16 19

External 9 Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7). Reset

ROM correction On-chip debug function Supply voltage VDD = 2.5 to 5.5 V (with Ring-OSC clock or subsystem clock: VDD = 2.0 to 5.5 V Operating ambient temperature TA = −40 to +85°C Package

PD78F0132H µPD78F0133HµPD78F0134HµPD78F0136HµPD78F0138H µPD78F0138HD

• UART mode supporting LIN-bus: 1 channel

• 3-wire serial I/O mode: 1 channel (none in the

• 3-wire serial I/O mode/UART mode

Note 1

: 1 channel

PD78F0132H)

• 16 bits × 16 bits = 32 bits (multiplication)

• 32 bits ÷ 16 bits = 32 bits remainder of 16 bits (division)

• Reset using RESET pin

• Internal reset by watchdog timer

• Internal reset by clock monitor

• Internal reset by power-on-clear

• Internal reset by low-voltage detector

−

Provided

Note 2

)

• 64-pin plastic LQFP (10 × 10)

• 64-pin plastic LQFP (14 × 14)

• 64-pin plastic TQFP (12 × 12)

• 64-pin plastic FBGA (6 × 6)

• 64-pin plastic LQFP (12 × 12)

Note 3

Note 4

Notes 1. Select either of the functions of these alternate-function pins.

2. Use the product in a voltage range of 2.2 to 5.5 V b ecause the detection voltage (VPOC) of the power- on-

clear (POC) circuit is 2.1 V ±0.1 V.

PD78F0138H and 78F0138HD only

4. µPD78F0138HD only

User’s Manual U16899EJ2V0UD

CHAPTER 1 OUTLINE

An outline of the timer is shown below.

Operation mode

Function

16-Bit Timer/

Event Counters 00

TM00 TM01

and 01

Note 1

8-Bit Timer/

Event Counters

8-Bit Timers H0 and

50 and 51

TM50 TM51 TMH0 TMH1

Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel

External event counter 1 channel 1 channel 1 channel 1 channel

Watchdog timer

− − − − − − −

− − − −

Watch

Timer

1 channel

Timer output 1 output 1 output 1 output 1 output 1 output 1 output

PPG output 1 output 1 output

PWM output

− −

Pulse width measurement 2 inputs 2 inputs

− − − − − −

1 output 1 output 1 output 1 output

− − − − − − Square-wave output 1 output 1 output 1 output 1 output 1 output 1 output Interrupt source 2 2 1 1 1 1 1

Watchdog

Timer

Note 2

1 channel

− −

−

Notes 1. 16-bit timer/ev ent counter 01 is available only in the µPD78F0133H, 78F0134H, 78F0136H, 78F0138H,

and 78F0138HD.

2. In the watch timer, the watch timer function and interval timer function can be used simultaneously.

Remark TM51 and TMH1 can be used in combination as a carrier generator mode.

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

There are three types of pin I/O buffer power supplies: AV

power supplies and the pins is shown below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27 VDD Pins other than port pins

(1) Port pins (1/2)

Pin Name I/O Function After Reset Alternate Function

P00 TI000

I/O P01 TI010/TO00 P02 SO11 P03 SI11 P04 SCK11 P05 SSI11 P06 P10 SCK10/TxD0

I/O P11 SI10/RxD0 P12 SO10 P13 TxD6 P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 P20 to P27 Input

P30 to P32 INTP1 to INTP3

I/O

P33

Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 2. 8-bit input-only port.

Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

REF, EVDD, and VDD. The relationship between these

Input

Note

/TI001

Note

/TO01

TI011

Input

TI50/TO50/FLMD1

Input ANI0 to ANI7

Input

INTP4/TI51/TO51

Note

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the

78F0136H, 78F0138H, and 78F0138HD.

User’s Manual U16899EJ2V0UD

PD78F0133H, 78F0134H,

CHAPTER 2 PIN FUNCTIONS

(1) Port pins (2/2)

Pin Name I/O Function After Reset Alternate Function

P40 to P43 I/O

P50 to P53 I/O

P60 to P63 I/O

P70 to P77 I/O

P120 I/O

P130 Output

P140 PCL/INTP6 P141

I/O

Port 4. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 6. 4-bit I/O port (N-ch open drain). Input/output can be specified in 1-bit units.

Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 13. 1-bit output-only port.

Port 14. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Input

Input KR0 to KR7

Input INTP0

Output

Input

BUZ/INTP7

−

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins (1/2)

Pin Name I/O Function After Reset Alternate Function

INTP0 P120

Input INTP1 to INTP3 P30 to P32 INTP4 P33/TI51/TO51

External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified

Input

INTP5 P16/TOH1 INTP6 P140/PCL INTP7 SI10 P11/RxD0

Note

SI11 SO10 P12

Note

SO11 SCK10 P10/TxD0

Note

SCK11 SSI11

Note

Input Serial interface chip select input Input P05/TI001

RxD0 P11/SI10

Input Serial data input to serial interface Input

Output Serial data output from serial interface Input

I/O Clock input/output for serial interface Input

Input Serial data input to asynchronous serial interface Input RxD6 TxD0 P10/SCK10

Output Serial data output from asynchronous serial interface Input TxD6 TI000

Input

External count clock input to 16-bit timer/event counter 00

Input

P141/BUZ

P03

P02

P04

P14

P13

P00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00

TI001

Note

External count clock input to 16-bit timer/event counter 01

P05/SSI11

Note

Capture trigger input to capture registers (CR001, CR011) of 16-bit timer/event counter 01

TI010

Capture trigger input to capture register (CR000) of 16-bit

P01/TO00 timer/event counter 00

TI011

Note

Capture trigger input to capture register (CR001) of 16-bit

P06/TO01

Note

timer/event counter 01

TO00 16-bit timer/event counter 00 output P01/TI010

Note

TO01 TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50/FLMD1 TI51 TO50 8-bit timer/event counter 50 output P17/TI50/FLMD1

Output

Input

Output

16-bit timer/event counter 01 output

External count clock input to 8-bit timer/event counter 51

Input

P06/TI011

Note

P33/TO51/INTP4

TO51 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 8-bit timer H0 output P15 TOH1 PCL Output

8-bit timer H1 output Clock output (for trimming of high-speed system clock,

P16/INTP5

Input P140/INTP6

subsystem clock)

BUZ Output Buzzer output Input P141/INTP7 ANI0 to ANI7 Input A/D converter analog input Input P20 to P27

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the

PD78F0133H, 78F0134H,

78F0136H, 78F0138H, and 78F0138HD.

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins (2/2)

Pin Name I/O Function After Reset Alternate Function

AVREF Input

AVSS

KR0 to KR7 Input Key interrupt input Input P70 to P77 RESET Input System reset input X1 Input X2 XT1 Input XT2 VDD EVDD VSS EVSS FLMD0 FLMD1 NC

A/D converter reference voltage input and positive power supply for port 2

A/D converter ground potential. Make the same potential as

−

SS or VSS.

Connecting resonator for high-speed system clock

− Connecting resonator for subsystem clock

− Positive power supply (except for ports)

− Positive power supply for ports

− Ground potential (except for ports)

− Ground potential for ports

− Flash memory programming mode setting.

−

Not internally connected. Leave open.

−

− −

Input P17/TI50/TO50

− −

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P06 (port 0)

P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O,

and chip select input.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

(2) Control mode

P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input.

(a) TI000, TI001

These are the pins for inputting an external count clock to 16-bit tim er/event cou nters 00 and 01 a nd are als o for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit timer/event counters 00 and 01.

(b) TI010, TI011

These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit timer/event counters 00 and 01.

These are timer output pins.

(d) SI11

This is a serial interface serial data input pin.

(e) SO11

This is a serial interface serial data output pin.

(f) SCK11

This is the serial interface serial clock I/O pin.

(g) SSI11

This is the serial interface chip select input pin.

Note TI001, TI011, TO01, SI11, SO11, SCK11, and SSI11 are available only in the

Note

78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

PD78F0133H,

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

2.2.2 P10 to P17 (port 1)

P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial

interface data I/O, clock I/O, timer I/O, and flash memory programming mode setting.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).

(2) Control mode

P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and flash memory programming mode setting.

(a) SI10

This is a serial interface serial data input pin.

(b) SO10

This is a serial interface serial data output pin.

This is a serial interface serial clock I/O pin.

(d) RxD0, RxD6

These are the serial data input pins of the asynchronous serial interface.

(e) TxD0, TxD6

These are the serial data output pins of the asynchronous serial interface.

(f) TI50

This is the pin for inputting an external count clock to 8-bit timer/event counter 50.

(g) TO50, TOH0, and TOH1

These are timer output pins.

(h) INTP5

This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.

(i) FLMD1

This is the pin for setting the flash memory programming mode.

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

2.2.3 P20 to P27 (port 2)

P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units.

(1) Port mode

P20 to P27 function as an 8-bit input-only port.

(2) Control mode

P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When usin g these pins as analog input pins, see (5) ANI0/P20 to ANI7/P27 in 12.6 Cautions for A/D Converter.

2.2.4 P30 to P33 (port 3)

P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and

timer I/O.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).

(2) Control mode

P30 to P33 function as external interrupt request input pins and timer I/O pins.

(a) INTP1 to INTP4

These are the external interrupt request input pins for which the valid edge (rising edge, falli ng edge, or both rising and falling edges) can be specified.

(b) TI51

This is an external count clock input pin to 8-bit timer/event counter 51.

This is a timer output pin.

Caution In the

PD78F0138HD, be sure to pull the P31 pin down after reset to prevent malfunction.

Remark P31/INTP2 and P32/INTP3 of the

PD78F0138HD can be used as on-chip de bug mode setting pins

when the on-chip debug function is used. For details, refer to CHAPTER 27 ON-CHIP DEBUG

FUNCTION (

PD78F0138HD ONLY).

2.2.5 P40 to P43 (port 4)

P40 to P43 function as a 4-bit I/O port. P40 to P43 can be set to input or output in 1-bit units using port mode

2.2.6 P50 to P53 (port 5)

P50 to P53 function as a 4-bit I/O port. P50 to P53 can be set to input or output in 1-bit units using port mode

User’s Manual U16899EJ2V0UD

CHAPTER 2 PIN FUNCTIONS

2.2.7 P60 to P63 (port 6)

P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port

mode register 6 (PM6).

P60 to P63 are N-ch open-drain pins.

2.2.8 P70 to P77 (port 7)

P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins. The following operation modes can be specified in 1-bit units.

(1) Port mode

P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).

(2) Control mode

P70 to P77 function as key interrupt input pins.

2.2.9 P120 (port 12)

P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified.

(1) Port mode

P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).

(2) Control mode

P120 functions as an external interrupt request input pin (I NTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.

2.2.10 P130 (port 13)

P130 functions as a 1-bit output-only port.

2.2.11 P140 and P141 (port 14)

P140 and P141 function as a 2-bit I/O port. These pins also function as external interrupt request input, cl ock

output, and buzzer output pins.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P140 and P141 function as a 2-bit I/O port. P140 and P141 can be set to input or output in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14).

(2) Control mode

P140 and P141 function as external interrupt request input, clock output, and buzzer output pins.

(a) INTP6, INTP7

These are the external interrupt request input pins for which the valid edge (rising edge, falli ng edge, or both rising and falling edges) can be specified.

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CHAPTER 2 PIN FUNCTIONS

(b) PCL

This is a clock output pin.

This is a buzzer output pin.

2.2.12 AV

REF

This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to EV

DD or VDD

Note

Note Connect port 2 directly to EV

DD when it is used as a digital port.

2.2.13 AV

This is the A/D converter ground potential pin. Even when the A/D conver ter is not used, always use thi s pin with

the same potential as the EV

SS pin or VSS pin.

2.2.14 RESET

This is the active-low system reset input pin.

2.2.15 X1 and X2

These are the pins for connecting a resonator for high-speed system clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.

Remark The X1 and X2 pins of the

PD78F0138HD can be used as on-chip debu g mode setting pins when the

on-chip debug function is used. For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION

(

PD78F0138HD ONLY).

2.2.16 XT1 and XT2

These are the pins for connecting a resonator for subsystem clock. When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.

2.2.17 V

DD and EVDD

VDD is the positive power supply pin for other than ports. EV

DD is the positive power supply pin for ports.

2.2.18 V

SS and EVSS

SS is the ground potential pin for other than ports.

SS is the ground potential pin for ports.

2.2.19 FLMD0 and FLMD1

This is a pin for setting flash memory programming mode. Connect FLMD0 to EV

SS or VSS in the normal operation mode (FLMD1 is not used in the normal operation mode).

In flash memory programming mode, be sure to connect these pins to the flash programmer.

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type.

Table 2-2. Pin I/O Circuit Types (1/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins

P00/TI000

8-A

P01/TI010/TO00

Note

/TI001

/TO01

Note

P02/SO11 P03/SI11 P04/SCK11 P05/SSI11 P06/TI011 P10/SCK10/TxD0 P11/SI10/RxD0 P12/SO10

5-A P13/TxD6 P14/RxD6 8-A P15/TOH0 5-A P16/TOH1/INTP5

8-A P17/TI50/TO50/FLMD1 P20/ANI0 to P27/ANI7 9-C Input Connect to EVDD or EVSS. P30/INTP1

8-A P31/INTP2

(except

PD78F0138HD) P31/INTP2 (µPD78F0138HD) Connect to EVSS via a resistor. P32/INTP3 P33/TI51/TO51/INTP4 P40 to P43

5-A P50 to P53 P60, P61 13-R P62, P63 13-W

P70/KR0 to P77/KR7

8-A P120/INTP0 P130 3-C Output Leave open. P140/PCL/INTP6

8-A I/O Input: Independently connect to EV P141/BUZ/INTP7

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the

78F0136H, 78F0138H, and 78F0138HD.

I/O Input: Independently connect to EV

Output: Leave open.

I/O

Input: Independently connect to EV Output: Leave open.

Input: Connect to EV

SS.

Output: Leave this pin open at low-level output after clearing the output latch of the port to 0.

Input: Independently connect to EV Output: Leave open.

Output: Leave open.

PD78F0133H, 78F0134H,

DD or EVSS via a resistor.

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CHAPTER 2 PIN FUNCTIONS

Table 2-2. Pin I/O Circuit Types (2/2)

Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins RESET 2 Connect to EVDD or VDD. XT1

16 XT2 AVREF Connect directly to EVDD or VDD

−

Input

Connect directly to EVSS or VSS Leave open.

−

Note 1

Note 2

. AVSS Connect directly to EVSS or VSS. FLMD0

Connect to EVSS or VSS.

Notes 1. Bit 6 (FRC) of the processor clock control register (PCC) must be set to 1 after reset mode is released.

2. Connect port 2 directly to EVDD when it is used as a digital port.

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CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuit List (1/2)

Type 2

Type 8-A

Schmitt-triggered input with hysteresis characteristics

Type 3-C

P-ch

Data

OUT

N-ch

Pullup enable

Data

Output disable

Type 9-C

P-ch N-ch

(threshold voltage)

P-ch

IN/OUT

N-ch

Comparator

–

REF

Type 5-A

Pullup enable

Data

Output disable

Input enable

P-ch

N-ch

P-ch

IN/OUT

Type 13-R

Output disable

Data

Input enable

IN/OUT

N-ch

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Type 13-W

CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuit List (2/2)

Type 16

Output disable

Input

enable

Data

N-ch

Middle-voltage input buffer

IN/OUT

Feedback cut-off

P-ch

XT1 XT2

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the 78K0/KE1+ can each access a 64 KB memory space. Figures 3-1 to 3-6 show the memory maps.

Caution Regardless of the internal memory capacity, the initial values of the internal memory size

switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE1+ are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. In addition, set the following values to the IMS and the IXS when using the 78K0/KE1+ to evaluate the program of a mask ROM version of the 78K0/KE1.

Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS)

Flash Memory Version

(78K0/KE1+)

−

PD78F0132H

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H, 78F0138HD µPD780138 CFH

Target Mask ROM Version

(78K0/KE1)

PD780131 42H

PD780132 44H

PD780133 C6H

PD780134 C8H

PD780136 CCH

IMS IXS

0CH

0AH

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Data memory space

CHAPTER 3 CPU ARCHITECTURE

Figure 3-1. Memory Map (µPD78F0132H)

FFF

Special function registers

00F

FFE

0EE

FDE

Internal high-speed RAM

00D

FFC

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

512 × 8 bits

HFFF

Program area

000

1 0

FFF

CALLF entry area

008

HFF7

Program area

180

080

F70

040

F30

000

Option byte area

CALLT table area

Vector table area

Program memory space

Reserved

000

FFF

Flash memory

16384 × 8 bits

Caution When replacing the µPD78F0132H with the µPD78F0138HD, note that the area from 0081H to

0083H in the

PD78F0138HD cannot be used.

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Data memory space

CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD78F0133H)

FFF

Special function registers

00F

FFE

0EE

FDE

Internal high-speed RAM

00B

FFA

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

1024 × 8 bits

HFFF

Program area

000

1 0

FFF

CALLF entry area

008

HFF7

Program area

180

080

F70

040

F30

000

Option byte area

CALLT table area

Vector table area

Program memory space

Reserved

000

FFF

Flash memory

24576 × 8 bits

Caution When replacing the µPD78F0133H with the µPD78F0138HD, note that the area from 0081H to

0083H in the

PD78F0138HD cannot be used.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-3. Memory Map (µPD78F0134H)

FFF

Special function registers

00F

FFE

0EE

FDE

Internal high-speed RAM

00B

FFA

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

1024 × 8 bits

HFFF

Program area

000

1 0

FFF

CALLF entry area

008

HFF7

Program area

180

080

F70

040

F30

000

Option byte area

CALLT table area

Vector table area

Program memory space

Reserved

000

FFF

Flash memory

32768 × 8 bits

Caution When replacing the µPD78F0134H with the µPD78F0138HD, note that the area from 0081H to

0083H in the

PD78F0138HD cannot be used.

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Data memory space

FFFFH

FF00H

FEFFH

FEE0H

FEDFH

FB00H

FAFFH

F800H

F7FFH

RAM space in which instruction can be fetched

F400H

F3FFH

CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Memory Map (µPD78F0136H)

Special function registers

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

Internal expansion RAM

1024 × 8 bits

Reserved

BFFFH

1000H 0FFFH

0800H 07FFH

0081H 0080H

007FH

Program area

CALLF entry area

Program area

Option byte area

CALLT table area

Vector table area

Program memory space

C000H BFFFH

0000H

Flash memory 49152 × 8 bits

0040H

003FH

0000H

Caution When replacing the µPD78F0136H with the µPD78F0138HD, note that the area from 0081H to

0083H in the

PD78F0138HD cannot be used.

User’s Manual U16899EJ2V0UD

Data memory space

FFFFH

FF00H FEFFH

FEE0H FEDFH

FB00H FAFFH

F800H F7FFH

RAM space in which instruction can be fetched

F400H F3FFH

CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Memory Map (µPD78F0138H)

Special function registers

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

Internal expansion RAM

1024 × 8 bits

Reserved

EFFFH

1000H

0FFFH

0800H 07FFH

0081H 0080H 007FH

Program area

CALLF entry area

Program area

Option byte area

CALLT table area

Vector table area

Program memory space

F000H

EFFFH

0000H

Flash memory 61440 × 8 bits

0040H 003FH

0000H

Caution When replacing the µPD78F0138H with the µPD78F0138HD, note that the area from 0081H to

0083H in the

PD78F0138HD cannot be used.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Memory Map (µPD78F0138HD)

FFFFH

FF00H FEFFH

FEE0H FEDFH

Special function registers

Internal high-speed RAM

(SFR)

256 × 8 bits

General-purpose

registers

32 × 8 bits

1024 × 8 bits

Note 1

EFFFH

1000H

0FFFH

0800H 07FFH

0190H 018FH 0084H

0083H 0081H

0080H 007FH

0040H 003FH

0000H

Program area

CALLF entry area

Program area

Note 2

Reserved for option byte

Option byte area

CALLT table area

Vector table area

Data memory space

RAM space in which instruction can be fetched

Program memory space

FB00H FAFFH

Reserved

F800H

F7FFH

Internal expansion RAM

1024 × 8 bits

F400H

F3FFH

Reserved

F000H EFFFH

Flash memory 61440 × 8 bits

Note 2

0000H

Notes 1. During on-chip debugging, 9 bytes of this area are used as the user data backup area for

communication.

2. During on-chip debugging, use of this area is disabled because it is used as the communication command area (0084H to 018FH: debugger’s default setting).

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores the program and table data. Normally, it is addressed with the program

counter (PC).

78K0/KE1+ products incorporate internal ROM (flash memory), as shown below.

Table 3-2. Internal ROM Capacity

Internal ROM Part Number

Structure Capacity

PD78F0132H 16384 × 8 bits (0000H to 3FFFH)

PD78F0133H 24576 × 8 bits (0000H to 5FFFH)

PD78F0134H 32768 × 8 bits (0000H to 7FFFH)

PD78F0136H 49152 × 8 bits (0000H to BFFFH)

PD78F0138H, 78F0138HD

Flash memory

61440 × 8 bits (0000H to EFFFH)

The internal program memory space is divided into the following areas.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses.

Table 3-3. Vector Table

Vector Table Address Interrupt Source Vector Table Address Interrupt Source

0004H INTLVI 0024H INTAD 0006H INTP0 0026H INTSR0

0008H INTP1 0028H INTWTI 000AH INTP2 002AH INTTM51 000CH INTP3 002CH INTKR 000EH INTP4 002EH INTWT

0010H INTP5 0030H INTP6

0012H INTSRE6 0032H INTP7

0014H INTSR6 0034H INTDMU

0016H INTST6 0036H INTCSI11

0018H INTCSI10/INTST0 0038H INTTM001 001AH INTTMH1 003AH INTTM011 001CH INTTMH0 003EH BRK 001EH INTTM50

Note Available only in the

RESET input, POC, LVI, clock monitor, WDT

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

0020H INTTM000 0000H 0022H INTTM010

Note

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CHAPTER 3 CPU ARCHITECTURE

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) Option byte area

The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 24 OPTION BYTE for details.

(4) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

3.1.2 Internal data memory space

78K0/KE1+ products incorporate the following RAMs.

(1) Internal high-speed RAM

Table 3-4. Internal High-Speed RAM Capacity

Part Number Internal High-Speed RAM

PD78F0132H 512 × 8 bits (FD00H to FEFFH)

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H, 78F0138HD

1024 × 8 bits (FB00H to FEFFH)

The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register b anks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory.

(2) Internal expansion RAM

Table 3-5. Internal Expansion RAM Capacity

Part Number Internal Expansion RAM

PD78F0132H

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H, 78F0138HD

1024 × 8 bits (F400H to F7FFH)

−

The internal expansion RAM can also be us ed as a normal data area simi lar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory.

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CHAPTER 3 CPU ARCHITECTURE

3.1.3 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to

Table 3-6 Special Function Register List in 3.2.3 Special function registers (SFRs)).

Caution Do not access addresses to which SFRs are not assigned.

3.1.4 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of

the register or memory relevant to the execution of instructions.

Several addressing modes are provided for addressing the memory relev ant to the executi on of instructions for the 78K0/KE1+, based on operability and other considerations. For areas containing data memory in particular, sp ecial addressing methods designed for the functions of special function registers (SFR) and general- purpose registers are available for use. Figures 3-7 to 3-12 show correspondence b etween data memory and addressing. For details of each addressing mode, refer to 3.4 Operand Address Addressing.

Figure 3-7. Correspondence Between Data Memory and Addressing (

PD78F0132H)

FFF

Special function registers (SFR)

02F

F1F

00F

FFE

General-purpose registers

0EE

FDE

02E

F1E

00D

FFC

256 × 8 bits

32 × 8 bits

Internal high-speed RAM

512 × 8 bits

Reserved

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

000

FFF

Flash memory 16384 × 8 bits

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-8. Correspondence Between Data Memory and Addressing (µPD78F0133H)

FFF

Special function registers (SFR)

02F

F1F

00F

FFE

General-purpose registers

0EE

FDE

02E

F1E

00B

FFA

256 × 8 bits

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

000

FFF

Flash memory 24576 × 8 bits

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-9. Correspondence Between Data Memory and Addressing (µPD78F0134H)

FFF

Special function registers (SFR)

02F

F1F

00F

FFE

General-purpose registers

0EE

FDE

02E

F1E

00B

FFA

256 × 8 bits

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

000

FFF

Flash memory 32768 × 8 bits

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-10. Correspondence Between Data Memory and Addressing (µPD78F0136H)

FFFFH

FF20H FF1FH

FF00H FEFFH

FEE0H FEDFH

FE20H FE1FH FB00H FAFFH

F800H F7FFH

Special function registers (SFR)

256 × 8 bits

General-purpose registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

Internal expansion RAM

1024 × 8 bits

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

F400H F3FFH

C000H BFFFH

0000H

Reserved

Flash memory

49152 × 8 bits

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-11. Correspondence Between Data Memory and Addressing (µPD78F0138H)

FFFFH

FF20H FF1FH

FF00H FEFFH

FEE0H FEDFH

FE20H FE1FH FB00H FAFFH

F800H F7FFH

Special function registers (SFR)

256 × 8 bits

General-purpose registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Reserved

Internal expansion RAM

1024 × 8 bits

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

F400H F3FFH

Reserved

F000H

EFFFH

Flash memory 61440 × 8 bits

0000H

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Figure 3-12. Correspondence Between Data Memory and Addressing (µPD78F0138HD)

FFFFH

FF20H FF1FH

FF00H FEFFH

FEE0H FEDFH

FB00H FAFFH

F800H F7FFH

Special function registers (SFR)

256 × 8 bits

General-purpose registers

32 × 8 bits

Internal high-speed RAM

1024 × 8 bits

Note 1

Reserved

Internal expansion RAM

1024 × 8 bits

SFR addressing

Short direct addressing

Direct addressing Register indirect addressing Based addressing Based indexed addressing

F400H F3FFH

Reserved

F000H EFFFH

Flash memory 61440 × 8 bits

Note 2

0000H

Notes 1. During on-chip debugging, 9 bytes of this area are used as the user data backup area for

communication.

2. During on-chip debugging, use of this area is disabled because it is used as the communication command area (0084H to 018FH: debugger’s default setting).

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CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

The 78K0/KE1+ products incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses and stack memory. The control registers consist of a

program counter (PC), a program status word (PSW) and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented ac cording to th e numbe r of bytes of the i nstruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-13. Format of Program Counter

15 0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H.

Figure 3-14. Format of Program Status Word

7 0

PSW IE Z RBS1 AC RBS0 0 ISP CY

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. Other interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sourc es, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or in terrupt acknowledgement and is set (1) upon EI instruction execution.

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CHAPTER 3 CPU ARCHITECTURE

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored i nterrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag regi ster (PR0L, PR 0H, PR1L, PR 1H ) (refer to 17.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the s hift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area.

Figure 3-15. Format of Stack Pointer

15 0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-16 and 3-17.

Caution Since RESET input makes th e SP contents undefined, be sure to initialize the SP before using

the stack.

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Figure 3-16. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

FEE0H

FEDDH

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

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Figure 3-17. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

(b) RET instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

PC15 to PC8

PC7 to PC0

FEE0H

FEDDH

FEDFH

FEDEH

FEDDH

PSW

PC15 to PC8

PC7 to PC0

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The

general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16- bit register

(AX, BC, DE, and HL).

These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and

absolute names (R0 to R7 and RP0 to RP3).

Register banks to be used for instruction execution are se t by the CPU control instruction (SEL RBn). Beca use of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank.

Figure 3-18. Configuration of General-Purpose Registers

(a) Absolute name

16-bit processing 8-bit processing

FEFFH

FEF8H

FEF0H

FEE8H

FEE0H

BANK0

BANK1

BANK2

BANK3

RP3

RP2

RP1

RP0

15 0 7 0

(b) Function name

16-bit processing 8-bit processing

FEFFH

FEF8H

FEF0H

FEE8H

FEE0H

BANK0

BANK1

BANK2

BANK3

15 0 7 0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special function registers (SFRs)

Unlike a general-purpose register, each special function reg ister has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit

manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address.

• 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address.

• 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address.

Table 3-6 gives a list of the special function registers. The meanings of items in the table are as follows.

• Symbol Symbol indic ating the addr ess of a spec ial function r egister. It is a re served word in the RA78K0, and is defined

as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand.

• R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: Read only W: Write only

• Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.

• After reset Indicates each register status upon RESET input.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Register List (1/4)

FF00H Port register 0 P0 R/W FF01H Port register 1 P1 R/W FF02H Port register 2 P2 R FF03H Port register 3 P3 R/W FF04H Port register 4 P4 R/W FF05H Port register 5 P5 R/W FF06H Port register 6 P6 R/W FF07H Port register 7 P7 R/W FF08H FF09H FF0AH Receive buffer register 6 RXB6 R FF0BH Transmit buffer register 6 TXB6 R/W FF0CH Port register 12 P12 R/W FF0DH Port register 13 P13 R/W FF0EH Port register 14 P14 R/W FF0FH Serial I/O shift register 10 SIO10 R FF10H FF11H FF12H FF13H FF14H FF15H FF16H 8-bit timer counter 50 TM50 R FF17H 8-bit timer compare register 50 CR50 R/W FF18H 8-bit timer H compare register 00 CMP00 R/W FF19H 8-bit timer H compare register 10 CMP10 R/W FF1AH 8-bit timer H compare register 01 CMP01 R/W FF1BH 8-bit timer H compare register 11 CMP11 R/W FF1FH 8-bit timer counter 51 TM51 R FF20H Port mode register 0 PM0 R/W FF21H Port mode register 1 PM1 R/W FF23H Port mode register 3 PM3 R/W FF24H Port mode register 4 PM4 R/W FF25H Port mode register 5 PM5 R/W FF26H Port mode register 6 PM6 R/W FF27H Port mode register 7 PM7 R/W FF28H A/D converter mode register ADM R/W FF29H Analog input channel specification register ADS R/W FF2AH Power-fail comparison mode register PFM R/W FF2BH Power-fail comparison threshold register PFT R/W FF2CH Port mode register 12 PM12 R/W FF2EH Port mode register 14 PM14 R/W

A/D conversion result register ADCR R

16-bit timer counter 00 TM00 R

16-bit timer capture/compare register 000 CR000 R/W

16-bit timer capture/compare register 010 CR010 R/W

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ −

− − √

− √ −

− √ − √ √ − √ √ − √ √ −

− √ −

− − √

− √ −

− √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ − √ √ −

− √ − √ √ − √ √ −

After

Reset

00H 00H

Undefined

00H 00H 00H 00H 00H

Undefined

FFH FFH

00H 00H 00H 00H

0000H

00H 00H 00H 00H 00H 00H

00H FFH FFH FFH FFH FFH FFH FFH

00H

00H FFH FFH

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CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Register List (2/4)

FF30H Pull-up resistor option register 0 PU0 R/W FF31H Pull-up resistor option register 1 PU1 R/W FF33H Pull-up resistor option register 3 PU3 R/W FF34H Pull-up resistor option register 4 PU4 R/W FF35H Pull-up resistor option register 5 PU5 R/W FF37H Pull-up resistor option register 7 PU7 R/W FF38H

Correction address register 0

Note 1

CORAD0 R/W FF39H FF3AH

Correction address register 1

Note 1

CORAD1 R/W FF3BH FF3CH Pull-up resistor option register 12 PU12 R/W FF3EH Pull-up resistor option register 14 PU14 R/W FF40H Clock output sele ction regi ster CKS R/W FF41H 8-bit timer compare register 51 CR51 R/W FF43H 8-bit timer mode control register 51 TMC51 R/W FF48H External interrupt rising edge enable register EGP R/W FF49H External interrupt falling edge enable register EGN R/W FF4AH Serial I/O shift register 11 FF4CH Transmit buffer register 11

Note 2

SIO11 R

Note 2

SOTB11 R/W FF4FH Input switch control register ISC R/W FF50H Asynchronous serial interface operation mode

ASIM6 R/W

FF53H Asynchronous serial interface reception error

ASIS6 R

status register 6

FF55H Asynchronous serial interface transmission

ASIF6 R

status register 6 FF56H Clock selection register 6 CKSR6 R/W FF57H Baud rate generator control register 6 BRGC6 R/W FF58H Asynchronous serial interface control register 6 ASICL6 R/W FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H

Remainder data register 0

Multiplication/division data register A0

Multiplication/division data register B0

SDR0

MDA0L

MDA0H

MDB0

SDR0L SDR0H MDA0LL MDA0LH MDA0HL MDA0HH MDB0L MDB0H

R/W

FF68H Multiplier/divider control register 0 DMUC0 R/W FF69H 8-bit timer H mode register 0 TMHMD0 R/W FF6AH Timer clock selection register 50 TCL50 R/W FF6BH 8-bit timer mode control register 50 TMC50 R/W

Notes 1. µPD78F0136H and 78F0138H only.

PD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD only.

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Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ − √ √ − √ √ − √ √ − √ √ − √ √ −

− − √

√ √ − √ √ − √ √ −

− √ − √ √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ −

− √ −

− √ − √ √ −

− √

− √ √ √ − √ √ −

− √ − √ √ −

√

After

Reset

00H 00H 00H 00H 00H 00H

0000H

00H 00H 00H 00H 00H 00H 00H 00H

Undefined

00H 01H

00H

FFH

16H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H

CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Register List (3/4)

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits FF6CH 8-bit timer H mode register 1 TMHMD1 R/W FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W FF6EH Key return mode register KRM R/W FF6FH Watch timer operation mode register WTM R/W FF70H Asynchronous serial interface operation mode

ASIM0 R/W

√ √ − √ √ − √ √ − √ √ − √ √ −

register 0 FF71H Baud rate generator control register 0 BRGC0 R/W FF72H Receive buffer register 0 RXB0 R FF73H Asynchronous serial interface reception error

ASIS0 R

− √ −

status register 0 FF74H Transmit shift register 0 TXS0 W FF80H Serial operation mode register 10 CSIM10 R/W FF81H Serial clock selection register 10 CSIC10 R/W FF84H Transmit buffer register 10 SOTB10 R/W FF88H Serial operation mode register 11 FF89H Serial clock selection register 11 FF8AH Correction control register

Note 1

CSIM11 R/W

Note 1

CSIC11 R/W

Note 2

CORCN R/W FF8CH Timer clock selection register 51 TCL51 R/W FF98H Watchdog timer mode register WDTM R/W FF99H Watchdog timer enable register WDTE R/W FFA0H Ring-OSC mode register RCM R/W FFA1H Main clock mode register MCM R/W FFA2H Main OSC control register MOC R/W FFA3H Oscillation stabilization time counter status register OSTC R FFA4H Oscillation stabilization time select register OSTS R/W FFA9H Clock monitor mode register CLM R/W FFACH Reset control flag register RESF R FFB0H

16-bit timer counter 01

Note 1

TM01 R

− √ − √ √ − √ √ −

− √ − √ √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ − √ √ − √ √ −

− √ − √ √ −

− √ −

− − √

FFB1H FFB2H

16-bit timer capture/compare register 001

Note 1

CR001 R/W

− − √ FFB3H FFB4H

16-bit timer capture/compare register 011

Note 1

CR011 R/W

− − √ FFB5H FFB6H 16-bit timer mode control register 01 FFB7H Prescaler mode register 01

Note 1

FFB8H Capture/compare control register 01 FFB9H 16-bit timer output control register 01 FFBAH 16-bit timer mode control register 00 TMC00 R/W FFBBH Prescaler mode register 00 PRM00 R/W

Note 1

TMC01 R/W

PRM01 R/W

Note 1

CRC01 R/W

Note 1

TOC01 R/W

√ √ − √ √ − √ √ − √ √ − √ √ − √ √ −

Notes 1. µPD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD only.

PD78F0136H, 78F0138H, and 78F0138HD only.

3 This value varies depending on the reset source.

After

Reset

00H 00H 00H 00H 01H

1FH FFH

00H

FFH

00H 00H

Undefined

00H 00H 00H 00H 67H

9AH

00H 00H 00H 00H 05H 00H

Note 3

00H

0000H

00H 00H 00H 00H 00H 00H

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CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Register List (4/4)

FFBCH Capture/compare control register 00 CRC00 R/W FFBDH 16-bit timer output control register 00 TOC00 R/W FFBEH Low-voltage detection register LVIM R/W FFBFH Low-voltage detection level selection register LVIS R/W FFC0H Flash protect command register PFCMD W FFC2H Flash status register PFS R/W FFC4H Flash programming mode control register FLPMC R/W FFE0H Interrupt request flag register 0L IF0 IF0L R/W FFE1H Interrupt request flag register 0H IF0H R/W FFE2H Interrupt request flag register 1L IF1 IF1L R/W FFE3H Interrupt request flag register 1H IF1H R/W FFE4H Interrupt mask flag register 0L MK0 MK0L R/W FFE5H Interrupt mask flag register 0H MK0H R/W FFE6H Interrupt mask flag register 1L MK1 MK1L R/W FFE7H Interrupt mask flag register 1H MK1H R/W FFE8H Priority specification flag register 0L PR0 PR0L R/W FFE9H Priority specification flag register 0H PR0H R/W FFEAH Priority specification flag register 1L PR1 PR1L R/W FFEBH Priority specification flag register 1H PR1H R/W FFF0H Internal memory size switching register FFF4H Internal expansion RAM size switching register FFFBH Processor clock contr ol register PCC R/W

Note 2

IMS R/W

Note 2

IXS R/W

Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

√ √ − √ √ − √ √ −

− √ −

− √ − √ √ − √ √ − √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √

− √ −

− √ − √ √ −

√

After

Reset

00H 00H 00H 00H

Undefined

00H

Note 1

0XH

00H 00H 00H

00H FFH FFH FFH DFH FFH FFH FFH FFH CFH 0CH

00H

Notes 1. Varies depending on the operation mode.

• User mode: 08H

• On-board mode: 0CH

2. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE1 + are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. In addition, set the following values to the IMS and the IXS when using the 78K0/KE1+ to evaluat e the program of a mask ROM version of the 78K0/KE1.

Flash Memory Version

(78K0/KE1+)

−

PD78F0132H

PD78F0133H

PD78F0134H

PD78F0136H

PD78F0138H, 78F0138HD µPD780138 CFH

Target Mask ROM Version

(78K0/KE1)

PD780131 42H

PD780132 44H

PD780133 C6H

PD780134 C8H

PD780136 CCH

IMS IXS

0CH

0AH

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents and is n ormally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction i s executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displac ement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the −128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15 0

876

PC indicates the start address

...

of the instruction after the BR instruction.

15 0

When S = 0, all bits of are 0. When S = 1, all bits of are 1.

α α

jdisp8

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

CALL or BR

Low Addr.

High Addr.

15 0

In the case of CALLF !addr11 instruction

15 0

00001

643

10–8

CALLF

7–0

11 10

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CHAPTER 3 CPU ARCHITECTURE

3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, a nd allows branching to the entire memory space.

[Illustration]

765 10

Operation code

4–0

111

Effective address

Effective address+1

15 1

00000000

Memory (Table)

Low Addr.

High Addr.

15 0

65 0

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed.

[Illustration]

15 0

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) to undergo manipulation

during instruction execution.

3.4.1 Implied addressing

[Function]

The register that functions as an accumulator (A and AX) among the general-purpose registers is auto matically (implicitly) addressed. Of the 78K0/KE1+ instruction words, the following instructions employ implied addressing.

Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets ROR4/ROL4 A register for storage of digit data that undergoes digit rotation

[Operand format]

Because implied addressing can be automatically em ployed with an instruction, no particular opera nd format is necessary.

[Description example]

In the case of MULU X With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Register addressing

[Function]

The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following opera nd format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL

‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as we ll as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; when selecting C register as r

Operation code 0 1100010

INCW DE; when selecting DE register pair as rp

Operation code 1 0000100

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Direct addressing

[Function]

The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address.

[Operand format]

Identifier Description

addr16 Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code 10001110 OP code

00000000 00H

11111110 FEH

[Illustration]

OP code

addr16 (lower)

addr16 (upper)

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and ca pture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration] shown below.

[Operand format]

Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)

[Description example]

MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)

Operation code 1 1110010 OP code

0 0110000 30H (saddr-offset)

[Illustration]

OP code

saddr-offset

Effective address

111111

When 8-bit immediate data is 20H to FFH, When 8-bit immediate data is 00H to 1FH,

= 0

= 1

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Short direct memory

CHAPTER 3 CPU ARCHITECTURE

3.4.5 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier Description sfr Special function register name sfrp

16-bit manipulatable special function register name (even address only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code 11110110 OP code

00100000 20H (sfr-offset)

[Illustration]

Effective address

OP code sfr-offset

111111

SFR

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Register indirect addressing

[Function]

Register pair contents specified by a register pair specify code in an instruction wor d and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can b e carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

Operation code 10000101

[Illustration]

16 0

The contents of the memory addressed are transferred.

7 0

Memory

The memory address

specified with the register pair DE

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CHAPTER 3 CPU ARCHITECTURE

3.4.7 Based addressing

[Function]

8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to addre ss the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A car ry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[HL + byte]

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

Operation code 10101110

00010000

[Illustration]

16 08H7

The contents of the memory addressed are transferred.

7 0

Memory

+10

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CHAPTER 3 CPU ARCHITECTURE

3.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to t he contents of the bas e register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by ex panding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier Description

−

[HL + B], [HL + C]

[Description example]

In the case of MOV A, [HL + B] (selecting B register)

Operation code 10101011

[Illustration]

16 0

The contents of the memory addressed are transferred.

7 0

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.

[Description example]

In the case of PUSH DE (saving DE register)

Operation code 10110101

[Illustration]

Memory 07

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

There are two types of pin I/O buffer power supplies: AV

supplies and the pins is shown below.

Table 4-1. Pin I/O Buffer Power Supplies

Power Supply Corresponding Pins AVREF P20 to P27 EVDD Port pins other than P20 to P27

78K0/KE1+ products are provided with the ports shown in Figure 4-1, which enable variety of control operations .

The functions of each port are shown in Table 4-2.

In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the

alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

REF and EVDD. The relationship between these power

Port 5

Port 6

Port 7

Port 12 Port 13

Port 14

P50

P53 P60

P63 P70

P77 P120 P130 P140

P141

P00

Port 0

P06 P10

Port 1

P17

P20

Port 2

P27 P30

Port 3

P33

P40

Port 4

P43

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CHAPTER 4 PORT FUNCTIONS

Table 4-2. Port Functions (1/2)

Pin Name I/O Function After Reset Alternate Function

P00 TI000

I/O P01 TI010/TO00 P02 SO11 P03 SI11 P04 SCK11 P05 SSI11 P06 P10 SCK10/TxD0

I/O P11 SI10/RxD0 P12 SO10 P13 TxD6

Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Input

TI011

Note

/TI001

/TO01

P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 P20 to P27 Input

Port 2.

Input ANI0 to ANI7

TI50/TO50/FLMD1

8-bit input-only port.

P30 to P32 INTP1 to INTP3

I/O

Port 3.

Input 4-bit I/O port. Input/output can be specified in 1-bit units.

P33

Use of an on-chip pull-up resistor can be specified by a

INTP4/TI51/TO51

software setting.

P40 to P43 I/O

Port 4.

Input

− 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

P50 to P53 I/O

Port 5.

Input

− 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

P60 to P63 I/O

Port 6.

Input

− 4-bit I/O port (N-ch open drain). Input/output can be specified in 1-bit units.

P70 to P77 I/O

Port 7.

Input KR0 to KR7 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Note SO11, SI11, SCK11, SSI11, TI001, TI011, and TO01 are available only in the

PD78F0133H, 78F0134H,

78F0136H, 78F0138H, and 78F0138HD.

Note

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Table 4-2. Port Functions (2/2)

Pin Name I/O Function After Reset Alternate Function

P120 I/O

P130 Output

P140 PCL/INTP6 P141

I/O

Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting.

Port 13. 1-bit output-only port.

Port 14. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.

Input INTP0

Output

Input

BUZ/INTP7

4.2 Port Configuration

Ports include the following hardware.

Table 4-3. Port Configuration

−

Item Configuration

Control registers

Port Total: 51 (CMOS I/O: 38, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor Total: 38

Port mode register (PM0, PM1, PM3 to PM7, PM12, PM14) Port register (P0 to P7, P12 to P14) Pull-up resistor option register (PU0, PU1, PU3 to PU5, PU7, PU12, PU14)

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.1 Port 0

Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).

This port can also be used for timer I/O, serial interface data I/O, and clock I/O.

RESET input sets port 0 to input mode.

Figures 4-2 to 4-5 show block diagrams of port 0.

Caution When P02/SO11

Note

, P03/SI11

Note

, and P04/SCK11

Note

are used as general-purpose ports, do not

write to serial clock selection register 11 (CSIC11).

Figure 4-2. Block Diagram of P00, P03, and P05

PU0

PORT

Internal bus

PU00, PU03, PU05

Alternate function

Selector

Output latch

(P00, P03, P05)

PM0

PM00, PM03, PM05

P-ch

Note Available only in the µPD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal

P00/TI000, P03/SI11 P05/SSI11

Note

/TI001

Note

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-3. Block Diagram of P01 and P06

PU0

PU01, PU06

P-ch

Alternate

function

Selector

PORT

Internal bus

Output latch

(P01, P06)

PM0

PM01, PM06

Alternate

function

Note Available only in the µPD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal

P01/TI010/TO00, P06/TI011

Note

/TO01

Note

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-4. Block Diagram of P02

PU0

PU02

Selector

PORT

Output latch

Internal bus

(P02)

PM0

PM02

Alternate

function

Note Available only in the µPD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal

P-ch

P02/SO11

Note

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P04

PU0

PU04

Alternate

function

Selector

PORT

Internal bus

Output latch

(P04)

PM0

PM04

Alternate

function

Note Available only in the µPD78F0133H, 78F0134H, 78F0136H, 78F0138H, and 78F0138HD.

PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal

P-ch

P04/SCK11

Note

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).

This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, timer I/O, and flash memory programming mode setting.

RESET input sets port 1 to input mode.

Figures 4-6 to 4-10 show block diagrams of port 1.

Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not

write to serial clock selection register 10 (CSIC10).

Figure 4-6. Block Diagram of P10

PU1

Internal bus

PU10

Alternate

function

PORT

Output latch

(P10)

PM1

PM10

Alternate

function

PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal

P-ch

Selector

P10/SCK10/TxD0

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-7. Block Diagram of P11 and P14

PU1

PU11, PU14

Alternate

function

Internal bus

PORT

Output latch

(P11, P14)

PM1

PM11, PM14

PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal

P-ch

Selector

P11/SI10/RxD0, P14/RxD6

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-8. Block Diagram of P12 and P15

PU1

PU12, PU15

PORT

Output latch

Internal bus

(P12, P15)

PM1

PM12, PM15

Alternate

function

PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal

P-ch

Selector

P12/SO10 P15/TOH0

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-9. Block Diagram of P13

EVDD

PU1

PU13

PORT

Internal bus

WRPM

Output latch

(P13)

PM1

PM13

Alternate

function

PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal

P-ch

Selector

P13/TxD6

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-10. Block Diagram of P16 and P17

PU1

Internal bus

PU16, PU17

Alternate

function

PORT

Output latch

(P16, P17)

PM1

PM16, PM17

Alternate

function

PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal

P-ch

Selector

P16/TOH1/INTP5, P17/TI50/TO50/FLMD1

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

Port 2 is an 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2.

Figure 4-11. Block Diagram of P20 to P27

A/D converter

Internal bus

P20/ANI0 to P27/ANI7

RD: Read signal

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 3

Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input por t, use of an on-chip pull-up resistor c an be specified in 1-bit units by pull-up resistor option register 3 (PU3).

This port can also be used for external interrupt request input and timer I/O.

RESET input sets port 3 to input mode.

Figures 4-12 and 4-13 show block diagrams of port 3.

Caution In the

PD78F0138HD, be sure to pull the P31 pin down after reset to prevent malfunction.

Remark P31/INTP2 and P32/INTP3 of the

PD78F0138HD can be used for on-chip debug mod e setting when

the on-chip debug function is used. For details, refer to CHAPTER 27 ON-CHIP DEBUG FUNCTION

(

PD78F0138HD ONLY).

Figure 4-12. Block Diagram of P30 to P32

PU3

PU30 to PU32

Alternate

function

Internal bus

PORT

Output latch

(P30 to P32)

PM3

PM30 to PM32

PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal

P-ch

Selector

P30/INTP1 to P32/INTP3

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

Figure 4-13. Block Diagram of P33

PU3

Internal bus

PU33

Alternate

function

PORT

Output latch

(P33)

PM3

PM33

Alternate

function

PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal

P-ch

Selector

P33/INTP4/TI51/TO51

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.5 Port 4

Port 4 is a 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4).

RESET input sets port 4 to input mode.

Figure 4-14 shows a block diagram of port 4.

Figure 4-14. Block Diagram of P40 to P43

PU4

PORT

Internal bus

PU40 to PU43

Selector

Output latch

(P40 to P43)

PM4

PM40 to PM43

P-ch

P40 to P43

PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.6 Port 5

Port 5 is a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up resistor can be specified in 1-bit units using pull-up resistor option register 5 (PU5).

RESET input sets port 5 to input mode.

Figure 4-15 shows a block diagram of port 5.

Figure 4-15. Block Diagram of P50 to P53

PORT

Internal bus

PU5

PU50 to PU53

Output latch

(P50 to P53)

PM5

P-ch

Selector

P50 to P53

PM50 to PM53

PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WR××: Write signal

User’s Manual U16899EJ2V0UD

CHAPTER 4 PORT FUNCTIONS

4.2.7 Port 6

Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units

using port mode register 6 (PM6).

The P60 to P63 pins are N-ch open-drain pins. RESET input sets port 6 to input mode. Figure 4-16 shows a block diagram of port 6.

Figure 4-16. Block Diagram of P60 to P63

Selector

PORT

Internal bus

Output latch

(P60 to P63)

PM6

PM60 to PM63

P60 to P63

PM6: Port mode register 6 RD: Read signal WR××: Write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.8 Port 7

Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).

This port can also be used for key return input.

RESET input sets port 7 to input mode.

Figure 4-17 shows a block diagram of port 7.

Figure 4-17. Block Diagram of P70 to P77

PU7

PU70 to PU77

Alternate function

PORT

Internal bus

Output latch

(P70 to P77)

PM7

PM70 to PM77

PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WR××: Write signal

P-ch

Selector

P70/KR0 to P77/KR7

100

User’s Manual U16899EJ2V0UD

NEC MuPD78F0132H, MuPD78F0138H, MuPD78F0136H, MuPD78F0134H, MuPD78F0138HD User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

INTRODUCTION

CHAPTER 1 OUTLINE

1.1 Features

1.2 Applications

1.3 Ordering Information

1.4 Pin Configuration (Top View)

1.5 Kx1 Series Lineup

1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup

1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup

1.6 Block Diagram

1.7 Outline of Functions

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

2.2 Description of Pin Functions

2.2.1 P00 to P06 (port 0)

2.2.2 P10 to P17 (port 1)

2.2.3 P20 to P27 (port 2)

2.2.4 P30 to P33 (port 3)

2.2.5 P40 to P43 (port 4)

2.2.6 P50 to P53 (port 5)

2.2.7 P60 to P63 (port 6)

2.2.8 P70 to P77 (port 7)

2.2.9 P120 (port 12)

2.2.10 P130 (port 13)

2.2.11 P140 and P141 (port 14)

2.2.15 X1 and X2

2.2.16 XT1 and XT2

2.2.19 FLMD0 and FLMD1

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

3.1.1 Internal program memory space

3.1.2 Internal data memory space

3.1.3 Special function register (SFR) area

3.1.4 Data memory addressing

3.2 Processor Registers

3.2.1 Control registers

3.2.2 General-purpose registers

3.2.3 Special function registers (SFRs)

3.3 Instruction Address Addressing

3.3.1 Relative addressing

3.3.2 Immediate addressing

3.3.3 Table indirect addressing

3.3.4 Register addressing

3.4 Operand Address Addressing

3.4.1 Implied addressing

3.4.2 Register addressing

3.4.3 Direct addressing

3.4.4 Short direct addressing

3.4.5 Special function register (SFR) addressing

3.4.6 Register indirect addressing

3.4.7 Based addressing

3.4.8 Based indexed addressing

3.4.9 Stack addressing

CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

4.2 Port Configuration

4.2.1 Port 0

4.2.2 Port 1

4.2.3 Port 2

4.2.4 Port 3

4.2.5 Port 4

4.2.6 Port 5

4.2.7 Port 6

4.2.8 Port 7