NEC V850E/PH2, MuPD70F3187 User Manual

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User’s Manual

V850E/PH2

32-Bit Single-Chip Microcontroller

Hardware

μPD70F3187 μPD70F3447

Document No. U16580EE3V1UD00 Date Published January 2007

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V V

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(MAX) and VIH (MIN) due to noise, etc., the device may

(MAX) and

or GND

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office.

User’s Manual U16580EE3V1UD00

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The information in this document is current as of October, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.

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No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

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NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative

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purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

•

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.

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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.

"Standard":

"Special":

"Specific":

Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.

(Note) (1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).

M8E 02. 11-1

User’s Manual U16580EE3V1UD00

For further information,

please contact:

NEC Electronics Corporation

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User’s Manual U16580EE3V1UD00

Preface

Readers This manual is intended for users who want to understand the functions of the

V850E/PH2 (PHOENIX-F).

Purpose This manual presents the hardware manual of V850E/PH2.

Organization This system specification describes the following sections:

• Pin function

• CPU function

• Internal peripheral function

• Flash memory

Legend Symbols and notation are used as follows:

Weight in data notation : Left is high-order column, right is low order column

Active low notation : xxx

(pin or signal name is over-scored) or

/xxx (slash before signal name)

Memory map address: : High order at high stage and low order at low stage

Note : Explanation of (Note) in the text

Caution : Item deserving extra attention

Remark : Supplementary explanation to the text

Numeric notation : Binary... Decimal...

XXXX or XXXB

XXXX

Hexadecimal... XXXXH or 0x XXXX

Prefixes representing powers of 2 (address space, memory capacity)

K (kilo): 2

M (mega): 2 G (giga): 2

= 1024

= 10242 = 1,048,576

= 10243 = 1,073,741,824

User’s Manual U16580EE3V1UD00

Preface

User’s Manual U16580EE3V1UD00

Table of Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.1 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.2 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.5 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.6 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.6.1 Internal block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.6.2 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.2 Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.4 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 76

2.5 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Chapter 3 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.2.3 Floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.1 Operating modes outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.4.2 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3.4.4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.4.5 Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.4.6 Peripheral I/O registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.4.7 Programmable peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.4.8 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.4.9 System wait control register (VSWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) . . . . . . . . . . . . . . . 142

3.4.11 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Chapter 4 Bus Control Function (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.2 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

4.3.1 Chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.4 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

4.4.1 Bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

4.5 Bus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

4.5.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.5.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

4.5.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

4.5.4 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.6 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

4.6.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

User’s Manual U16580EE3V1UD00

4.7 Idle State Insertion Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

4.8 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.9 Boundary Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Chapter 5 Memory Access Control Function (μPD70F3187 only). . . . . . . . . . . . . . . 181

5.1 SRAM, External ROM, External I/O Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

5.1.2 SRAM connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

6.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

6.3 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

6.4 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) . . . . . . . . . . . . 200

6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) . . . . . . . . . . . . . . . . . . . . . 204

6.4.3 DMA transfer of serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.4.4 Forcible termination of DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6.5 DMA Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Chapter 7 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 219

7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

7.2 Non-maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

7.2.3 Non-maskable interrupt status flag (NP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.2.4 Edge Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

7.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

7.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

7.3.4 Interrupt control register (PICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) . . . . . . . . . . . . . . . . . . . . . . . . 240

7.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

7.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

7.3.8 Interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

7.4 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

7.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

7.4.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

7.4.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

7.5 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.5.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

7.6 Periods in Which CPU Does Not Acknowledge Interrupts. . . . . . . . . . . . . . . . . . . . 254

Chapter 8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

8.3 Power Save Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

8.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

8.3.2 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Chapter 9 16-Bit Timer/Event Counter P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

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9.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

9.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

9.5.1 Anytime rewrite and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) . . . . . . . . . . . . . . . . . . . . . 279

9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) . . . . . . . . . . . . . . . 282

9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) . . . . . . . . . 286

9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) . . . . . . . . . . . . . . . . . . . 289

9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) . . . . . . . . . . . . . . . . . . . . . 297

9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) . . . . . . . . . . . 304

9.5.9 Counter synchronous operation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

10.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

10.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

10.4 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

10.4.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

10.4.2 Compare register rewrite operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

10.4.3 List of outputs in each mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

10.5 Match Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

10.5.1 Compare match interrupt related cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

10.6 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

10.6.1 Up count flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

10.6.2 Normal phase/inverted phase simultaneous active detection flag . . . . . . . . . . 369

10.6.3 Reload hold flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

10.7 Interrupt Thinning Out Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

10.7.1 Operation of interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

10.7.2 Operation examples when peak interrupts and valley interrupts occur alternately 374

10.7.3 Interrupt thinning out function during counter saw tooth wave operation . . . . . 375

10.8 A/D Conversion Trigger Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

10.8.1 A/D conversion trigger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

10.9 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380

10.9.1 Error interrupt and error signal output functions . . . . . . . . . . . . . . . . . . . . . . . . 380

10.10 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

10.10.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

10.10.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

10.10.3 External trigger pulse output mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . 394

10.10.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

10.10.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

10.10.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

10.10.7 Pulse width measurement mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . . . 415

10.10.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

10.10.9 High-accuracy T-PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

10.10.10 PWM mode with dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

Chapter 11 16-bit Timer/Event Counter T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

11.2 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458

11.4 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

11.5 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

11.5.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

11.5.2 Method for writing to compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

11.6 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

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11.6.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

11.6.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490

11.6.3 External trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

11.6.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

11.6.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

11.6.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

11.6.7 Pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

11.6.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

11.6.9 Encoder count function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

11.6.10 Offset trigger generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose

Timer (TMENC10) (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

12.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

12.3 Basic Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

12.4 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

12.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

12.5.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

12.5.2 Operation in general-purpose timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

12.5.3 Operation in UDC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

12.6 Supplementary Description of Internal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 566

12.6.1 Clearing of count value in UDC mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

12.6.2 Clearing of count value upon occurrence of compare match . . . . . . . . . . . . . . 567

12.6.3 Transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

12.6.4 Interrupt signal output upon compare match . . . . . . . . . . . . . . . . . . . . . . . . . . 568

12.6.5 TM1UBD flag (bit 0 of STATUS register) operation . . . . . . . . . . . . . . . . . . . . . 568

Chapter 13 Auxiliary Frequency Output Function (AFO) . . . . . . . . . . . . . . . . . . . . . . . 569

13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

13.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569

13.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

13.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.4.1 Auxiliary frequency output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.4.2 Auxiliary frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.4.3 Interval timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Chapter 14 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

14.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574

14.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

14.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

14.4.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

14.4.2 Operation mode and trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

14.5 Operation in A/D Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

14.5.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

14.5.2 Scan mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

14.6 Operation in Timer Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

14.6.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

14.6.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

14.7 Operation in External Trigger Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

14.7.1 Select mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

14.7.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

14.8 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

Chapter 15 Asynchronous Serial Interface C (UARTC) . . . . . . . . . . . . . . . . . . . . . . . . 609

15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

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15.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

15.4 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

15.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

15.5.1 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

15.5.2 SBF transmission/reception format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

15.5.3 SBF transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630

15.5.4 SBF receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

15.5.5 UART transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

15.5.6 Continuous transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

15.5.7 UART receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

15.5.8 Receive error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

15.5.9 Parity types and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

15.5.10 Receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

15.6 Dedicated Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

15.6.1 Baud rate generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

15.6.2 Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

15.6.3 Baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

15.6.4 Baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

15.6.5 Allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

15.6.6 Baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

Chapter 16 Clocked Serial Interface B (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

16.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645

16.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

16.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

16.4.1 Single transfer mode (master mode, transmission/reception mode) . . . . . . . . 655

16.4.2 Single transfer mode (master mode, transmission mode) . . . . . . . . . . . . . . . . 656

16.4.3 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 657

16.4.4 Continuous mode (master mode, transmission/reception mode) . . . . . . . . . . . 658

16.4.5 Continuous mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . 659

16.4.6 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 660

16.4.7 Continuous reception mode (error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

16.4.8 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . . . . 662

16.4.9 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . 663

16.4.10 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

16.5 Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666

16.6 Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

16.7 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

16.7.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

16.7.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

16.7.3 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

16.8 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

Chapter 17 Clocked Serial Interface 3 (CSI3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

17.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .678

17.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680

17.4 Dedicated Baud Rate Generator 3n (BRG3n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

17.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

17.5.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

17.5.2 Function of CSI data buffer register (CSIBUFn) . . . . . . . . . . . . . . . . . . . . . . . . 696

17.5.3 Data transfer direction specification function . . . . . . . . . . . . . . . . . . . . . . . . . . 697

17.5.4 Transfer data length changing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

17.5.5 Function to select serial clock and data phase . . . . . . . . . . . . . . . . . . . . . . . . . 700

17.5.6 Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

17.5.7 Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

17.5.8 Transfer clock selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

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17.5.9 Single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

17.5.10 Consecutive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

17.5.11 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

17.5.12 Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

17.5.13 Transmission/reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707

17.5.14 Delay control of transmission/reception completion interrupt (INTC3n) . . . . . . 708

17.5.15 Transfer wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

17.5.16 Output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

17.5.17 CSIBUFn overflow interrupt signal (INTC3nOVF) . . . . . . . . . . . . . . . . . . . . . . 713

17.6 Operating Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

17.6.1 Single mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . 714

17.6.2 Single mode (master mode, reception mode). . . . . . . . . . . . . . . . . . . . . . . . . . 716

17.6.3 Single mode (master mode, transmission/reception mode) . . . . . . . . . . . . . . . 718

17.6.4 Single mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . . 720

17.6.5 Single mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

17.6.6 Single mode (slave mode, transmission/reception mode) . . . . . . . . . . . . . . . . 724

17.6.7 Consecutive mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . 726

17.6.8 Consecutive mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 728

17.6.9 Consecutive mode (master mode, transmission/reception mode) . . . . . . . . . . 730

17.6.10 Consecutive mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . 732

17.6.11 Consecutive mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . 734

17.6.12 Consecutive mode (in slave mode and transmission/reception mode) . . . . . . 736

17.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

Chapter 18 AFCAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

18.1.1 Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

18.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

18.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .742

18.2.1 Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

18.2.2 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

18.2.3 Data frame and remote frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

18.2.4 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750

18.2.5 Overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

18.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

18.3.1 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

18.3.2 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

18.3.3 Multi masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

18.3.4 Multi cast. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

18.3.5 CAN sleep mode/CAN stop mode function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

18.3.6 Error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

18.3.7 Baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

18.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

18.5 Internal Registers of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

18.5.1 CAN module register and message buffer addresses . . . . . . . . . . . . . . . . . . . 764

18.5.2 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

18.5.3 CAN registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

18.5.4 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

18.6 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

18.7 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

18.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

18.8.1 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

18.8.2 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

18.8.3 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

18.8.4 Transition from Initialization Mode to Operation Mode . . . . . . . . . . . . . . . . . . . 808

18.8.5 Resetting error counter CnERC of CAN module . . . . . . . . . . . . . . . . . . . . . . . 809

18.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

18.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

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18.9.2 Receive Data Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

18.9.3 Receive history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

18.9.4 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

18.9.5 Multi buffer receive block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

18.9.6 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

18.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

18.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

18.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

18.10.3 Automatic block transmission (ABT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

18.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

18.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

18.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

18.11.1 CAN sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

18.11.2 CAN stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

18.11.3 Example of using power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

18.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

18.13 Diagnosis Functions and Special Operational Modes . . . . . . . . . . . . . . . . . . . . . . . 828

18.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

18.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

18.13.3 Self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

18.13.4 Receive/Transmit Operation in Each Operation Mode . . . . . . . . . . . . . . . . . . . 830

18.14 Time Stamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

18.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831

18.15 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

18.15.1 Baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

18.15.2 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . 836

18.16 Operation of CAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

Chapter 19 Random Number Generator (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . 865

19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

19.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .865

19.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

19.3.1 Access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

Chapter 20 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867

20.2 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

20.2.1 Function of each port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

20.2.2 Port types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870

20.2.3 Peripheral registers of I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893

20.2.4 Peripheral registers of valid edge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896

20.3 Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

20.3.1 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

20.3.2 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

20.3.3 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902

20.3.4 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906

20.3.5 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

20.3.6 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

20.3.7 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

20.3.8 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

20.3.9 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

20.3.10 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

20.3.11 Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936

20.3.12 Port AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

20.3.13 Port AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

20.3.14 Port DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945

20.3.15 Port DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949

20.3.16 Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953

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20.3.17 Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

20.3.18 Port CM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958

20.3.19 Port CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961

20.4 Noise Elimination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

Chapter 21 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971

21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971

21.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .971

21.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972

Chapter 22 Internal RAM Parity Check Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

22.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

22.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974

Chapter 23 On-Chip Debug Function (OCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

23.1 Function Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

23.1.1 On-chip debug unit type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

23.1.2 Debug function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977

23.2 Connection with N-Wire Type Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

23.2.1 KEL connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

23.3 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983

Chapter 24 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

24.2 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986

24.3 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

24.4 Rewriting by Dedicated Flash Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

24.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

24.4.2 Communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

24.4.3 Flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

24.4.4 Selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

24.4.5 Communication commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997

24.4.6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998

24.5 Rewriting by Self Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

24.5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

24.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004

Chapter 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

25.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007

25.2 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008

25.2.1 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008

25.2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008

25.2.3 Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009

25.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010

25.4 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011

25.4.1 External asynchronous memory access read timing . . . . . . . . . . . . . . . . . . . 1012

25.4.2 External asynchronous memory access write timing . . . . . . . . . . . . . . . . . . . 1014

25.4.3 Reset Timing (Power Up/Down Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

25.4.4 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

25.5 Peripheral Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

25.5.1 Timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

25.5.2 Serial interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021

25.5.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030

25.6 Flash Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031

Chapter 26 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033

User’s Manual U16580EE3V1UD00

Chapter 27 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035

Appendix A Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037

Appendix B Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

User’s Manual U16580EE3V1UD00

List of Figures

Figure 1-1: Pin Configuration 208-pin Plastic LQFP ...................................................................... 37

Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 × 21) ........................................................ 38

Figure 1-3: Internal Block Diagram of mPD70F3187 ..................................................................... 44

Figure 1-4: Internal Block Diagram of mPD70F3447 ..................................................................... 45

Figure 2-1: Pin I/O Circuits ............................................................................................................ 80

Figure 2-2: Noise Removal Time Control Register (1/2) .............................................................. 82

Figure 3-1: CPU Register Set ........................................................................................................ 86

Figure 3-2: Program Counter (PC) ............................................................................................... 87

Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW) ..................................................... 89

Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW) .......................................................... 90

Figure 3-5: Interrupt Source Register (ECR) ............................................................................... 90

Figure 3-6: Program Status Word (PSW) .................................................................................... 91

Figure 3-7: CALLT Execution Status Saving Registers (CTPC, CTPSW) .................................... 92

Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) ............................ 93

Figure 3-9: CALLT Base Pointer (CTBP) ...................................................................................... 93

Figure 3-10: Floating Point Arithmetic Control Register (ECT) ....................................................... 94

Figure 3-11: Floating Point Arithmetic Status Register (EFG) ........................................................ 95

Figure 3-12: CPU Address Space ...................................................................................................98

Figure 3-13: Address Space Image .................................................................................................99

Figure 3-14: Program Space ......................................................................................................... 100

Figure 3-15: Data Space................................................................................................................ 100

Figure 3-16: Memory Map of μPD70F3187 ................................................................................... 101

Figure 3-17: Memory Map of μPD70F3447 ................................................................................... 102

Figure 3-18: Internal ROM / Internal Flash Memory Area of μPD70F3187 ................................... 103

Figure 3-19: Internal ROM / Internal Flash Memory Area of μPD70F3447 .................................. 104

Figure 3-20: Internal RAM Area of μPD70F3187........................................................................... 105

Figure 3-21: Internal RAM Area of μPD70F3447........................................................................... 105

Figure 3-22: On-Chip Peripheral I/O Area ..................................................................................... 106

Figure 3-23: Programmable Peripheral I/O Area (Outline) ............................................................ 121

Figure 3-24: Programmable Peripheral Area Control Register BPC ............................................. 122

Figure 3-25: Processor Command Register (PRCMD).................................................................. 140

Figure 3-26: System Status Register Format PHS ...................................................................... 141

Figure 4-1: Memory Block Function ............................................................................................. 146

Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2) ......................................................... 147

Figure 4-3: Bus Cycle Configuration Registers 0, 1 (BCT0, BCT1) ........................................... 150

Figure 4-4: Bus Size Configuration Register (BSC) .................................................................... 152

Figure 4-5: Big Endian Addresses within Word ........................................................................... 153

Figure 4-6: Little Endian Addresses within Word......................................................................... 153

Figure 4-7: Endian Configuration Register (BEC) ....................................................................... 154

Figure 4-8: Data Wait Control Registers 0, 1 (DWC0, DWC1) Format ..................................... 174

Figure 4-9: Address Wait Control Register (AWC) ..................................................................... 175

Figure 4-10: Bus Cycle Control Register (BCC) ........................................................................... 177

Figure 4-11: Bus Clock Dividing Control Register (DVC) .............................................................. 178

Figure 5-1: Examples of Connection to SRAM (1/2).................................................................... 182

Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/8).......................................... 184

Figure 6-1: DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to MAR7) ................ 194

Figure 6-2: DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3) ............................. 195

Figure 6-3: DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7) ...................................... 196

Figure 6-4: DMA Mode Control Register (DMAMC) .................................................................... 197

Figure 6-5: DMA Status Register (DMAS) .................................................................................. 197

Figure 6-6: DMA Data Size Control Register (DMDSC) ............................................................. 198

Figure 6-7: DMA Trigger Factor Registers 4 to 7 (DTFR4 to DTFR7) ........................................ 199

Figure 6-8: Initialization of DMA Transfer for A/D Conversion Result.......................................... 201

Figure 6-9: Operation of DMA Channel 0/1 ................................................................................. 202

Figure 6-10: DMA Channel 0 and 1 Trigger Signal Timing ............................................................ 203

Figure 6-11: Initialization of DMA Transfer for TMRn Compare Registers .................................... 205

User’s Manual U16580EE3V1UD00

Figure 6-12: Operation of DMA Channel 2/3 ................................................................................. 206

Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing ............................................................ 207

Figure 6-14: Initialization of DMA Transfer for Serial Data Reception ........................................... 209

Figure 6-15: Operation of DMA Channel 4/5 ................................................................................. 210

Figure 6-16: DMA Channel 4 and 5 Trigger Signal Timing ............................................................ 211

Figure 6-17: Initialization of DMA Transfer for Serial Data Transmission ...................................... 213

Figure 6-18: DMA Channel 6 and 7 Trigger Signal Timing ............................................................ 214

Figure 6-19: Operation of DMA Channel 6/7 ................................................................................. 215

Figure 6-20: CPU and DMA Controller Processing of DMA Transfer Termination (Example)....... 216

Figure 6-21: Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts 218

Figure 7-1: Processing Configuration of Non-Maskable Interrupt................................................ 225

Figure 7-2: Acknowledging Non-Maskable Interrupt Request ..................................................... 226

Figure 7-3: RETI Instruction Processing...................................................................................... 227

Figure 7-4: Non-maskable Interrupt Status Flag (NP) ................................................................ 228

Figure 7-5: NMI Edge Detection Specification: Interrupt Mode Register 0 (INTM0) .................. 228

Figure 7-6: Maskable Interrupt Processing .................................................................................. 230

Figure 7-7: RETI Instruction Processing...................................................................................... 231

Figure 7-8: Example of Processing in which Another Interrupt Request Is Issued

while an Interrupt is being Processed (1/2) ............................................................... 233

Figure 7-9: Example of Processing Interrupt Requests Simultaneously Generated.................... 235

Figure 7-10: Interrupt Control Register (PICn) .............................................................................. 236

Figure 7-11: Interrupt Mask Registers 0 to 2 (IMR0 to IMR2) ....................................................... 240

Figure 7-12: Interrupt Mask Registers 3 to 6 (IMR3 to IMR6) ....................................................... 241

Figure 7-13: Interrupt Service Priority Register (ISPR) ................................................................. 242

Figure 7-14: Maskable interrupt status flag (ID) ............................................................................ 243

Figure 7-15: Interrupt Mode Register 0 (INTM0) .......................................................................... 245

Figure 7-16: Interrupt Mode Register 1 (INTM1) .......................................................................... 246

Figure 7-17: Interrupt Mode Register 2 (INTM2) .......................................................................... 247

Figure 7-18: Interrupt Mode Register 3 (INTM3) .......................................................................... 248

Figure 7-19: Software Exception Processing................................................................................. 249

Figure 7-20: RETI Instruction Processing ...................................................................................... 250

Figure 7-21: Exception Status Flag (EP) ...................................................................................... 251

Figure 7-22: Illegal Opcode............................................................................................................ 252

Figure 7-23: Exception Trap Processing........................................................................................ 253

Figure 7-24: Restore Processing from Exception Trap.................................................................. 253

Figure 8-1: Clock Generator ........................................................................................................ 255

Figure 8-2: Power Save Mode State Transition Diagram ............................................................ 256

Figure 9-1: Block Diagram of Timer P.......................................................................................... 260

Figure 9-2: TMPn Capture/Compare Register 0 (TPnCCR0) ..................................................... 261

Figure 9-3: TMPn Capture/Compare Register 1 (TPnCCR1) ..................................................... 262

Figure 9-4: TMPn Counter Register (TPnCNT) .......................................................................... 263

Figure 9-5: TMPn Control Register 0 (TPnCTL0) ...................................................................... 264

Figure 9-6: TMPn Control Register 1 (TPnCTL1) (1/2)............................................................... 265

Figure 9-7: TMPn I/O Control Register 0 (TPnIOC0) .................................................................. 267

Figure 9-8: TMPn I/O Control Register 1 (TPnIOC1) .................................................................. 268

Figure 9-9: TMPn I/O Control Register 2 (TPnIOC2) .................................................................. 269

Figure 9-10: TMPn Option Register 0 (TPnOPT0) ........................................................................ 270

Figure 9-11: TMPn Input Control Register 0 (TPIC0) .................................................................. 271

Figure 9-12: TMP Input Control Register 1 (TPIC1) .................................................................... 272

Figure 9-13: TMP Input Control Register 1 (TPIC1) .................................................................... 273

Figure 9-14: Basic Operation Flow for Anytime Write.................................................................... 275

Figure 9-15: Timing Diagram for Anytime Write............................................................................. 276

Figure 9-16: Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 277

Figure 9-17: Timing Chart for Reload ............................................................................................ 278

Figure 9-18: Flowchart of Basic Operation in Interval Timer Mode................................................ 279

Figure 9-19: Basic Operation Timing in Interval Timer Mode (1/2)................................................ 280

Figure 9-20: Flowchart of Basic Operation in External Event Count Mode.................................... 283

Figure 9-21: Basic Operation Timing in External Event Count Mode (1/2) .................................... 284

User’s Manual U16580EE3V1UD00

Figure 9-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...................... 287

Figure 9-23: Basic Operation Timing in External Trigger Pulse Output Mode ............................... 288

Figure 9-24: Flowchart of Basic Operation in One-Shot Pulse Mode ............................................ 290

Figure 9-25: Timing of Basic Operation in One-Shot Pulse Mode ................................................. 291

Figure 9-26: Flowchart of Basic Operation in PWM Mode (1/2) .................................................... 293

Figure 9-27: Basic Operation Timing in PWM Mode (1/2) ............................................................. 295

Figure 9-28: Flowchart of Basic Operation in Free-Running Mode................................................ 299

Figure 9-29: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0) ...... 300

Figure 9-30: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1) ...... 301

Figure 9-31: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 0) ...... 302

Figure 9-32: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1) ...... 303

Figure 9-33: Flowchart of Pulse Period Measurement .................................................................. 305

Figure 9-34: Basic Operation Timing of Pulse Period Measurement............................................. 306

Figure 9-35: Flowchart of Alternating Pulse Width and Pulse Space Measurement ..................... 307

Figure 9-36: Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement 308

Figure 9-37: Flowchart of Simultaneous Pulse Width and Pulse Space Measurement................. 309

Figure 9-38: Basic Operation Timing of Simultaneous Pulse Width

and Pulse Space Measurement ................................................................................ 310

Figure 10-1: Timer Rn Block Diagram ........................................................................................... 315

Figure 10-2: TMRn Capture/Compare Register 0 (TRnCCR0) ..................................................... 316

Figure 10-3: TMRn Capture/Compare Register 1 (TRnCCR1) ..................................................... 317

Figure 10-4: TMRn Capture/Compare Register 2 (TRnCCR2) ..................................................... 318

Figure 10-5: TMRn Capture/Compare Register 3 (TRnCCR3) ..................................................... 319

Figure 10-6: TMRn Compare Register 4 (TRnCCR4) ................................................................... 320

Figure 10-7: TMRn Compare Register 5 (TRnCCR5) ................................................................... 321

Figure 10-8: TMRn Counter Read Register (TRnCNT) ................................................................ 322

Figure 10-9: TMRn Sub-Counter Read Register (TRnSBC) ......................................................... 322

Figure 10-10: TMRn Dead Time Setting Register 0 (TRnDTC0) .................................................... 323

Figure 10-11: TMRn Dead Time Setting Register 1 (TRnDTC1) .................................................... 323

Figure 10-12: TMRn Control Register 0 (TRnCTL0) (1/2) .............................................................. 324

Figure 10-13: TMRn Control Register 1 (TRnCTL1) (1/2) ............................................................... 326

Figure 10-14: TMRn I/O Control Register 0 (TRnIOC0) ................................................................. 328

Figure 10-15: TMR1 I/O Control Register 1 (TR1IOC1) ................................................................. 329

Figure 10-16: TMR1 I/O Control Register 2 (TR1IOC2) ................................................................. 330

Figure 10-17: TMRn I/O Control Register 3 (TRnIOC3) ................................................................. 331

Figure 10-18: TMRn I/O Control Register 4 (TRnIOC4) ................................................................. 332

Figure 10-19: TMRn Option Register 0 (TRnOPT0) (1/2)................................................................ 333

Figure 10-20: TMRn Option Register 1 (TRnOPT1) (1/2)................................................................ 335

Figure 10-21: TMRn Option Register 2 (TRnOPT2) (1/2)................................................................ 337

Figure 10-22: TMRn Option Register 3 (TRnOPT3) (1/2)................................................................ 339

Figure 10-23: TMRn Option Register 6 (TRnOPT6) ....................................................................... 341

Figure 10-24: TMRn Option Register 7 (TRnOPT7) ....................................................................... 342

Figure 10-25: Anytime Rewrite Timing ............................................................................................ 347

Figure 10-26: Basic Operation Flow during Batch Rewrite.............................................................. 352

Figure 10-27: Batch Rewrite Timing (1/2)........................................................................................ 353

Figure 10-28: TORn7 Pin Output Timing 1 ...................................................................................... 360

Figure 10-29: Interrupt Signal Output Example (1/2) ....................................................................... 364

Figure 10-30: Up Count Flags Timings (1/2) ................................................................................... 368

Figure 10-31: Normal Phase/Inverted Phase Simultaneous Active Detection Flag Timing............. 369

Figure 10-32: Reload Hold Flag Timings ......................................................................................... 370

Figure 10-33: Interrupt Thinning Out Operations (1/2) .................................................................... 372

Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2)......... 374

Figure 10-35: A/D Conversion Trigger Output Controller................................................................. 376

Figure 10-36: A/D Conversion Trigger Timings (1/2) ....................................................................... 378

Figure 10-37: Error Interrupt (INTTRnER) and Error Signal (TRnER) Output Controller................. 380

Figure 10-38: Error Interrupt and Error Signal Output Controller in PWM mode ............................. 381

Figure 10-39: Error Interrupt and Error Signal Output Controller in triangular wave PWM mode.... 382

Figure 10-40: Error Interrupt and Error Signal Output Controller

User’s Manual U16580EE3V1UD00

in High-Accuracy T-PWM Mode / PWM Mode with Dead Time ................................ 383

Figure 10-41: Basic Operation Flow in Interval Timer Mode............................................................ 384

Figure 10-42: Basic Timing in Interval Timer Mode (1/2)................................................................. 386

Figure 10-43: Basic Operation Timing in External Event Count Mode (1/4).................................... 390

Figure 10-44: Basic Operation Flow in External Trigger Pulse Output Mode .................................. 396

Figure 10-45: Basic Operation Timing in External Trigger Pulse Output Mode............................... 397

Figure 10-46: Basic Operation Flow in One-Shot Pulse Mode ........................................................ 400

Figure 10-47: Basic Operation Timing in One-Shot Pulse Mode ..................................................... 401

Figure 10-48: Basic Operation Mode in PWM Mode (1/2) ............................................................... 404

Figure 10-49: Basic Operation Timing in PWM Mode (1/2) ............................................................. 406

Figure 10-50: Basic Operation Flow in Free-Running Mode............................................................ 408

Figure 10-51: Basic Operation Timing in Free-Running Mode (Compare Function) ....................... 411

Figure 10-52: Basic Operation Timing in Free-Running Mode (Capture Function) ......................... 412

Figure 10-53: Basic Operation Timing in Free-Running Mode (Compare/Capture Function).......... 413

Figure 10-54: Basic Operation Timing in Pulse Width Measurement Mode .................................... 415

Figure 10-55: Basic Operation Timing in Triangular Wave PWM Mode .......................................... 419

Figure 10-56: High-Accuracy T-PWM Mode Block Diagram............................................................ 420

Figure 10-57: Counter Operation in High-Accuracy T-PWM Mode.................................................. 424

Figure 10-58: Sub-Counter Operation in High-Accuracy T-PWM Mode .......................................... 424

Figure 10-59: Timer Output Example When TRnCE = 1 Is Set (Initial)

(High-Accuracy T-PWM Mode).................................................................................. 425

Figure 10-60: Timer Output Example During Operation (High-Accuracy T-PWM Mode) ................ 426

Figure 10-61: TORn1 Pin Output Example When Performing Additional Pulse Control.................. 427

Figure 10-62: TORn1 Pin Output Example When Additional Pulse Control Is Not Performed........ 428

Figure 10-63: Timings of Timer Output in High-accuracy T-PWM mode (1/3)................................. 429

Figure 10-64: Timer Output Change after Compare Register Updating Timings (1/3) .................... 433

Figure 10-65: Compare Register Value After Trough Reload Timing (1/3)...................................... 436

Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (1/3) ......... 439

Figure 10-67: Compare Register Value After Trough Reload (1/3) ................................................. 442

Figure 10-68: Output Waveform Example When Dead Time Is Set ................................................ 445

Figure 10-69: Dead Time Control in High-Accuracy T-PWM Mode ................................................. 446

Figure 10-70: Operation Example Setting Is Out of Range ............................................................. 447

Figure 10-71: Error Interrupt Operation Example ............................................................................ 448

Figure 10-72: Block Diagram in PWM Mode With Dead Time......................................................... 449

Figure 10-73: Output Waveform Example in PWM Mode with Dead Time ...................................... 451

Figure 10-74: Timer Output Example When TRnCE = 1 Is Set (Initial)

(PWM mode with Dead Time) ................................................................................... 454

Figure 10-75: Output Waveform Example in PWM Mode with Dead Time ...................................... 455

Figure 10-76: Error Interrupt (INTTRnER) in PWM Mode with Dead Time...................................... 456

Figure 11-1: Block Diagram of Timer T.......................................................................................... 460

Figure 11-2: TMTn Capture/Compare Register 0 (TTnCCR0) ...................................................... 461

Figure 11-3: TMTn Capture/Compare Register 1 (TTnCCR1) ...................................................... 462

Figure 11-4: TMTn Counter Write Buffer Register (TTnTCW) ...................................................... 464

Figure 11-5: TMTn Counter Read Buffer Register (TTnCNT) ....................................................... 464

Figure 11-6: TMTn Control Register 0 (TTnCTL0) (1/2) ................................................................ 465

Figure 11-7: TMTn Control Register 1 (TTnCTL1) (1/2) ................................................................ 467

Figure 11-8: TMTn Control Register 2 (TTnCTL2) (1/2) ................................................................ 469

Figure 11-9: TMTn I/O Control Register 0 (TTnIOC0) .................................................................. 471

Figure 11-10: TMTn I/O Control Register 1 (TTnIOC1) .................................................................. 472

Figure 11-11: TMTn I/O Control Register 2 (TTnIOC2) .................................................................. 473

Figure 11-12: TMTn I/O Control Register 3 (TTnIOC3) (1/2)........................................................... 474

Figure 11-13: TMTn Option Register 0 (TTnOPT0) ........................................................................ 476

Figure 11-14: TMTn Option Register 1 (TTnOPT1) (1/2)................................................................. 477

Figure 11-15: TMTn Option Register 2 (TTnOPT2) ......................................................................... 479

Figure 11-16: Basic Operation Flow for Anytime Rewrite ................................................................ 483

Figure 11-17: Basic Anytime Rewrite Operation Timing .................................................................. 484

Figure 11-18: Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 485

Figure 11-19: Basic Reload Operation Timing................................................................................. 486

User’s Manual U16580EE3V1UD00

Figure 11-20: Basic Operation Flow in Interval Timer Mode............................................................ 487

Figure 11-21: Basic Timing in Interval Timer Mode (1/2)................................................................. 488

Figure 11-22: Basic Operation Timing in External Event Count Mode (1/4).................................... 491

Figure 11-23: Basic Operation Flow in External Trigger Pulse Output Mode .................................. 496

Figure 11-24: Basic Operation Timing in External Trigger Pulse Output Mode ............................... 497

Figure 11-25: Basic Operation Flow in One-Shot Pulse Mode ........................................................ 499

Figure 11-26: Basic Operation Timing in One-Shot Pulse Mode..................................................... 500

Figure 11-27: Basic Operation Mode in PWM Mode (1/2) ............................................................... 501

Figure 11-28: Basic Operation Timing in PWM Mode (1/2) ............................................................. 503

Figure 11-29: Basic Operation Flow in Free-Running Mode............................................................ 505

Figure 11-30: Basic Operation Timing in Free-Running Mode (Compare Function) ....................... 507

Figure 11-31: Basic Operation Timing in Free-Running Mode (Capture Function) ......................... 508

Figure 11-32: Basic Operation Timing in Free-Running Mode (Compare/Capture Function).......... 509

Figure 11-33: Basic Operation Timing in Pulse Width Measurement Mode .................................... 511

Figure 11-34: Basic Operation Timing in Triangular Wave PWM Mode .......................................... 513

Figure 11-35: Encoder Count Function Up/Down Count Selection Specification Timings (1/6) ...... 516

Figure 11-36: Counter Clearing to 0000H through Encoder Clear Input (pin TECRTn)

Timings (1/4) ............................................................................................................. 523

Figure 11-37: Counter Hold through Bit TTnECC Timings (1/5) ...................................................... 527

Figure 11-38: Basic Timing in Offset Trigger Generation Mode ...................................................... 533

Figure 12-1: Block Diagram of Timer ENC10 (TMENC10) ............................................................ 538

Figure 12-2: Timer ENC10 (TMENC10) ........................................................................................ 539

Figure 12-3: Compare Register 100 (CM100) .............................................................................. 541

Figure 12-4: Compare Register 101 (CM101) .............................................................................. 542

Figure 12-5: Capture/Compare Register 100 (CC100) ................................................................. 543

Figure 12-6: Capture/Compare Register 101 (CC101) ................................................................. 544

Figure 12-7: Timer Unit Mode Register 10 (TUM10) ................................................................... 545

Figure 12-8: Timer Control Register 10 (TMC10) (1/2) ................................................................. 546

Figure 12-9: Capture/Compare Control Register 10(CCR10) ....................................................... 548

Figure 12-10: Signal Edge Selection Register 10 (SESA10) (1/2) ................................................ 549

Figure 12-11: Prescaler Mode Register 10 (PRM10) ..................................................................... 551

Figure 12-12: Status Register 10 (STATUS10) ............................................................................. 553

Figure 12-13: TMENC10 Block Diagram (During PWM Output Operation) ..................................... 556

Figure 12-14: PWM Signal Output Example (When ALVT10 Bit = 0 Is Set).................................... 557

Figure 12-15: Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin)..................... 559

Figure 12-16: Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin):

In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing....................................... 559

Figure 12-17: Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1, TCUD1 Pins) ..... 560

Figure 12-18: Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin)..................... 561

Figure 12-19: Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1 Pin):

In Case of Simultaneous TIUD1, TCUD1 Pin Edge Timing....................................... 561

Figure 12-20: Mode 4 ...................................................................................................................... 562

Figure 12-21: Example of TMENC10 Operation When Interval Operation and Transfer

Operation are Combined ........................................................................................... 563

Figure 12-22: Example of TM1Operation in UDC Mode.................................................................. 564

Figure 12-23: Clear Operation upon Match with CM100 During TMENC10 Up Count Operation ... 566 Figure 12-24: Clear Operation upon Match with CM101 during TMENC10

Down Count Operation .............................................................................................. 566

Figure 12-25: Count Value Clear Operation upon Compare Match................................................. 567

Figure 12-26: Internal Operation During Transfer Operation ........................................................... 567

Figure 12-27: Interrupt Output upon Compare Match (CM101 with Operation Mode

set to General-Purpose Timer Mode and Count Clock Set to f

/8) ......................... 568

Figure 12-28: TM1UBDn Flag Operation......................................................................................... 568

Figure 13-1: Block Diagram of Auxiliary Frequency Output Function ............................................ 569

Figure 13-2: Prescaler Mode Register 2 (PRSM2) ...................................................................... 570

Figure 13-3: Prescaler Compare Register 2 (PRSCM2) .............................................................. 571

Figure 14-1: Block Diagram of A/D Converter (ADCn) .................................................................. 575

Figure 14-2: A/D Converter n Mode Register 0 (ADMn0) ............................................................ 576

User’s Manual U16580EE3V1UD00

Figure 14-3: A/D Converter n Mode Register 1 (ADMn1) (1/2) ..................................................... 577

Figure 14-4: A/D Converter n Mode Register 2 (ADMn2) ............................................................ 579

Figure 14-5: A/D Converter n Trigger Source Select Register (ADTRSELn) ............................... 580

Figure 14-6: A/D Conversion Result Registers n0 to n9, n0H to n9H

(ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 581

Figure 14-7: Relationship Between Analog Input Voltage and A/D Conversion Results ............... 583

Figure 14-8: A/D Conversion Result Registers n0 to n9, n0H to n9H

(ADCRn0 to ADCRn9, ADCRn0H to ADCRn9H) ..................................................... 584

Figure 14-9: Select Mode Operation Timing: 1-Buffer Mode (ANIn1) ............................................ 588

Figure 14-10: Select Mode Operation Timing: 4-Buffer Mode (ANIn2) ............................................ 589

Figure 14-11: Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)................................ 590

Figure 14-12: Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)......................... 591

Figure 14-13: Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)....................... 593

Figure 14-14: Example of Scan Mode Operation (A/D Trigger Scan).............................................. 595

Figure 14-15: Example of 1-Buffer Mode Operation (Timer Trigger Select: 1 Buffer) (ANIn1) ........ 597

Figure 14-16: Example of 4-Buffer Mode Operation (Timer Trigger Select: 4 Buffers) (ANIn3) ...... 599

Figure 14-17: Example of Scan Mode Operation (Timer Trigger Scan) (ANIn0 to ANIn4).............. 601

Figure 14-18: Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer) (ANIn1) .... 603

Figure 14-19: Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers) (ANIn2) .. 605

Figure 14-20: Example of Scan Mode Operation (External Trigger Scan) (ANIn0 to ANIn3).......... 607

Figure 15-1: Block Diagram of Asynchronous Serial Interface n ................................................... 611

Figure 15-2: UARTCn Control Register 0 (UCnCTL0) (1/2) ........................................................ 612

Figure 15-3: UARTCn Control Register 1 (UCnCTL1) ................................................................. 614

Figure 15-4: UARTCn Control Register 2 (UCnCTL2) ................................................................. 615

Figure 15-5: UARTCn Option Control Register 0 (UCnOPT0) (1/2) ............................................. 616

Figure 15-6: UARTCn Option Control Register 1 (UCnOPT1) ..................................................... 618

Figure 15-7: UARTCn Status Register (UCnSTR) (1/2) .............................................................. 620

Figure 15-8: UARTCn Status Register 1 (UCnSTR1) .................................................................. 622

Figure 15-9: UARTCn Receive Data Register (UCnRX, UCnRXL) .............................................. 623

Figure 15-10: UARTCn Transmit Data Register (UCnTX, UCnTXL) .............................................. 624

Figure 15-11: UARTC Transmit/Receive Data Format (1/2)............................................................ 626

Figure 15-12: LIN Transmission Manipulation Outline..................................................................... 628

Figure 15-13: LIN Reception Manipulation Outline .......................................................................... 629

Figure 15-14: SBF Transmission Timing ......................................................................................... 630

Figure 15-15: SBF Reception Timing...............................................................................................631

Figure 15-16: UART Transmission ..................................................................................................632

Figure 15-17: Continuous Transmission Processing Flow............................................................... 633

Figure 15-18: Continuous Transfer Operation Timing ..................................................................... 634

Figure 15-19: UART Reception Timing ............................................................................................ 635

Figure 15-20: Noise Filter Circuit ..................................................................................................... 638

Figure 15-21: Configuration of Baud Rate Generator ...................................................................... 639

Figure 15-22: Allowable Baud Rate Range During Reception......................................................... 642

Figure 15-23: Transfer Rate During Continuous Transfer ............................................................... 644

Figure 16-1: Block Diagram of CSIBn............................................................................................ 646

Figure 16-2: CSIBn Receive Data Register (CBnRX, CBnRXL) ................................................... 647

Figure 16-3: CSIBn Transmit Data Register (CBnTX, CBnTXL) ................................................... 648

Figure 16-4: CSIBn Control Register 0 (CBnCTL0) (1/2) ............................................................. 649

Figure 16-5: CSIBn Control Register 1 (CBnCTL1) ..................................................................... 651

Figure 16-6: CSIBn Control Register 2 (CBnCTL2) ...................................................................... 652

Figure 16-7: Effect of Transfer Data Length Setting ...................................................................... 653

Figure 16-8: CSIBn Status Register (CBnSTR) ........................................................................... 654

Figure 16-9: Single Transfer Mode (Master Mode, Transmission/Reception Mode) ..................... 655

Figure 16-10: Single Transfer Mode (Master Mode, Transmission Mode) ...................................... 656

Figure 16-11: Single Transfer Mode (Master Mode, Reception Mode)............................................ 657

Figure 16-12: Continuous Mode (Master Mode, Transmission/Reception Mode) ........................... 658

Figure 16-13: Continuous Mode (Master Mode, Transmission Mode)............................................. 659

Figure 16-14: Continuous Mode (Master Mode, Reception Mode).................................................. 660

Figure 16-15: Continuous Reception Mode (Error).......................................................................... 661

User’s Manual U16580EE3V1UD00

Figure 16-16: Continuous Mode (Slave Mode, Transmission/Reception Mode) ............................. 662

Figure 16-17: Continuous Mode (Slave Mode, Reception Mode).................................................... 663

Figure 16-18: CSIBn Clock Timing (1/2) .......................................................................................... 664

Figure 16-19: Operation Flow of Single Transmission..................................................................... 667

Figure 16-20: Operation Flow of Single Reception (Master)............................................................ 668

Figure 16-21: Operation Flow of Single Reception (Slave) ............................................................. 669

Figure 16-22: Operation Flow of Continuous Transmission............................................................. 670

Figure 16-23: Operation Flow of Continuous Reception (Master) ................................................... 671

Figure 16-24: Operation Flow of Continuous Reception (Slave) ..................................................... 672

Figure 16-25: Block Diagram of Baud Rate Generators 0 and 1 (BRG0, BRG1) ............................ 673

Figure 16-26: Block Diagram of CSIBn Baud Rate Generators....................................................... 673

Figure 16-27: Prescaler Mode Registers 0 and 1 (PRSM0, PRSM1) ............................................ 674

Figure 16-28: Prescaler Compare Registers 0 and 1 (PRSCM0, PRSCM1) ................................. 675

Figure 17-1: Block Diagram of Clocked Serial Interface 3n (CSI3n).............................................. 679

Figure 17-2: Clocked Serial Interface Mode Register 3n (CSIM3n) (1/2) .................................... 680

Figure 17-3: Clocked Serial Interface Clock Select Register 3n (CSIC3n) (1/3) .......................... 682

Figure 17-4: Receive Data Buffer Register 3n (SIRB3n, SIRB3nL, SIRB3nH) ............................ 685

Figure 17-5: Chip Select CSI Buffer Register 3n (SFCS3n, SFCS3nL) ........................................ 686

Figure 17-6: Transmit Data CSI Buffer Register 3n (SFDB3n, SFDB3nL, SFDB3nH) ................ 687

Figure 17-7: CSIBUF Status Register 3n (SFA3n)(1/3) ............................................................... 688

Figure 17-8: Transfer Data Length Select Register 3n (CSIL3n) ................................................. 691

Figure 17-9: Transfer Data Number Specification Register 3n (SFN3n) ..................................... 692

Figure 17-10: Transfer Clock of CSI3n ............................................................................................693

Figure 17-11: Function of CSI Data Buffer Register n (CSIBUFn)................................................... 696

Figure 17-12: Data Transfer Direction Specification (MSB first) ...................................................... 697

Figure 17-13: Data Transfer Direction Specification (LSB first) ....................................................... 698

Figure 17-14: Transfer Data Length Changing Function ................................................................. 699

Figure 17-15: Clock Timing.............................................................................................................. 700

Figure 17-16: Master Mode ............................................................................................................. 701

Figure 17-17: Slave Mode ............................................................................................................... 702

Figure 17-18: Single Mode .............................................................................................................. 704

Figure 17-19: Consecutive Mode..................................................................................................... 706

Figure 17-20: Delay Control of Transmission/Reception Completion Interrupt (INTC3n):............... 708

Figure 17-21: Transfer Wait Function (1/3)...................................................................................... 709

Figure 17-22: Single Mode (Master Mode, Transmission Mode)..................................................... 714

Figure 17-23: Single Mode (Master Mode, Reception Mode).......................................................... 716

Figure 17-24: Single Mode (Master Mode, Transmission/Reception Mode).................................... 718

Figure 17-25: Single Mode (Slave Mode, Transmission Mode)....................................................... 720

Figure 17-26: Single Mode (Slave Mode, Reception Mode) ............................................................ 722

Figure 17-27: Single Mode (Slave Mode, Transmission/Reception Mode)...................................... 724

Figure 17-28: Consecutive Mode (Master Mode, Transmission Mode) ........................................... 726

Figure 17-29: Consecutive Mode (Master Mode, Reception Mode) ................................................ 728

Figure 17-30: Consecutive Mode (Master Mode, Transmission/Reception Mode).......................... 730

Figure 17-31: Consecutive Mode (Slave Mode, Transmission Mode) ............................................. 732

Figure 17-32: Consecutive Mode (Slave Mode, Reception Mode) .................................................. 734

Figure 17-33: Consecutive Mode (Slave Mode, Transmission/Reception Mode)............................ 736

Figure 18-1: Block Diagram of CAN Module.................................................................................. 741

Figure 18-2: Composition of Layers...............................................................................................742

Figure 18-3: Data Frame ............................................................................................................... 743

Figure 18-4: Remote Frame .......................................................................................................... 744

Figure 18-5: Start of frame (SOF).................................................................................................. 744

Figure 18-6: Arbitration field (in standard format mode) ................................................................ 745

Figure 18-7: Arbitration field (in extended format mode) ............................................................... 745

Figure 18-8: Control field ............................................................................................................... 746

Figure 18-9: Data field ................................................................................................................... 747

Figure 18-10: CRC field ................................................................................................................... 747

Figure 18-11: ACK field ................................................................................................................... 748

Figure 18-12: End of frame (EOF) ................................................................................................... 748

User’s Manual U16580EE3V1UD00

Figure 18-13: Interframe space (error active node) ......................................................................... 749

Figure 18-14: Interframe space (error passive node) ...................................................................... 749

Figure 18-15: Error frame ................................................................................................................ 750

Figure 18-16: Overload frame .......................................................................................................... 751

Figure 18-17: Recovery from bus-off state through normal recovery sequence.............................. 758

Figure 18-18: Segment setting......................................................................................................... 759

Figure 18-19: Configuration of data bit time defined by CAN specification...................................... 760

Figure 18-20: Adjusting synchronization of data bit ......................................................................... 761

Figure 18-21: Re-synchronization.................................................................................................... 762

Figure 18-22: Connection to CAN bus............................................................................................. 763

Figure 18-23: Example of bit setting/clearing operations................................................................. 771

Figure 18-24: CAN module clock ..................................................................................................... 791

Figure 18-25: Data bit time .............................................................................................................. 792

Figure 18-26: Setting transmission request (TRQ) to transmit message buffer after redefinition.... 808

Figure 18-27: Transition to operation modes ................................................................................... 809

Figure 18-28: DN and MUC Bit Setting Period (for Standard ID Format) ........................................ 811

Figure 18-29: Receive history list..................................................................................................... 812

Figure 18-30: Message processing example ................................................................................... 816

Figure 18-31: Transmit history list.................................................................................................... 819

Figure 18-32: CAN module terminal connection in receive-only mode ............................................ 828

Figure 18-33: CAN module terminal connection in self-test mode................................................... 830

Figure 18-34: Timing diagram of capture signal TSOUT ................................................................. 831

Figure 18-35: Initialization................................................................................................................ 840

Figure 18-36: Re-initialization .......................................................................................................... 841

Figure 18-37: Message buffer initialization ......................................................................................842

Figure 18-38: Message buffer redefinition ....................................................................................... 843

Figure 18-39: Message Buffer Redefinition during Transmission .................................................... 844

Figure 18-40: Message transmit processing.................................................................................... 845

Figure 18-41: ABT Message transmit processing............................................................................ 846

Figure 18-42: Transmission via interrupt (using CnLOPT register) ................................................. 847

Figure 18-43: Transmission via interrupt (using CnTGPT register) ................................................. 848

Figure 18-44: Transmission via software polling.............................................................................. 849

Figure 18-45: Transmission abort processing (Except Normal Operation Mode with ABT) ............ 850

Figure 18-46: Transmission Abort Processing Except for ABT Transmission

(Normal Operation Mode with ABT) .......................................................................... 851

Figure 18-47: Transmission abort processing (normal operation mode with ABT) .......................... 852

Figure 18-48: Transmission request abort processing (normal operation mode with ABT)............. 853

Figure 18-49: Reception via interrupt (using CnLIPT register) ........................................................ 854

Figure 18-50: Reception via interrupt (using CnRGPT register) ...................................................... 855

Figure 18-51: Reception via software polling................................................................................... 856

Figure 18-52: Setting CAN sleep mode/stop mode ......................................................................... 857

Figure 18-53: Clear CAN sleep/stop mode ...................................................................................... 858

Figure 18-54: Bus-Off recovery (Except Normal Operation Mode with ABT) .................................. 859

Figure 18-55: Bus-Off recovery (Normal Operation Mode with ABT) .............................................. 860

Figure 18-56: Normal shutdown process ......................................................................................... 861

Figure 18-57: Forced shutdown process ......................................................................................... 861

Figure 18-58: Error handling ............................................................................................................ 862

Figure 18-59: Setting CPU stand-by (from CAN sleep mode) ......................................................... 863

Figure 18-60: Setting CPU stand-by (from CAN stop mode)........................................................... 864

Figure 19-1: Random Number Register (RNG) ............................................................................. 865

Figure 20-1: Port Configuration...................................................................................................... 868

Figure 20-2: Port Type 1................................................................................................................ 870

Figure 20-3: Port Type 1S.............................................................................................................. 871

Figure 20-4: Port Type 1E.............................................................................................................. 872

Figure 20-5: Port Type 2................................................................................................................ 873

Figure 20-6: Port Type 2A.............................................................................................................. 874

Figure 20-7: Port Type 2C ............................................................................................................. 875

Figure 20-8: Port Type 3................................................................................................................ 876

User’s Manual U16580EE3V1UD00

Figure 20-9: Port Type 4 ................................................................................................................ 877

Figure 20-10: Port Type 4C ............................................................................................................. 878

Figure 20-11: Port Type 5 ................................................................................................................ 879

Figure 20-12: Port Type 6 ................................................................................................................ 880

Figure 20-13: Port Type 7 ................................................................................................................ 881

Figure 20-14: Port Type 8 ................................................................................................................ 882

Figure 20-15: Port Type 9 ................................................................................................................ 883

Figure 20-16: Port Type 10 .............................................................................................................. 884

Figure 20-17: Port Type 11 .............................................................................................................. 885

Figure 20-18: Port Type 12 .............................................................................................................. 886

Figure 20-19: Port Type 13 .............................................................................................................. 888

Figure 20-20: Port Type 14 .............................................................................................................. 890

Figure 20-21: Port Type 15 .............................................................................................................. 891

Figure 20-22: Port Type 15A ........................................................................................................... 892

Figure 20-23: Port Register 0 (P0) ................................................................................................. 897

Figure 20-24: Port Register 1 (P1) ................................................................................................. 899

Figure 20-25: Port Mode Register 1 (PM1) .................................................................................... 899

Figure 20-26: Port Mode Control Register 1 (PMC1) (1/2) ............................................................. 900

Figure 20-27: Port Register 2 (P2) ................................................................................................. 903

Figure 20-28: Port Mode Register 2 (PM2) .................................................................................... 903

Figure 20-29: Port Mode Control Register 2 (PMC2) (1/2) ............................................................. 904

Figure 20-30: Port Register 3 (P3) ................................................................................................. 907

Figure 20-31: Port Mode Register 3 (PM3) .................................................................................... 907

Figure 20-32: Port Mode Control Register 3 (PMC3) (1/2) ............................................................. 908

Figure 20-33: Port Register 4 (P4) ................................................................................................. 911

Figure 20-34: Port Mode Register 4 (PM4) .................................................................................... 911

Figure 20-35: Port Mode Control Register 4 (PMC4) ...................................................................... 912

Figure 20-36: Port Register 5 (P5) ................................................................................................. 914

Figure 20-37: Port Mode Register 5 (PM5) .................................................................................... 914

Figure 20-38: Port Mode Control Register 5 (PMC5)) .................................................................... 915

Figure 20-39: Port Emergency Shut Off Control Register 5 (PESC5) ............................................ 916

Figure 20-40: Port Emergency Shut Off Status Register 5 (ESOST5)) .......................................... 917

Figure 20-41: Port Register 6 (P6) ................................................................................................. 919

Figure 20-42: Port Mode Register 6 (PM6) .................................................................................... 919

Figure 20-43: Port Mode Control Register 6 (PMC6) (1/2) ............................................................. 920

Figure 20-44: Port Emergency Shut Off Control Register 6 (PESC6) ............................................ 922

Figure 20-45: Port Emergency Shut Off Status Register 6 (ESOST6)) .......................................... 923

Figure 20-46: Port Register 7 (P7) ................................................................................................. 925

Figure 20-47: Port Mode Register 7 (PM7) .................................................................................... 925

Figure 20-48: Port Mode Control Register 7 (PMC7) (1/2) ............................................................. 926

Figure 20-49: Port Register 8 (P8) ................................................................................................. 929

Figure 20-50: Port Mode Register 8 (PM8) .................................................................................... 929

Figure 20-51: Port Mode Control Register 8 (PMC8) (1/2) ............................................................. 930

Figure 20-52: Port Register 9 (P9) ................................................................................................. 933

Figure 20-53: Port Mode Register 9 (PM9) .................................................................................... 933

Figure 20-54: Port Mode Control Register 9 (PMC9) (1/2) ............................................................. 934

Figure 20-55: Port Register 10 (P10) ............................................................................................. 937

Figure 20-56: Port Mode Register 10 (PM10) ................................................................................ 937

Figure 20-57: Port Mode Control Register 10 (PMC10) .................................................................. 938

Figure 20-58: Port Register AL(PAL) ........................................................................................... 940

Figure 20-59: Port Mode Register AL(PMAL) .............................................................................. 941

Figure 20-60: Port Mode Control Register AL (PMCAL) .............................................................. 942

Figure 20-61: Port Register AH (PAH) ...........................................................................................943

Figure 20-62: Port Mode Register AH (PMAH) ............................................................................... 944

Figure 20-63: Port Mode Control Register AH (PMCAH) ............................................................... 944

Figure 20-64: Port Register DL(PDL) ..........................................................................................946

Figure 20-65: Port Mode Register DL(PMDL) ............................................................................. 947

Figure 20-66: Port Mode Control Register DL (PMCDL) ............................................................. 948

User’s Manual U16580EE3V1UD00

Figure 20-67: Port Register DH(PDH) ......................................................................................... 950

Figure 20-68: Port Mode Register DH(PMDH) ............................................................................ 951

Figure 20-69: Port Mode Control Register DH (PMCDH) ............................................................ 952

Figure 20-70: Port Register CS (PCS) ...........................................................................................953

Figure 20-71: Port Mode Register CS (PMCS) ............................................................................... 954

Figure 20-72: Port Mode Control Register CS (PMCCS) ............................................................... 954

Figure 20-73: Port Register CT (PCT) ...........................................................................................955

Figure 20-74: Port Mode Register CT (PMCT) ............................................................................... 956

Figure 20-75: Port Mode Control Register CT (PMCCT) ............................................................... 957

Figure 20-76: Port Register CM (PCM) .......................................................................................... 958

Figure 20-77: Port Mode Register CM (PMCM) .............................................................................. 959

Figure 20-78: Port Mode Control Register CM (PMCCM) .............................................................. 960

Figure 20-79: Port Register CD (PCD) .......................................................................................... 961

Figure 20-80: Port Mode Register CD (PMCD) .............................................................................. 963

Figure 20-81: Port Mode Control Register CD (PMCCD) .............................................................. 964

Figure 20-82: Noise Elimination Control Register (NRC) (1/2) ....................................................... 967

Figure 21-1: Reset Timing ............................................................................................................. 972

Figure 22-1: Internal RAM Parity Error Status Register (RAMERR) ............................................ 974

Figure 22-2: Internal RAM Parity Error Address Register (RAMPADD) ...................................... 975

Figure 23-1: Connecting N-Wire Type Emulator (IE-V850E1-CD-NW (N-Wire Card)) .................. 979

Figure 23-2: Pin Configuration of Emulator Connector (on Target System Side) .......................... 980

Figure 23-3: Example of Recommended Emulator Connection of V850E/PH2............................. 982

Figure 24-1: Flash Memory Mapping of μPD70F3187................................................................... 986

Figure 24-2: Flash Memory Mapping of μPD70F3447................................................................... 987

Figure 24-3: Environment Required for Writing Programs to Flash Memory ................................. 991

Figure 24-4: Communication with Dedicated Flash Programmer (UARTC0) ................................ 992

Figure 24-5: Communication with Dedicated Flash Programmer (CSIB0) .................................... 992

Figure 24-6: Communication with Dedicated Flash Programmer (CSIB0 + HS) ........................... 993

Figure 24-7: Procedure for Manipulating Flash Memory................................................................ 995

Figure 24-8: Selection of Communication Mode............................................................................ 996

Figure 24-9: Communication Commands ...................................................................................... 997

Figure 24-10: FLMD0 Pin Connection Example .............................................................................. 998

Figure 24-11: FLMD1 Pin Connection Example .............................................................................. 999

Figure 24-12: Conflict of Signals (Serial Interface Input Pin) ......................................................... 1000

Figure 24-13: Malfunction of Other Device .................................................................................... 1001

Figure 24-14: Conflict of Signals (RESET

Figure 24-15: Concept of Self Programming ................................................................................. 1003

Figure 24-16: Rewriting Entire Memory Area (Boot Swap)............................................................ 1005

Figure 25-1: Oscillator Recommendations................................................................................... 1009

Figure 25-2: AC Test Input/Output Waveform ............................................................................. 1011

Figure 25-3: AC Test Load Condition .......................................................................................... 1011

Figure 25-4: External Asynchronous Memory Access Read Timing............................................ 1013

Figure 25-5: External Asynchronous Memory Access Write Timing ............................................ 1015

Figure 25-6: Reset Timing ........................................................................................................... 1016

Figure 25-7: Interrupt Timing ....................................................................................................... 1017

Figure 25-8: Timer P Characteristics ........................................................................................... 1018

Figure 25-9: Timer R Characteristics ........................................................................................... 1019

Figure 25-10: Timer T Characteristics ........................................................................................... 1020

Figure 25-11: CSIB Timing in Master Mode (CKP, DAP bits = 00B or 11B).................................. 1022

Figure 25-12: CSIB Timing in Master Mode (CKP, DAP bits = 01B or 10B).................................. 1022

Figure 25-13: CSIB Timing in Slave Mode (CKP, DAP bits = 00B or 11B).................................... 1023

Figure 25-14: CSIB Timing in Slave Mode (CKP, DAP bits = 01B or 10B).................................... 1023

Figure 25-15: CSI3 Timing in Master Mode (CKP, DAP bits = 00B or 11B) .................................. 1025

Figure 25-16: CSI3 Timing in Master Mode (CKP, DAP bits = 01B or 10B) .................................. 1025

Figure 25-17: CSI3 Timing in Slave Mode (CKP, DAP bits = 00B or 11B) .................................... 1026

Figure 25-18: CSI3 Timing in Slave Mode (CKP, DAP bits = 01B or 10B) .................................... 1026

Figure 25-19: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 0, CSMD = 0) .. 1027 Figure 25-20: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 0) .. 1027

Pin) .............................................................................. 1002

User’s Manual U16580EE3V1UD00

Figure 25-21: CSI3 Chip Select Timing (Master Mode only) (CSIT = 0, CSWE = 1, CSMD = 1) .. 1028 Figure 25-22: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 0, CSMD = 0) .. 1028 Figure 25-23: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 0) .. 1029 Figure 25-24: CSI3 Chip Select Timing (Master Mode only) (CSIT = 1, CSWE = 1, CSMD = 1) .. 1029

Figure 25-25: Equivalent Circuit of Analog Inputs ......................................................................... 1030

Figure 25-26: Serial Write Operation Characteristics .................................................................... 1032

Figure 26-1: 208-Pin Plastic QFP (Fine Pitch) (28 x 28).............................................................. 1033

Figure 26-2: 256-Pin Plastic BGA (Fine Pitch) (21 x 21) ............................................................. 1034

User’s Manual U16580EE3V1UD00

List of Tables

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA .................................................. 39

Table 2-1: Port Pins......................................................................................................................... 49

Table 2-2: Non-Port Pins ................................................................................................................. 54

Table 2-3: Pin Status in Reset and Standby Mode .......................................................................... 60

Table 2-4: I/O Circuit Types............................................................................................................. 76

Table 2-5: Noise Suppression Timing..............................................................................................81

Table 3-1: Program Registers.......................................................................................................... 87

Table 3-2: System Register Numbers.............................................................................................. 88

Table 3-3: Saturated Operation Results ......................................................................................... 92

Table 3-4: Floating Point Arithmetic Unit Registers ......................................................................... 94

Table 3-5: Peripheral I/O Registers ............................................................................................... 107

Table 3-6: Programmable Peripheral I/O Registers....................................................................... 123

Table 4-1: Number of Bus Access Clocks ..................................................................................... 151

Table 4-2: Bus Priority Order ......................................................................................................... 179

Table 6-1: Timer TMR Address Mapping for DMA Transfer.......................................................... 204

Table 6-2: DMA Configuration of Serial Data Reception ............................................................... 208

Table 6-3: DMA Configuration of Serial Data Transmission .......................................................... 212

Table 6-4: Relations Between DMA Trigger Factors and DMA Completion Interrupts.................. 217

Table 7-1: Interrupt/Exception Source List .................................................................................... 219

Table 7-2: Addresses and Bits of Interrupt Control Registers ....................................................... 237

Table 8-1: Operation Status in HALT Mode................................................................................... 257

Table 8-2: Operation After Releasing HALT Mode by Interrupt Request Signal ........................... 258

Table 9-1: Configuration of TMP0 to TMP8 ................................................................................... 260

Table 10-1: Timer R Configuration .................................................................................................. 314

Table 10-2: TMRn Count Clock and Count Delay ........................................................................... 325

Table 10-3: List of Timer Outputs in Each Mode (1/2)..................................................................... 358

Table 10-4: List of Interrupts in Each Mode (1/2) ............................................................................ 361

Table 10-5: List of A/D Conversion Triggers, Peak Interrupts and Valley Interrupts in Each Mode 363

Table 10-1: Positive Phase Operation Condition List ...................................................................... 432

Table 10-2: Negative Phase Operation Condition List..................................................................... 432

Table 10-3: Compare Register Value After Trough Reload (TRnDTC0 < TRnDTC1)..................... 433

Table 10-4: Compare Register Value After Trough Reload ............................................................. 436

Table 10-5: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0)..................... 438

Table 10-6: Compare Register Value After Trough Reload ............................................................. 442

Table 11-1: Timer T Configuration................................................................................................... 458

Table 11-2: List of Timer T Registers .............................................................................................. 459

Table 11-3: Capture/Compare Functions in Each Mode ................................................................. 461

Table 11-4: Capture/Compare Functions in Each Mode ................................................................. 463

Table 11-5: TMTn Count Clock and Count Delay............................................................................ 466

Table 11-6: Counter Clear Operation ..............................................................................................481

Table 11-7: Capture/Compare Rewrite Methods in Each Mode ...................................................... 486

Table 12-1: Timer ENC10 Configuration List................................................................................... 537

Table 12-2: Timer ENC10 (TMENC10) Clear Conditions ................................................................ 540

Table 12-3: Capture Trigger Signal to 16-Bit Capture Register ....................................................... 556

Table 12-4: List of Count Operations in UDC Mode ........................................................................ 558

Table 13-1: AFO Configuration ....................................................................................................... 569

Table 14-1: Assignment of A/D Conversion Result Registers to Analog Input Pins ........................ 582

Table 14-2: Relationship Between Operation Mode and Trigger Mode........................................... 586

Table 14-3: Correspondence Between Analog Input Pins and ADCRnm Register

(A/D Trigger Select: 1 Buffer) ....................................................................................... 591

Table 14-4: Correspondence Between Analog Input Pins and ADCRnm Register

(A/D Trigger Select: 4 Buffers) ..................................................................................... 592

Table 14-5: Correspondence Between Analog Input Pins and ADCRnm Register

(A/D Trigger Scan)........................................................................................................ 594

Table 14-6: Correspondence Between Analog Input Pins and ADCRnm Register

(1-Buffer Mode (Timer Trigger Select: 1 Buffer)).......................................................... 597

User’s Manual U16580EE3V1UD00

Table 14-7: Correspondence Between Analog Input Pins and ADCRnm Register

(4-Buffer Mode (Timer Trigger Select: 4 Buffers)) ........................................................ 598

Table 14-8: Correspondence Between Analog Input Pins and ADCRnm Register

(Scan Mode (Timer Trigger Scan))............................................................................... 600

Table 14-9: Correspondence Between Analog Input Pins and ADCRnm Register

(External Trigger Select: 1 Buffer) ................................................................................ 602

Table 14-10: Correspondence Between Analog Input Pins and ADCRnm Register

(External Trigger Select: 4 Buffers)) ............................................................................. 604

Table 14-11: Correspondence Between Analog Input Pins and ADCRnm Register

(External Trigger Scan) ................................................................................................ 606

Table 15-1: Relation between UARTCn Register Settings and Data Format ................................. 619

Table 15-2: Default Priorities of UARTCn Interrupts....................................................................... 625

Table 15-3: Reception Error Causes ..............................................................................................636

Table 15-4: Baud Rate Generator Setting Data............................................................................... 641

Table 15-5: Maximum/Minimum Allowable Baud Rate Error ........................................................... 643

Table 16-1: CSIBn Configuration..................................................................................................... 645

Table 17-1: Operation Modes .......................................................................................................... 695

Table 17-2: Conditions Under Which Data Can Be Transferred in Slave Mode .............................. 702

Table 17-3: Default Output Level of SCK3n

Table 17-4: Default Output Level of SO3n Pin ................................................................................ 712

Table 17-5: Default Output Level of SCS3n0 to SCS3n3 Pins ........................................................ 713

Table 18-1: Overview of Functions .................................................................................................. 740

Table 18-2: Frame types.................................................................................................................. 743

Table 18-3: RTR frame settings....................................................................................................... 745

Table 18-4: Frame format setting (IDE bit) and number of identifier (ID) bits .................................. 746

Table 18-5: Data length setting........................................................................................................ 746

Table 18-6: Operation in error status............................................................................................... 750

Table 18-7: Definition of error frame fields ...................................................................................... 750

Table 18-8: Definition of overload frame fields ................................................................................ 751

Table 18-9: Determining bus priority................................................................................................ 752

Table 18-10: Bit stuffing..................................................................................................................... 752

Table 18-11: Error types.................................................................................................................... 753

Table 18-12: Output timing of error frame ......................................................................................... 754

Table 18-13: Types of error states..................................................................................................... 755

Table 18-14: Error counter................................................................................................................. 756

Table 18-15: Segment setting............................................................................................................ 759

Table 18-16: Configuration of data bit time defined by CAN specification......................................... 760

Table 18-17: CAN module base addresses....................................................................................... 764

Table 18-18: List of CAN Controller registers ....................................................................................765

Table 18-19: CAN0 global and module registers............................................................................... 766

Table 18-20: CAN0 message buffer registers ................................................................................... 767

Table 18-21: CAN global register bit configuration ............................................................................ 767

Table 18-22: CAN module register bit configuration .......................................................................... 768

Table 18-23: Message buffer register bit configuration ..................................................................... 770

Table 18-1: List of CAN module interrupt sources........................................................................... 827

Table 18-2: Outline of the Receive/Transmit in Each Operation Mode ........................................... 830

Table 18-3: Settable bit rate combinations ...................................................................................... 833

Table 18-4: Representative examples of baud rate settings

(fCANMOD = 8 MHz).................................................................................................... 836

Table 18-5: Representative examples of baud rate settings

(fCANMOD = 16 MHz).................................................................................................. 838

Table 20-1: Port Type and Function Overview ................................................................................ 869

Table 20-2: Peripheral Registers of I/O Ports................................................................................. 893

Table 20-3: Peripheral Registers of Valid Edge Control ................................................................. 896

Table 20-4: Alternate Function Pins and Port Types of Port 0 ........................................................ 897

Table 20-5: Alternate Function Pins and Port Types of Port 1 ........................................................ 898

Table 20-6: Alternate Function Pins and Port Types of Port 2 ........................................................ 902

Table 20-7: Alternate Function Pins and Port Types of Port 3 ........................................................ 906

Pin ............................................................................. 712

User’s Manual U16580EE3V1UD00

Table 20-8: Alternate Function Pins and Port Types of Port 4 ........................................................ 910

Table 20-9: Alternate Function Pins and Port Types of Port 5 ........................................................ 913

Table 20-10: Alternate Function Pins and Port Types of Port 6 ........................................................ 918

Table 20-11: Alternate Function Pins and Port Types of Port 7 ........................................................ 924

Table 20-12: Alternate Function Pins and Port Types of Port 8 ........................................................ 928

Table 20-13: Alternate Function Pins and Port Types of Port 9 ........................................................ 932

Table 20-14: Alternate Function Pins and Port Types of Port 10 ...................................................... 936

Table 20-15: Alternate Function Pins and Port Types of Port AL ...................................................... 939

Table 20-16: Alternate Function Pins and Port Types of Port AH ..................................................... 943

Table 20-17: Alternate Function Pins and Port Types of Port DL ...................................................... 945

Table 20-18: Alternate Function Pins and Port Types of Port DH ..................................................... 949

Table 20-19: Alternate Function Pins and Port Types of Port CS ..................................................... 953

Table 20-20: Alternate Function Pins and Port Types of Port CT...................................................... 955

Table 20-21: Alternate Function Pins and Port Types of Port CM ..................................................... 958

Table 20-22: Alternate Function Pins and Port Types of Port CD ..................................................... 961

Table 20-23: Noise Elimination.......................................................................................................... 965

Table 23-1: Pin Functions of Connector for IE-V850E1-CD-NW (on Target System Side)............. 981

Table 24-1: Rewrite Method ............................................................................................................ 988

Table 24-2: Basic Functions ............................................................................................................ 989

Table 24-3: Protection Functions..................................................................................................... 990

Table 24-4: Signal Connections of Dedicated Flash Programmer (PG-FP4) .................................. 994

Table 24-5: Communication Commands ......................................................................................... 997

Table 24-6: Relationship Between FLMD0 and FLMD1 Pins and Operation Mode

when Reset is Released............................................................................................... 999

Table 24-7: Pins Used by Serial Interfaces ................................................................................... 1000

Table 25-1: Absolute Maximum Ratings........................................................................................ 1007

Table 25-2: Capacitance ............................................................................................................... 1008

Table 25-3: Operating Conditions ................................................................................................. 1008

Table 25-4: Oscillator Characteristics ........................................................................................... 1009

Table 25-5: DC Characteristics...................................................................................................... 1010

Table 25-6: External Asynchronous Memory Access Read Timing .............................................. 1012

Table 25-7: External Asynchronous Memory Access Write Timing .............................................. 1014

Table 25-8: Reset Timing ............................................................................................................. 1016

Table 25-9: Interrupt Timing ......................................................................................................... 1017

Table 25-10: Timer P Characteristics ............................................................................................. 1018

Table 25-11: Timer R Characteristics ............................................................................................. 1019

Table 25-12: Timer T Characteristics ............................................................................................. 1020

Table 25-13: CSIB Characteristics (Master Mode) .......................................................................... 1021

Table 25-14: CSIB Characteristics (Slave Mode) ............................................................................ 1021

Table 25-15: CSI3 Characteristics (Master Mode) .......................................................................... 1024

Table 25-16: CSI3 Characteristics (Slave Mode) ............................................................................ 1024

Table 25-17: A/D Converter Characteristics ................................................................................... 1030

Table 25-18: Analog Input Characteristics....................................................................................... 1030

Table 25-19: Flash Memory Basic Characteristics .......................................................................... 1031

Table 25-20: Flash Memory Programming Characteristics ............................................................. 1031

Table 25-21: Serial Write Operation Characteristics ....................................................................... 1032

Table 27-1: Soldering Conditions .................................................................................................. 1035

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

The V850E/PH2 (PHOENIX-F “V850 series™”. This chapter gives a short outline of the V850E/PH2 microcontroller.

Note

) is a product of the NEC Electronics single-chip microcontrollers

1.1 Outline

The V850E/PH2 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation. It uses the V850E1 CPU (NU85EFC) of the V850 Series including single-precision floating point unit, and has on-chip ROM, RAM, bus interface, DMA controller, a realtime pulse unit including 3-phase PWM timer for inverter control, various serial interfaces including AFCAN, and peripheral facilities such as A/D converters, as well as an on-chip debug interface.

(1) V850E1 CPU

The V850E1 CPU (NU85EFC) supports a RISC instruction set that enhances the performance of the V850 CPU, which is the CPU core integrated in the V850 Series, and has added instructions supporting high-level languages, such as C-language switch statement processing, table look-up branching, stack frame creation/deletion, and data conversion. This enhances the performance of both data processing and control. It is possible to use the software resources of the V850 CPU integrated system since the instruction codes of the V850E1 are upwardly compatible at the object code level with those of the V850 CPU. In addition, the V850E1 CPU (NU85EFC) incorporates a single-precision floating point unit, which supports high speed floating point arithmetic operations.

(2) External memory interface function

The V850E/PH2 microcontroller features n on-chip external memory interface including separately configured address (22 bits) and data (32 bits) buses. SRAM and ROM can be connected.

(3) On-chip flash memory

The V850E/PH2 microcontroller has a quickly accessible flash memory on-chip, that can shorten system development time since it is possible to rewrite a program with the V850E/PH2 microcontroller mounted in an application system. Moreover, it can greatly improve maintain ability after system ships.

(4) A full range of development environment products

A development environment system that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyser, and other elements is also available.

Note: PHOENIX-F is the European name of the V850E/PH2 microcontroller.

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

1.2 Device Features

• Number of instructions: 96

• Instruction execution time: 15.625 ns (@ φ = 64 MHz)

• General-purpose registers: 32 bits × 32

• Instruction set: V850E1 CPU (NU85EFC)

(compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed) Single-precision floating point arithmetic operation Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format Signed load instructions

• Memory space: 64 MB linear address space (common program/data) Chip select output function: 4 spaces Memory block division function: 2, 4, or 8 MB/block Programmable wait function Idle state insertion function

Note1

• External bus interface

: 32-bit data bus (address/data separated)

22-bit address bus 4 programmable chip select areas 32-/16-/8-bit bus sizing function External wait function

• Internal memory: μPD70F3187 μPD70F3447

Flash ROM: 512 KB 384 KB RAM: 32 KB 24 KB

• Interrupts/exceptions: External interrupts: up to 14 (including NMI) Internal interrupts: up to 85 sources Exceptions: 1 source 8 programmable interrupt priority levels

Note1

• Memory access controller

: SRAM controller

• DMA controller: 8 channels Transfer mode: Single transfer Transfer units: 8 bits or 16 bits (depending on peripheral)

Maximum transfer count: 256 (2

)

Transfer target: internal RAM ↔ I/O Transfer request: On-chip peripheral I/O DMA transfer termination interrupt

• I/O lines: Input ports: 5 I/O ports: 137

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

• Timer: 16-bit timer for 3-phase PWM inverter control: 2 channels

16-bit up/down counter for 4-quadrant encoding: 1 channel 16-bit general purpose timers: 9 channels 16-bit general purpose timers with encoding capability:

2 channels

• Serial interfaces: Asynchronous serial interface (UARTC): 2 channels Clocked serial interface (CSIB): up to 2 channels

Note 2

Queued clocked serial interface (CSI3): up to 2 channels FCAN interface (AFCAN): up to 2 channels

Note 2

• A/D converters: 10-bit resolution

2 × 10 channels

• Random number generator: Automatic seed generation

Fips/Maurer test passing

• Clock generator: 16 MHz clock oscillator

4 fold PLL synthesizer for internal system clock

• Power save modes: HALT mode

Note 1

Note 2

• Auxiliary frequency output: Programmable by user software

• Supply voltage: 1.5 V (internal power supply, clock generator)

3.3 V (external I/O pins, A/D converter)

• Package 208-pin plastic LQFP (fine pitch) (28 × 28)

256-pin plastic BGA (21 × 21)

• CMOS technology

Notes: 1. Not available on μPD70F3447

2. Only 1 channel on μPD70F3447

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

1.3 Applications

The V850E/PH2 microcontroller is ideally suited for automotive applications, like electrical power steering and electric car control. It is also an excellent choice for other applications where a combination of general-purpose inverter control functions and CAN network support is required.

1.4 Ordering Information

Part Number Package

μPD70F3187GD-64-LML 208-pin plastic LQFP (fine pitch) (28 × 28) μPD70F3187GD(A1)-64-LML 208-pin plastic LQFP (fine pitch) (28 × 28) μPD70F3187GD(A2)-64-LML 208-pin plastic LQFP (fine pitch) (28 × 28) μPD70F3187F1(A2)-64-JN4 256-pin plastic BGA (21 × 21) μPD70F3447F1(A2)-64-JN4 256-pin plastic BGA (21 × 21)

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

1.5 Pin Configuration (Top View)

• 208-pin plastic LQFP (fine pitch) (28 × 28)

μPD70F3187GD-64-LML μPD70F3187GD(A1)-64-LML μPD70F3187GD(A2)-64-LML

Figure 1-1: Pin Configuration 208-pin Plastic LQFP

PAH5/A21

PCS4/CS4

PDL0/D0

PDL1/D1 PDL2/D2 PDL3/D3

DD35

SS35

PDL4/D4 PDL5/D5 PDL6/D6 PDL7/D7

SS14

DD14

PDL8/D8 PDL9/D9

PDL10/D10

PDL11/D11 PDL12/D12 PDL13/D13 PDL14/D14 PDL15/D15

DD36

SS36

PDH0/D16 PDH1/D17 PDH2/D18 PDH3/D19 PDH4/D20

PDH5/D21 PDH6/D22 PDH7/D23 PDH8/D24 PDH9/D25

PDH10/D26 PDH11/D27 PDH12/D28

DD15

SS15

PDH13/D29 PDH14/D30

PDH15/D31

DD37

SS37

PCM1

PCT5/WR

PCM6 PCM7

PCT4/RD

PCD2/BEN0

PCD3/BEN1

PCD4/BEN2

PAL15/A15

PAL14/A14

151

150

PAL12/A12

PAL13/A13

147

148

149

PCS1/CS1

144

146

145

PAL11/A11

PAL10/A10

141

143

142

140

139

PAH4/A20

PAH3/A19

PAH2/A18

PAH1/A17

PAH0/A16

156

155

154

153

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

152

DD34

SS34

PAL9/A9

PAL8/A8

PAL7/A7

PCS3/CS3

PAL6/A6

PAL5/A5

138

137

DD13

SS13

PAL4/A4

MODE0/FLMD0

136

135

133

134

PAL2/A2

PAL3/A3

131

132

PAL1/A1

PAL0/A0

130

129

PCS0/CS0

P42/SCKB0

P41/SOB0

128

127

126

P40/SIB0

P96/SCS313/SSB1

P95/SCS312/INTP11

P94/SCS311/INTP10

125

124

123

122

DD33

SS33

P84/SCS301/INTP7

P86/SCS303/SSB0

P83/SCS300/INTP6

P85/SCS302/INTP8

P93/SCS310/INTP9

116

118

115

117

119

120

121

P92/SCK31

P91/SO31

P90/SI31

112

113

114

P82/SCK30

P81/SO30

P80/SI30

109

110

111

P45/SCKB1

P44/SOB1

P43/SIB1

106

107

108

P33/TXDC1

105

104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

P32/RXDC1/INTP5 P31/TXDC0 P30/RXDC0/INTP4 P37/FCTXD1 P36/FCRXD1 P35/FCTXD0 P34/FCRXD0 V

SS32

DD32

P67/TOR17/TRTEVT1 P66/TOR16 P65/TOR15 P64/TOR14/TIR13 P63/TOR13/TIR12 V

SS12

DD12

DDO DDI DMS DRST DCK RESET CV

X1 X2 CV

P62/TOR12/TIR11 P61/TOR11/TIR10 P60/TOR10/TTRGR1 P57/TOR07 P56/TOR06 P55/TOR05 P54/TOR04 V

SS31

DD31

P53/TOR03 P52/TOR02 P51/TOR01 P50/TOR00 V

SS11

DD11

P102/TIUD0/TO0 P101/TCUD0/TICC01 P100/TCLR0/TICC00/TOP81 P75/TECRT1/AFO P74/TIT11/TEVTT0/TOT11/TENCT11 P73/TIT10/TTRGT0/TOT10/TENCT10 P72/TECRT0/INTP12 P71/TIT01/TTRGT1/TOT01/TENCT01 P70/TIT00/TEVTT1/TOT00/TENCT00 P27/TIP71/TEVTP6/TOP71 P26/TIP70/TTRGP6/TOP70

MODE2

PCM0/WAIT

PCD5/BEN3

MODE1/FLMD1

SS0

ANI01

ANI02

ANI05

ANI00

ANI03

ANI04

ANI06

ANI07

ANI08

ANI09

REF0

REF1

ANI15

ANI19

ANI18

ANI16

ANI17

User’s Manual U16580EE3V1UD00

ANI14

ANI13

ANI12

ANI11

ANI10

SS1

P00/NMI

P02/INTP1/ESO1

P01/INTP0/ESO0

SS10

DD10

P04/INTP3/ADTRG1

P03/INTP2/ADTRG0

P10/TIP00/TEVTP1/TOP00

P11/TIP01/TTRGP1/TOP01

P12/TIP10/TTRGP0/TOP10

DD30

SS30

P13/TIP11/TEVTP0/TOP11

P14/TIP20/TEVTP3/TOP20

P15/TIP21/TTRGP3/TOP21

P16/TIP30/TTRGP2/TOP30

P17/TIP31/TEVTP2/TOP31

P20/TIP40/TEVTP5/TOP40

P21/TIP41/TTRGP5/TOP41

P22/TIP50/TTRGP4/TOP50

P23/TIP51/TEVTP4/TOP51

P24/TIP60/TEVTP7/TOP60

P25/TIP61/TTRGP7/TOP61

• 256-pin plastic BGA (21 × 21)

μPD70F3187F1(A2)-JN4 μPD70F3447F1(A2)-JN4

Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 × 21)

Top View Bottom View

Chapter 1 Introduction

20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

ABCDEFGHJKLMNPRTUVWY

YWVUTRPNMLKJHGFEDCBA

Index markIndex mark

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (1/4)

Pin No Pin Function (Name) Pin No Pin Function (Name)

μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447

A1 NC NC B1 NC NC

A2 NC NC B2 NC NC

A3 PCT4/RD

A4 PCT5/WR PCT5 B4 PCD2/BEN0 PCD2

A5 PDH15/D31 PDH15 B5 PCM6 PCM6

A6 PDH13/D29 PDH13 B6 PCM1 PCM1

A7 PDH11/D27 PDH11 B7 PDH14/D30 PDH14

A8 PDH9/D25 PDH9 B8 PDH12/D28 PDH12

A9 PDH8/D24 PDH8 B9 PDH10/D26 PDH10

A10 PDH6/D22 PDH6 B10 PDH7/D23 PDH7

A11 PDH3/D19 PDH3 B11 PDH5/D21 PDH5

A12 PDH0/D16 PDH0 B12 PDH1/D17 PDH1

A13 PDL15/D15 PDL15 B13 PDL13/D13 PDL13

A14 PDL14/D14 PDL14 B14 PDL12/D12 PDL12

A15 PDL9/D9 PDL9 B15 PDL8/D8 PDL8

A16 PDL5/D5 PDL5 B16 PDL4/D4 PDL4

A17 PDL1/D1 PDL1 B17 PDL3/D3 PDL3

A18 PDL0/D0 PDL0 B18 PCS4/CS4

A19 NC NC B19 NC NC

A20 NC NC B20 NC NC

C1 AV

SS0

C2 MODE1 MODE1 D2 AV

C3 MODE2 MODE2 D3 AV

C4 PCD4/BEN2 PCD4 D4 PCM0/WAIT PCM0

C5 PCM7 PCM7 D5 PCD3/BEN1

C6 V

C7 V

C8 V

C9 V

SS37

SS15

C10 PDH4/D20 PDH4 D10 PDH2/D18 PDH2

C11 V

C12 V

SS36

C13 PDL11/D11 PDL11 D13 PDL10/D10 PDL10

C14 V

SS14

C15 PDL7/D7 PDL7 D15 PDL6/D6 PDL6

C16 V

C17 V

SS35

C18 PDL2/D2 PDL2 D18 PAH4/A20 PAH4

PCT4 B3 PCD5/BEN3 PCD5

PCS4

SS0

D1 AV

SS0

PCD3

SS37

SS15

SS36

SS14

SS35

D6 V

D7 V

D8 V

D9 V

D11 V

D12 V

D14 V

D16 V

D17 V

DD37

DD15

DD36

DD14

DD35

DD37

DD15

DD36

DD14

DD35

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (2/4)

Pin No Pin Function (Name) Pin No Pin Function (Name)

μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447

C19 PAH5/A21 PAH5 D19 PAH3/A19 PAH3

C20 NC NC D20 PAL14/A14 PAL14

E1 ANI00 ANI00 F1 ANI03 ANI03

E2 ANI02 ANI02 F2 ANI06 ANI06

E3 ANI01 ANI01 F3 ANI05 ANI05

E4 AV

SS0

E17 PAH0/A16 PAH0 F17 PAL12/A12 PAL12

E18 PAH2/A18 PAH2 F18 PAL15/A15 PAL15

E19 PAH1/A17 PAH1 F19 PAL13/A13 PAL13

E20 PCS3/CS3 PCS3 F20 PAL11/A11 PAL11

G1 ANI07 ANI07 H1 ANI18 ANI18

G2 ANI09 ANI09 H2 ANI19 ANI19

G3 ANI08 ANI08 H3 AV

G4 AV

G17 V

G18 V

REF0

DD34

SS34

G19 PCS1/CS1 PCS1 H19 PAL10/A10 PAL10

G20 PAL9/A9 PAL9 H20 PAL6/A6 PAL6

J1 ANI17 ANI17 K1 ANI13 ANI13

J2 ANI14 ANI14 K2 ANI10 ANI10

J3 ANI15 ANI15 K3 ANI11 ANI11

J4 ANI16 ANI16 K4 ANI12 ANI12

J17 PAL5/A5 PAL5 K17 V

J18 PAL8/A8 PAL8 K18 V

J19 PAL7/A7 PAL7 K19 PAL4/A4 PAL4

J20 MODE0 MODE0 K20 PAL2/A2 PAL2

L1 AV

L2 AV

L3 AV

L4 AV

L17 V

SS1

DD13

SS0

REF0

DD34

SS34

SS1

DD13

F4 ANI04 ANI04

REF1

DD34

SS34

DD13

SS13

H4 AV

H17 V

H18 V

REF1

DD34

SS34

DD13

SS13

M1 P01/INTP0/ESO0 P01/INTP0/ESO0

M2 P00/NMI P00/NMI

M3 V

M4 V

SS10

DD10

SS10

DD10

M17 P95/SCS312/INTP11P95/INTP11

L18 V

SS13

M18 PAL0 PAL0

L19 PAL3/A3 PAL3 M19 PCS0 PCS0

L20 PAL1/A1 PAL1 M20 P42/SCKB0 P42/SCKB0

N1 P02/INTP1/ESO1 P02/INTP1/ESO1 P1 P04/INTP3/

ADTRG1

N2 P03/INTP2/

ADTRG0

N3 V

SS10

P03/INTP2/ ADTRG0

SS10

P2 P10/TIP00/

TEVTP1/TOP00

P3 V

SS30

P04/INTP3/ ADTRG1

P10/TIP00/ TEVTP1/TOP00

SS30

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (3/4)

Pin No Pin Function (Name) Pin No Pin Function (Name)

μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447

N4 V

N17 V

N18 V

DD10

DD33

SS33

N19 P41/SOB0 P41/SOB0 P19 P96/SCS313/SSB1 P96

N20 P40/SIB0 P40/SIB0 P20 P94/SCS311/

R1 P11/TIP01/

TTRGP1/TOP01

R2 P12/TIP10/

TTRGP0/TOP10

R3 V

R4 V

SS30

DD30

R17 P83/SCS300/INTP6 P83/SCS300/INTP6 T17 P80/SI30 P80/SI30

R18 P86/SCS303/SSB0 P86/SCS303/SSB0 T18 P84/SCS301/INTP7 P84/SCS301/INTP7

R19 P93/SCS310/INTP9 P93/INTP9 T19 P90/SI31 P90

R20 P85/SCS302/INTP8 P85/SCS302/INTP8 T20 P91/SO31 P91

U1 P15/TIP21/

TTRGP3/TOP21

U2 P17/TIP31/

TEVTP2/TOP31

U3 P22/TIP50/

TTRGP4/TOP50

U4 P25/TIP61/

TTRGP7/TOP61

U5 P71/TIT01/TTRGT1/

TOT01/TENCT01

U6 P75 P75 V6 P102/TIUD1/TO1 P102

U7 V

U8 V

DD11

DD31

U9 P62/TOR12/TIR11 P62/TOR12/TIR11 V9 P61/TOR11/TIR10 P61/TOR11/TIR10

U10 V

SS31

U11 DCK DCK V11 RESET RESET

U12 V

U13 V

U14 V

U15 V

DD12

DD32

U16 P32/RXDC1/INTP5 P32/INTP5 V16 P67/TOR17/

U17 P81/SO30 P81/SO30 V17 P31/TXDC0 P31/TXDC0

U18 P82/SCK30

U19 P44/SOB1 P44 V19 P43/SIB1 P43

DD10

DD33

SS33

P4 V

P17 V

P18 V

DD30

DD33

SS33

DD30

DD33

SS33

P94/INTP10

INTP10

P11/TIP01/ TTRGP1/TOP01

P12/TIP10/ TTRGP0/TOP10

SS30

DD30

P15/TIP21/ TTRGP3/TOP21

P17/TIP31/ TEVTP2/TOP31

P22/TIP50/ TTRGP4/TOP50

P25/TIP61/ TTRGP7/TOP61

P71/TIT01/TTRGT1/ TOT01/TENCT01

DD11

DD31

SS31

DD12

DD32

T1 P13/TIP11/TEVTP0/

TOP11

T2 P14/TIP20/TEVTP3/

TOP20

T3 P16/TIP30/TTRGP2/

TOP30

T4 P21/TIP41/TTRGP5/

TOP41

V1 P20/TIP40/

TEVTP5/TOP40

V2 P23/TIP51/

TEVTP4/TOP51

V3 P24/TIP60/

TEVTP7/TOP60

V4 P70/TIT00/TEVTT1/

TOT00/TENCT00

V5 P74/TIT11/TEVTT0/

TOT11/TENCT11

V7 V

V8 V

V10 V

V12 V

V13 V

V14 V

V15 V

SS11

SS31

SS12

SS32

P13/TIP11/TEVTP0/ TOP11

P14/TIP20/TEVTP3/ TOP20

P16/TIP30/TTRGP2/ TOP30

P21/TIP41/TTRGP5/ TOP41

P20/TIP40/ TEVTP5/TOP40

P23/TIP51/ TEVTP4/TOP51

P24/TIP60/ TEVTP7/TOP60

P70/TIT00/TEVTT1/ TOT00/TENCT00

P74/TIT11/TEVTT0/ TOT11/TENCT11

SS11

SS31

SS12

SS32

P67/TOR17/

TEVTR1

P82/SCK30 V18 P30/RXDC0/INTP4 P30/RXDC0/INTP4

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (4/4)

Pin No Pin Function (Name) Pin No Pin Function (Name)

μPD70F3187 μPD70F3447 μPD70F3187 μPD70F3447

U20 P92/SCK31 P92 V20 P45/SCKB1 P45

W1 NC NC Y1 NC NC

W2 P26 P26 Y2 NC NC

W3 P27/TIP71/

TEVTP6/TOP71

W4 P73/TIT10/TTRGT0/

TOT10/TENCT10

W5 P101/TCUD1/

TICC11

W6 P51/TOR01 P51/TOR01 Y6 P52/TOR02 P52/TOR02

W7 P53/TOR03 P53/TOR03 Y7 P54/TOR04 P54/TOR04

W8 P55/TOR05 P55/TOR05 Y8 P56/TOR06 P56/TOR06

W9 P57/TOR07 P57/TOR07 Y9 P60/TOR10/TTRGR1P60/TOR10/TTRGR

W10 V

SS31

W11 X2 X2 Y11 CV

W12 X1 X1 Y12 CV

W13 DMS DMS Y13 DRST DRST

W14 DDO DDO Y14 DDI DDI

W15 P65/TOR15 P65/TOR15 Y15 P63/TOR13/TIR12 P63/TOR13/TIR12

W16 P66/TOR16 P66/TOR16 Y16 P64/TOR14/TIR13 P64/TOR14/TIR13

W17 P34/FCRXD0 P34/FCRXD0 Y17 P35/FCTXD0 P35/FCTXD0

W18 P36/FCRXD1 P36 Y18 P37/FCTXD1 P37

W19 P33/TXDC1 P33 Y19 NC NC

W20 NC NC Y20 NC NC

P27/TIP71/ TEVTP6/TOP71

P73/TIT10/TTRGT0/ TOT10/TENCT10

Y3 P72/TECRT0/

INTP12

Y4 P100/TCLR1/

TICC10/TOP81

P72/INTP12

P100/TOP81

P101 Y5 P50/TOR00 P50/TOR00

SS31

Y10 V

SS31

User’s Manual U16580EE3V1UD00

Pin Identification

Chapter 1 Introduction

A0 to A21: Address bus ADTRG0, ADTRG1: A/D trigger input AFO: Auxiliary frequency output ANI00 to ANI09, ANI10 to ANI19: Analog input

: Analog power supply

AV AV BEN0

CS0 CV

, AV

REF0

, AV

SS0

to BEN3: Byte enable

, CS1, CS3, CS4: Chip select

: Power supply for oscillator

: Oscillator ground

: Analog reference voltage

REF1

: Analog ground

SS1

D0 to D31: Data bus DCK: Debug clock input DDI: Debug data input DDO: Debug data output DMS: Debug mode select

: Debug reset

DRST ESO0, ESO1: Emergency shut-off FCRXD0, FCRXD1: FCAN receive data input FCTXD0, FCTXD1: FCAN transmit data output INTP0 to INTP12: External interrupt request MODE0 to MODE2: Mode NMI: Non-maskable interrupt

request NC: Not connected P00 to P04: Port 0 P10 to P17: Port 1 P20 to P27: Port 2 P30 to P37: Port 3 P40 to P45: Port 4 P50 to P57: Port 5 P60 to P67: Port 6 P70 to P75: Port 7 P80 to P86: Port 8 P90 to P96: Port 9 P100 to P102: Port 10 PAL0 to PAL15: Port AL PAH0 to PAH5: Port AH PCD2 to PCD5: Port CD PCM0, PCM1, PCM6, PCM7: Port CM PCS0, PCS1, PCS3, PCS4: Port CS PCT4, PCT5: Port CT PDL0 to PDL15: Port DH PDH0 to PDH15: Port DL

: Read strobe

RD RESET

: Reset RXDC0, RXDC1: Receive data input SCK30 SCKB0

, SCK31,

, SCKB1: Serial clock SCS300 to SCS303, SCS310 to SCS313: Serial chip select

SI30, SI31, SIB0, SIB1: Serial data input SO30, SO31, SOB0, SOB1: Serial data output SSB0, SSB1: Serial slave select input TCLR1: Timer clear TCUD1: Timer control pulse input TECRT0, TECRT1: Timer external clear TENCT00, TENCT01, TENCT10, TENCT11: Timer encoder input TEVTP0 to TEVTP7, TEVTR1, TEVTT0, TEVTT1: Timer event input TICC10, TICC11 TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31, TIP40, TIP41, TIP50, TIP51, TIP60, TIP61, TIP70, TIP71, TIR10 to TIR13, TIT00, TIT01, TIT10, TIT11: Timer input TIUD1: Timer count pulse input TO1, TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31, TOP40, TOP41, TOP50, TOP51, TOP60, TOP61, TOP70, TOP71, TOP81, TOR00 to TOR07, TOR10 to TOR17, TOT00, TOT01, TOT10, TOT11: Timer output TTRGP0 to TTRGP7, TTRGR1, TTRGT0, TTRGT1: Timer trigger input TXDC0, TXDC1: Transmit data output

to V

DD10

to V

DD30

to V

SS10

to V

SS30

: Wait

WAIT

: Write strobe

: Power supply for CPU

DD15

: I/O buffers power supply

DD37

: CPU Ground

SS15

: I/O buffers ground

SS37

X1, X2: Crystal

User’s Manual U16580EE3V1UD00

1.6 Function Blocks

1.6.1 Internal block diagrams

Figure 1-3: Internal Block Diagram of μPD70F3187

Chapter 1 Introduction

INTP0 to INTP12

TEVTP0 to TEVTP8

TTRGP0 to TTRGP8

TENCT00, TENCT01, TECRT0 TENCT10, TENCT11, TECRT1

TEVTT0,

TTRGT0,

TOR00 to TOR07 TOR10 to TOR17 TOP00 to TOP70 TOP01 1to TOP8

CSC300 to CSC303

CSC310 to CSC313

NMI

ESO0, ESO1

TTRGR1 TIR10 to TIR13 TIP00 to TIP70 TIP01 to TIP71

TIT00, TIT01 TIT10, TIT11

TEVTT1 TTRGT1

TICC10 TICC11

TCLR1

TCUD1,TIUD1

TOT00, TOT01 TOT10, TOT11

TO1

TXDC0

RXDC0

TXDC1

RXDC1

SOB0

SIB0

SCKB0

SSB0

SOB1

SIB1

SCKB1

SSB1

SO30

SI30

SCK30

SO31

SI31

SCK31

FCRXD0 FCTXD0

FCRXD1 FCTXD1

INTC

RPU

TMR: 2ch

TMP: 9ch

TMT: 2ch

TMENC10:1ch

UARTC0

UARTC1

CSIB0

BRG0

CSIB1

BRG1

CSI30

CSI31

FCAN0

FCAN1

ROM BCUCPU

512 KB

32-bit Barrel

Shifter

System

Registers

RAM

General

Registers

P40 to P45

P30 to P37

32-bit

x 32

P50 to P57

P60 to P67

AFO

P70 to P75

32 KB

DMAC

P00 to P04

P10 to P17

RNG

BRG2

P20 to P27

Floating Point

Multiplier

32 x 32

ALU

Por ts

P80 to P86

P90 to P96

P100 to P102

PCS0, PCS1, PCS3, PCS4

Instruction

Queue

Unit

PCT4, PCT5

PAH0 to PAH5

PAL0 to PAL15

PCD2 to PCD5

PCM0, PCM1, PCM6, PCM7

PDL0 to PDL15

PDH0 to PDH15

MEMC

SRAM

ROM

DCU

A/D

Converter 0

A/D

Converter 1

Clock

Generator

& System Control

RD WR

WAIT

BE0 BE3to

CS0 CS1, CS3 CS4,

D0 to D31

A0 to A21

DCK, DMS DDI, DDO DRST

ANI00 to ANI09

ADTRG0 AV

AVSS0

REF

ANI10 to ANI19

ADTRG1 AV

AVSS1

REF

RESET

MODEn

X1 X2

DD1

SS1

DD3

SS3

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

Figure 1-4: Internal Block Diagram of μPD70F3447

INTP0 to INTP12

TEVTP0 to TEVTP8

TTRGP0 to TTRGP8

TEVTT0,

TTRGT0,

TOR00 to TOR07 TOR10 to TOR17

TOP00 to TOP70 TOP01 1to TOP8

CSC300 to CSC303

NMI

ESO0, ESO1

TTRGR1

TIR10 to TIR13

TIP00 to TIP70 TIP01 to TIP71

TIT00, TIT01 TIT10, TIT11

TECRT0 TECRT1 TEVTT1

TTRGT1

TOT00, TOT01 TOT10, TOT11

TXDC0 RXDC0

TXDC1

RXDC1

SOB0

SIB0

SCKB0

SSB0

SO30

SI30

SCK30

FCRXD0

FCTXD0

INTC

RPU

TMR: 2ch

TMP: 9ch

TMT: 2ch

UARTC0

UARTC1

CSIB0

BRG0

BRG1

CSI30

FCAN0

ROM CPU

384 KB

32-bit Barrel Shifter

System

Registers

RAM

General

Registers

P40 to P45

P30 to P37

32-bit

x 32

P50 to P57

P60 to P67

AFO

P70 to P75

24 KB

DMAC

P00 to P04

P10 to P17

BRG2

P20 to P27

Por ts

P80 to P86

P90 to P96

Floating Point

Multiplier

32 x 32

ALU

P100 to P102

BCU

Instruction

Queue

Unit

PCT4, PCT5

PAH0 to PAH5

PAL0 to PAL15

PCD2 to PCD5

PDH0 to PDH15

PCS0, PCS1, PCS3, PCS4

PCM0, PCM1, PCM6, PCM7

PDL0 to PDL15

DCU

A/D

Converter 0

A/D

Converter 1

Clock

Generator

& System Control

DCK, DMS DDI, DDO DRST

ANI00 to ANI09

ADTRG0 AV

AVSS0

REF

ANI10 to ANI19

ADTRG1

AV AVSS1 AV

REF

RESET

MODEn

X1 X2

DD1

SS1

DD3

SS3

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

1.6.2 On-chip units

(1) CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits or 32 bits

× 32 bits → 64 bits) and a barrel shifter (32 bits), help accelerate processing of complex

instructions.

(2) Bus control unit (BCU)

The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue in the CPU. The BCU controls a memory controller (MEMC) and DMA controller (DMAC) and performs external memory access and DMA transfer.

(a) Memory controller (MEMC)

Note2

The MEMC controls SRAM, ROM, and various I/O for external memory expansion.

• SRAM, external ROM, external I/O interface Supports access to SRAM, external ROM, and external I/O.

(b) DMA controller (DMAC)

The DMAC performs data transfers b/w internal on-chip RAM and peripheral I/O. For this purpose eight DMA channels are provided for particular transfer functions of serial I/O interfaces, real-time pulse unit (TMR), and A/D converter.

(3) ROM

There is on-chip flash memory of 512 KB provided in the μPD70F3187, and 384 KB in the μPD70F3447.

On an instruction fetch, the ROM can be accessed by the CPU in one clock. When single-chip mode 0 or flash memory programming mode is set, ROM is mapped starting from address 00000000H.

Note2

When single-chip mode 1 ROM cannot be accessed if ROM-less mode

is set, it is mapped starting from address 00100000H.

Note2

is set.

(4) RAM

There is on-chip RAM of 32 KB provided in the μPD70F3187, and 24 KB in the μPD70F3447. Onchip RAM is mapped starting from address 03FF0000H for both, μPD70F3187 and μPD70F3447. It can be accessed by the CPU in one clock on an instruction fetch or data access.

(5) Interrupt controller (INTC)

The INTC services hardware interrupt requests from on-chip peripheral I/O and external sources (NMI, INTP0 to INTP12). Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple-interrupt servicing control can be performed for interrupt sources

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

(6) Clock generator (CG)

The CG provides a frequency that is 4 times the input clock (f internal system clock (f

). As the input clock, connect an external crystal or resonator to pins X1

CPU

) (using the on-chip PLL) as the

and X2 or input an external clock from the X1 pin.

(7) Real-time pulse unit (RPU)

The RPU incorporates a 2-channel 16-bit timer (TMR) for 3/6-phase sine wave PWM inverter

control, an 1-channel 16-bit up/down counter (TMENC10), μPD70F3187 only and a 2-channel

16-bit up/down counter (TMT) that can be used for 2-phase encoder input or as a general-purpose timer, a 9-channel 16-bit general-purpose timer unit (TMP). The RPU can measure pulse interval or frequency and can output programmable pulses.

(8) Serial interface (SIO)

The serial interfaces consist of 2 channels asynchronous serial interface C (UARTC), up to 2 channels clocked serial interface B (CSIB), up to 2 channels clocked serial interface 3 (CSI3), and up to 2 channels FCAN interface (AFCAN). The UARTC performs data transfer using pins TXDCn and RXDCn (n = 0, 1).

The CSIB performs data transfer using pins SOBn, SIBn, SCKBn

The CSI3 performs data transfer using pins SO3n, SI3n, SCK3n

, SSIn, and SSOn

, SCS3n0 to SCS3

The AFCAN performs data transfer using pins FCTXDn and FCRXDn

Note1

(9) Baud rate generator (BRG)

The baud rate generator comprises 3 channels of 8-bit counters and comparators that can be used for clock supply of serial interfaces (CSIB), auxiliary frequency output (AFO) or interval timer.

(10) A/D converter (ADC)

The two units of high-speed, high-resolution 10-bit A/D converter include 10 analog input pins for each unit. Conversion is performed using the successive approximation method.

(11) Random number generator (RNG)

For encryption purpose a random number generator is provided.

(12) Debug control unit (DCU)

On-chip debugging can be performed via a debug control unit (n-wire interface).

Notes: 1. n = 0, 1 for μPD70F3187

n = 0 for μPD70F3447

2. Not available on µPD70F3447

User’s Manual U16580EE3V1UD00

Chapter 1 Introduction

(13) Ports

As shown below, the following ports have general-purpose port functions and control pin functions.

Port I/O Control Function

μPD70F3187 μPD70F3447

Port 0 5-bit input NMI input, external interrupt input, A/D converter external trigger input,

emergency shut-off input

Port 1 8-bit I/O Real-time pulse unit I/O

Port 2 8-bit I/O Real-time pulse unit I/O

Port 3 8-bit I/O Serial interface I/O, external interrupt input

Port 4 6-bit I/O Serial interface I/O

Port 5 8-bit I/O Real-time pulse unit I/O

Port 6 8-bit I/O Real-time pulse unit I/O

Port 7 6-bit I/O Real-time pulse unit I/O, external interrupt input

Port 8 7-bit I/O Serial interface I/O, external interrupt input

Port 9 7-bit I/O Serial interface I/O, external interrupt

input

Port 10 3-bit I/O Real-time pulse unit I/O

Port AL 16-bit I/O External address bus None

Port AH 6-bit I/O External address bus None

Port DL 16-bit I/O External data bus None

Port DH 16-bit I/O External data bus None

Port CD 4-bit I/O External bus interface control signal

output

Port CM 4-bit I/O Wait insertion signal input None

Port CS 4-bit I/O External bus interface control signal

output

Port CT 2-bit I/O External bus interface control signal

output

External interrupt input

None

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

2.1 List of Pin Functions

The names and functions of the V850E/PH2 microcontroller pins are listed below. These pins can be divided into port pins and non-port pins according to their functions.

(1) Port pins

Table 2-1: Port Pins (1/5)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

P00 I Port 0

P01 INTP0, ESO0

P02 INTP1, ESO1

P03 INTP2, ADTRG0

P04 INTP3, ADTRG1

P10 I/O Port 1

P11 TIP01, TTRGP1, TOP01

P12 TIP10, TTRGP0, TOP10

P13 TIP11, TEVTP0, TOP11

P14 TIP20, TEVTP3, TOP20

P15 TIP21, TTRGP3, TOP21

P16 TIP30, TTRGP2, TOP30

P17 TIP31, TEVTP2, TOP31

P20 I/O Port 2

P21 TIP41, TTRGP5, TOP41

P22 TIP50, TTRGP4, TOP50

P23 TIP51, TEVTP4, TOP51

P24 TIP60, TEVTP7, TOP60

P25 TIP61, TTRGP7, TOP61

P26 TIP70, TTRGP6, TOP70

P27 TIP71, TEVTP6, TOP71

P30 I/O Port 3

P31 TXDC0

P32 RXDC1, INTP5

P33 TXDC1

P34 FCRXD0

P35 FCTXD0

P36 FCRXD1 –

P37 FCTXD1 –

5-bit input-only port

8-bit I/O port Input or output direction can be specified in 1-bit units

NMI

TIP00, TEVTP1, TOP00

TIP40, TEVTP5, TOP40

RXDC0, INTP4

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-1: Port Pins (2/5)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

P40 I/O Port 4

P41 SOB0

P42 SCKB0

P43 SIB1 –

P44 SOB1 –

P45 SCKB1

P50 I/O Port 5

P51 TOR01

P52 TOR02

P53 TOR03

P54 TOR04

P55 TOR05

P56 TOR06

P57 TOR07

P60 I/O Port 6

P61 TOR11, TIR10

P62 TOR12, TIR11

P63 TOR13, TIR12

P64 TOR14, TIR13

P65 TOR15

P66 TOR16

P67 TOR17, TEVTR1

P70 I/O Port 7

P71 TIT01, TTRGT1, TOT01, TENCT01

P72 TECRT0, INTP12

P73 TIT10, TTRGT0, TOT10, TENCT10

P74 TIT11, TEVTT0, TOT11, TENCT11

P75 TECRT1, AFO

P80 I/O Port 8

P81 SO30

P82 SCK30

P83 SCS300, INTP6

P84 SCS301, INTP7

P85 SCS302, INTP8

P86 SCS303, SSB0

6-bit I/O port Input or output direction can be specified in 1-bit units

8-bit I/O port Input or output direction can be specified in 1-bit units

6-bit I/O port Input or output direction can be specified in 1-bit units

7-bit I/O port Input or output direction can be specified in 1-bit units

SIB0

–

TOR00

TOR10, TTRGR1

TIT00, TEVTT1, TOT00, TENCT00

SI30

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-1: Port Pins (3/5)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

P90 I/O Port 9

P91 SO31 –

P92 SCK31

P93 SCS310, INTP9 INTP9

P94 SCS311, INTP10 INTP10

P95 SCS312, INTP11 INTP11

P96 SCS313, SSB1

P100 I/O Port 10

P101 TCUD1, TICC11 –

P102 TIUD1, TO1 –

PA L 0 I / O Por t A L

PA L1 A 1

PA L2 A 2

PA L3 A 3

PA L4 A 4

PA L5 A 5

PA L6 A 6

PA L7 A 7

PA L8 A 8

PA L9 A 9

PAL10 A10

PAL11 A11

PAL12 A12

PAL13 A13

PAL14 A14

PAL15 A15

PA H 0 I / O P o r t A H

PA H1 A1 7

PA H2 A1 8

PA H3 A1 9

PA H4 A2 0

PA H5 A2 1

7-bit I/O port Input or output direction can be specified in 1-bit units

3-bit I/O port Input or output direction can be specified in 1-bit units

16-bit I/O port Input or output direction can be specified in 1-bit units

6-bit I/O port Input or output direction can be specified in 1-bit units

SI31 –

TCLR1, TICC10, TOP81

A0 –

A16 –

–

TOP81

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-1: Port Pins (4/5)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

PDL0 I/O Port DL

PDL1 D1

PDL2 D2

PDL3 D3

PDL4 D4

PDL5 D5

PDL6 D6

PDL7 D7

PDL8 D8

PDL9 D9

PDL10 D10

PDL11 D11

PDL12 D12

PDL13 D13

PDL14 D14

PDL15 D15

PDH0 I/O Port DH

PDH1 D17

PDH2 D18

PDH3 D19

PDH4 D20

PDH5 D21

PDH6 D22

PDH7 D23

PDH8 D24

PDH9 D25

PDH10 D26

PDH11 D27

PDH12 D28

PDH13 D29

PDH14 D30

PDH15 D31

PCD2 I/O Port CD

PCD3 BEN1

PCD4 BEN2

PCD5 BEN3

16-bit I/O port Input or output direction can be specified in 1-bit units

4-bit I/O port Input or output direction can be specified in 1-bit units

D0 –

D16 –

BEN0

–

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-1: Port Pins (5/5)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

PCM0 I/O Port CM

PCM1 –

PCM6 –

PCM7 –

PCS0 I/O Port CS

PCS1 CS1

PCS3 CS3

PCS4 CS4

PCT4 I/O Port CT

PCT5 WR

4-bit I/O port Input or output direction can be specified in 1-bit units

2-bit I/O port Input or output direction can be specified in 1-bit units

WAIT –

CS0

RD –

–

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(2) Non-port pins

Table 2-2: Non-Port Pins (1/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

A0 to A15

A16 to A21

Note

O 22-bit external address bus PAL0 to PAL15

PAH0 to PAH5

ADTRG0 I A/D conversion start trigger (ADC0) P03, INTP2

ADTRG1 I A/D conversion start trigger (ADC1) P04, INTP3

AFO O Auxiliary frequency output P75, TECRT1

ANI00 to ANI09 I Analog input channels (ADC0) –

ANI10 to ANI19 I Analog input channels (ADC1) –

REF0

REF1

SS0

SS1

Note

BEN0

Note

BEN1

Note

BEN2

Note

BEN3

Note

CS0

Note

CS1

Note

CS3

Note

CS4

D0 to D15

D16 to D31

Note

Positive power supply (3.3 V) (ADC0, ADC1) –

–

I Reference voltage input (ADC0) –

I Reference voltage input (ADC1) –

Power supply ground (ADC0) –

–

Power supply ground (ADC1) –

–

O External byte enable output PCD2

PCD3

PCD4

PCD5

O Chip select signal output PCS0

PCS1

PCS3

PCS4

Oscillator power supply (1.5 V) –

–

Oscillator power supply ground –

–

I/O 32-bit external data bus PDL0 to PDL15

PDH0 to PDH15

DCK I N-wire interface clock –

DDI I N-wire data input and reset mode selection –

DDO O N-wire data output –

DMS I N-wire mode select –

DRST

I N-wire interface reset –

ESO0 I Emergency shut off input (TMR0) INTP0, P01

ESO1 I Emergency shut off input (TMR1) INTP1, P02

FCRXD0 I Receive input (AFCAN0) P34

FCRXD1

Note

I Receive input (AFCAN1) P36

FCTXD0 O Transmit output (AFCAN0) P35

FCTXD1

Note

O Transmit output (AFCAN1) P37

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-2: Non-Port Pins (2/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

FLMD0 I Flash programming mode selection MODE0

FLMD1 MODE1

INTP0 I External maskable interrupt request input P01, ESO0

INTP1 P02, ESO1

INTP2 P03, ADTRG0

INTP3 P04, ADTRG1

INTP4 P30, RXDC0

INTP5 P32, RXDC1 P32

INTP6 P83, SCS300

INTP7 P84, SCS301

INTP8 P85, SCS302

INTP9 P93, SCS310 P93

INTP10 P94, SCS311 P94

INTP11 P95, SCS312 P95

INTP12 P72, TECRT0

MODE0 I Device operating mode selection FLMD0

MODE1 FLMD1

MODE2 –

NMI I Non-maskable interrupt request input P00

Note

RESET I System reset input –

RXDC0 I Receive input (UARTC0) P30, INTP4

RXDC1 I Receive input (UARTC1) P32, INTP5

SCK30

Note

SCK31

SCKB0

Note

SCKB1

SCS300 O Serial peripheral chip select (CSI30) P83, INTP7

SCS301 P84, INTP8

SCS302 P85, INTP9

SCS303 P86, SSB0

SCS310

SCS311

SCS312

SCS313

Note

SI30 I Serial data input (CSI30) P80

Note

SI31

SIB0 I Serial data input (CSIB0) P40

O Read strobe signal output PCT4

I/O Serial shift clock I/O (CSI30) P82

I/O Serial shift clock I/O (CSI31) P92

I/O Serial shift clock I/O (CSIB0) P42

I/O Serial shift clock I/O (CSIB1) P45

O Serial peripheral chip select (CSI31) P93, INTP10

P94, INTP10

P95, INTP11

P96, SSB1 P96

I Serial data input (CSI31) P90

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-2: Non-Port Pins (3/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

SIB1

Note

I Serial data input (CSIB1) P43

SO30 O Serial data output (CSI30) P81

SO31 O Serial data output (CSI31) P91

SOB0 O Serial data output (CSIB0) P41

SOB1 O Serial data output (CSIB1) P44

SSB0

SSB1

TCLR1

Note

I Serial slave select input (CSIB0) P86, SCS303

I Serial slave select input (CSIB1) P96, SCS313 P96

I Timer clear input (TMENC10) P100, TICC10,

P100, TOP81

TOP81

TCUD1

Note

I Count up/down direction control input

P101, TICC11 P101

(TMENC10)

TECRT0 I Timer clear input (TMT0) P72, INTP12

TECRT1 I Timer clear input (TMT1) P75, AFO

TENCT00 I Timer encoder input (TMT0) P70, TIT00, TEVTT1, TOT00

TENCT01 I P71, TIT01, TTRGT1, TOT01

TENCT10 I Timer encoder input (TMT1) P73, TIT10, TTRGT0, TOT10

TENCT11 I P74, TIT11, TEVTT0, TOT11

TEVTP0 I Timer event input (TMP0) P13, TIP11, TOP11

TEVTP1 I Timer event input (TMP1) P10, TIP00, TOP00

TEVTP2 I Timer event input (TMP2) P17, TIP31, TOP31

TEVTP3 I Timer event input (TMP3) P14, TIP20, TOP20

TEVTP4 I Timer event input (TMP4) P23, TIP51, TOP51

TEVTP5 I Timer event input (TMP5) P20, TIP40, TOP40

TEVTP6 I Timer event input (TMP6) P27, TIP71, TOP71

TEVTP7 I Timer event input (TMP7) P24, TIP60, TOP60

TEVTR1 I Timer event input (TMR1) P67, TOR17

TEVTT0 I Timer event input (TMT0) P74,TIT11, TOT11, TENCT11

TEVTT1 I Timer event input (TMT1) P70, TIT00, TOT00, TENCT00

TICC10

Note

I TMENC10 capture trigger input P100, TCLR1,

P100, TOP81

TOP81

TICC11

Note

P101, TCUD1 P101

TIP00 I Capture trigger input (TMP0) P10, TEVTP1, TOP00

TIP01 P11, TTRGP1, TOP01

TIP10 I Capture trigger input (TMP1) P12, TTRGP0, TOP10

TIP11 P13, TEVTP0, TOP11

TIP20 I Capture trigger input (TMP2) P14, TEVTP3, TOP20

TIP21 P15, TTRGP3, TOP21

TIP30 I Capture trigger input (TMP3) P16, TTRGP2, TOP30

TIP31 P17, TEVTP2, TOP31

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Chapter 2 Pin Functions

Table 2-2: Non-Port Pins (4/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

TIP40 I Capture trigger input (TMP4) P20, TEVTP5, TOP40

TIP41 P21, TTRGP5, TOP41

TIP50 I Capture trigger input (TMP5) P22, TTRGP4, TOP50

TIP51 P23, TEVTP4, TOP51

TIP60 I Capture trigger input (TMP6) P24, TEVTP7, TOP60

TIP61 P25, TTRGP7, TOP61

TIP70 I Capture trigger input (TMP7) P26, TTRGP6, TOP70

TIP71 P27, TEVTP6, TOP71

TIR10 I Capture trigger input (TMR1) P61, TOR11

TIR11 P62, TOR12

TIR12 P63, TOR13

TIR13 P64, TOR14

TIT00 I Capture trigger input (TMT0) P70, TEVTT1, TOT00, TENCT00

TIT01 P71, TTRGT1, TOT01, TENCT01

TIT10 I Capture trigger input (TMT0) P73, TTRGT0, TOT10, TENCT10

TIT11 P74,TEVTT0, TOT11, TENCT11

Note

TIUD1

Note

TO1

TOP00 O Pulse signal output (TMP0) P10, TIP00, TEVTP1

TOP01 P11, TIP01, TTRGP1

TOP10 O Pulse signal output (TMP1) P12, TIP10, TTRGP0

TOP11 P13, TIP11, TEVTP0

TOP20 O Pulse signal output (TMP2) P14, TIP20, TEVTP3

TOP21 P15, TIP21, TTRGP3

TOP30 O Pulse signal output (TMP3) P16, TIP30, TTRGP2

TOP31 P17, TIP31, TEVTP2

TOP40 O Pulse signal output (TMP4) P20, TIP40, TEVTP5

TOP41 P21, TIP41, TTRGP5

TOP50 O Pulse signal output (TMP5) P22, TIP50, TTRGP4

TOP51 P23, TIP51, TEVTP4

TOP60 O Pulse signal output (TMP6) P24, TIP60, TEVTP7

TOP61 P25, TIP61, TTRGP7

TOP70 O Pulse signal output (TMP7) P26, TIP70, TTRGP6

TOP71 P27, TIP71, TEVTP6

TOP81 O Pulse signal output (TMP8) P100, TCLR1,

I External count clock input (TMENC10) P102, TO1 P102

O Pulse signal output (TMENC10) P102, TIUD1 P102

P100

TICC10

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Table 2-2: Non-Port Pins (5/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

TOR00 O Pulse signal output (TMR0) P50

TOR01 P51

TOR02 P52

TOR03 P53

TOR04 P54

TOR05 P55

TOR06 P56

TOR07 P57

TOR10 O Pulse signal output (TMR1) P60, TTRGR1

TOR11 P61, TIR10

TOR12 P62, TIR11

TOR13 P63, TIR12

TOR14 P64, TIR13

TOR15 P65

TOR16 P66

TOR17 P67, TEVTR1

TOT00 O Pulse signal output (TMT0) P70, TIT00, TEVTT1, TENCT00

TOT01 P71, TIT01, TTRGT1, TENCT01

TOT10 O Pulse signal output (TMT1) P73, TIT10, TTRGT0, TENCT10

TOT11 P74,TIT11, TEVTT0, TENCT11

TTRGP0 I Timer trigger input (TMP0) P12, TIP10, TOP10

TTRGP1 Timer trigger input (TMP1) P11, TIP01, TOP01

TTRGP2 Timer trigger input (TMP2) P16, TIP30, TOP30

TTRGP3 Timer trigger input (TMP3) P15, TIP21, TOP21

TTRGP4 Timer trigger input (TMP4) P22, TIP50, TOP50

TTRGP5 Timer trigger input (TMP5) P21, TIP41, TOP41

TTRGP6 Timer trigger input (TMP6) P26, TIP70, TOP70

TTRGP7 Timer trigger input (TMP7) P25, TIP61, TOP61

TTRGR1 I Timer trigger input (TMR1) P60, TOR10

TTRGT0 I Timer trigger input (TMT0) P73, TIT10, TOT10, TENCT10

TTRGT1 I Timer trigger input (TMT1) P71, TIT01, TOT01, TENCT01

TXDC0 O Transmit output (UARTC0) P31

TXDC1 O Transmit output (UARTC1) P33

DD10

to V

DD15

Positive power supply for internal CPU (1.5 V)–

–

DD30

SS10

SS30

to V

DD37

SS15

SS37

Positive power supply for peripheral interface

–

(3.3 V)

Power supply ground for internal CPU –

–

Power supply ground for peripheral interface –

–

User’s Manual U16580EE3V1UD00

–

Chapter 2 Pin Functions

Table 2-2: Non-Port Pins (6/6)

Pin Name I/O Function Alternate Function

μPD70F3187 μPD70F3447

Note

WAIT

Note

X1 I Crystal connection –

I External wait control signal input PCM0

O Write strobe signal output PCT5

–

Note: Not available on μPD70F3447

–

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

2.2 Pin Status

Table 2-3: Pin Status in Reset and Standby Mode

Operating Status

During

reset

A0 to A15 (PAL0 to PAL15) Hi-Z Hi-Z Operating Operating

A16 to A21 (PAH0 to PAH5) Hi-Z Hi-Z Operating Operating

D0 to D15 (PDL0 to PDL15) Hi-Z Hi-Z Operating Operating

D16 to D31 (PDH0 to PDH15) Hi-Z Hi-Z Operating Operating

BEN0

to BEN3 (PCD2 to PCD5) Hi-Z Hi-Z Operating Operating

CS0

(PCS0) Hi-Z Hi-Z Operating Operating

CS1 (PCS1) Hi-Z Hi-Z Operating Operating

CS3 (PCS3) Hi-Z Hi-Z Operating Operating

CS4 (PCS4) Hi-Z Hi-Z Operating Operating

(PCT4) Hi-Z Hi-Z Operating Operating

WR (PCT5) Hi-Z Hi-Z Operating Operating

WAIT (PCM0) Hi-Z Hi-Z Operating Operating

PCM1, PCM6, PCM7 Hi-Z Hi-Z Hi-Z Operating

DCK Operating Operating Operating Operating

DDI Operating Operating Operating Operating

DDO Operating Operating Operating Operating

DMS Operating Operating Operating Operating

DRST

INTP0 to INTP3 (P01 to P04)

INTP4 (P30)

INTP5 (P32)

INTP6 to INTP8 (P83 to P85)

INTP9 to INTP11 (P93 to P95)

NMI (P00)

Peripheral input pin other than above

Peripheral output pin other than above

Port input pin other than above Hi-Z Hi-Z Hi-Z

Port output pin other than above ×× × Hold

Operating Operating Operating Operating

–

Hi-Z Hi-Z Hi-Z Operating

×× × Operating

Single-chip

Mode 0

After reset release HALT Mode

Single-chip

Mode 1

Input Input Operating

Note

ROM-less

Note

Mode

–

Remark: Hi-Z: High Impedance

–: Input data is not sampled ×: No function selected at reset

Note: Not available on μPD70F3447

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

2.3 Description of Pin Functions

(1) P00 to P04 (Port 0) … Input

Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as a port, in control mode, P00 to P04 operate as NMI input, external interrupt request signal, real-time pulse unit (RPU) emergency shut off signal input, and A/D converter (ADC) external trigger input. Normally, if function pins also serve as ports, one mode or the other is selected using a port mode control register. However, there is no such register for P00 to P04. Therefore, the input port cannot be switched with the NMI input pin, external interrupt request input pin, RPU emergency shut off signal input pin, and A/D converter (ADC) external trigger input pin. Read the status of each pin by reading the port.

(a) Port mode

P00 to P04 are input-only.

(b) Control mode

P00 to P04 also serve as NMI, INTP0 to INTP3, ESO0, ESO1, ADTRG0, and ADTRG1 pins, but the control function cannot be disabled.

(i) NMI (Non-maskable interrupt request) … Input

This is non-maskable interrupt request input.

(ii) INTP0 to INTP3 (Interrupt request from peripherals) … Input

These are external interrupt request input pins.

(iii) ESO0, ESO1 (Emergency shut off) … Input

These pins input timer TMR0 and timer TMR1 emergency shut off signals.

(iv) ADTRG0, ADTRG1 (A/D trigger input) … Input

These are A/D converter external trigger input pins.

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Chapter 2 Pin Functions

(2) P10 to P17 (Port 1) … Input/Output

Port 1 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P10 to P17 operate as RPU input or output. The operation mode can be specified by the port 1 mode control register (PMC1) to port or control mode for each port pin individually.

(a) Port mode

P10 to P17 can be set to input or output in 1-bit units using the port 1 mode register (PM1).

(b) Control mode

P10 to P17 can be set to port or control mode in 1-bit units using the PMC1 register.

(i) TIP00, TIP01, TIP10, TIP11, TIP20, TIP21, TIP30, TIP31 (Timer capture input) … Input

These are timer TMP0 to TMP3 capture trigger input pins.

(ii) TEVTP0, TEVTP1, TEVTP2, TEVTP3 (Timer event input) … Input

These are timer TMP0 to TMP3 external event counter input pins.

(iii) TTRGP0, TTRGP1, TTRGP2, TTRGP3 (Timer trigger) … Input

These are timer TMP0 to TMP3 external trigger input pins.

(iv) TOP00, TOP01, TOP10, TOP11, TOP20, TOP21, TOP30, TOP31 (Timer output) …

Output

These pins output timer TMP0 to TMP3 pulse signals.

(3) P20 to P27 (Port 2) … Input/Output

Port 2 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P20 to P27 operate as RPU input or output. The operation mode can be specified by the port 2 mode control register (PMC2) to port or control mode for each port pin individually.

(a) Port mode

P20 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2).

(b) Control mode

P20 to P27 can be set to port or control mode in 1-bit units using the PMC2 register.

(i) TIP40, TIP41, TIP50, TIP51, TIP60, TIP61, TIP70, TIP71 (Timer capture input) … Input

These are timer TMP4 to TMP7 capture trigger input pins.

(ii) TEVTP4, TEVTP5, TEVTP6, TEVTP7 (Timer event input) … Input

These are timer TMP4 to TMP7 external event counter input pins.

(iii) TTRGP4, TTRGP5, TTRGP6, TTRGP7 (Timer trigger) … Input

These are timer TMP4 to TMP7 external trigger input pins.

(iv) TOP40, TOP41, TOP50, TOP51, TOP60, TOP61, TOP70, TOIP71 (Timer output) … Out-

put

These pins output timer TMP4 to TMP7 pulse signals.

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(4) P30 to P37 (Port 3) … Input/Output

Port 3 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface

Note

(UARTC0, UARTC1, AFCAN0, AFCAN1

). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 3 mode control register (PMC3) to port or control mode for each port pin individually.

(a) Port mode

P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3).

(i) INTP4, INTP5 (Interrupt request from peripherals) … Input

These are external interrupt request input pins, which are simultaneously enabled in port input mode.

(b) Control mode

P30 to P37 can be set to port or control mode in 1-bit units using the PMC3 register.

(i) TXDC0, TXDC1 (Transmit data) … Output

These pins output serial transmit data of UARTC0 and UARTC1.

(ii) RXDC0, RXDC1 (Receive data) … Input

These pins input serial receive data of UARTC0 and UARTC1.

Note

(iii) FCTXD0, FCTXD1

(Transmit data for controller area network) … Output

These pins output AFCAN0 and AFCAN1

(iv) FCRXD 0, FCRXD1

Note

These pins input AFCAN0 and AFCAN1

Note: Not available on μPD70F3447

Note

serial transmit data.

(Receive data for controller area network) … Input

Note

serial receive data.

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(5) P40 to P45 (Port 10) … Input/Output

Port 4 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P40 to P45 operate as serial interface (CSIB0,

Note

CSIB1

). The operation mode can be specified by the port 4 mode control register (PMC4) to port or control mode for each port pin individually.

(a) Port mode

P40 to P45 can be set to input or output in 1-bit units using the port 4 mode register (PM4).

(b) Control mode

P40 to P45 can be set to port or control mode in 1-bit units using the PMC4 register.

Note

(i) SOB0, SOB1

These pins output CSIB0 and CSIB1

(ii) SIB0, SIB1

These pins input CSIB0 and CSIB1

(Serial output) … Output

Note

(Serial input) … Input

Note

serial transmit data.

Note

serial receive data.

(iii) SCKB0

, SCKB1

Note

(Serial clock) … I/O

These are the CSIB0 and CSIB1

Note: Not available on μPD70F3447

Note

serial clock I/O pins.

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(6) P50 to P57 (Port 5) … Input/Output

Port 5 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P50 to P57 operate as RPU input or output. The operation mode can be specified by the port 5 mode control register (PMC5) to port or control mode for each port pin individually.

(a) Port mode

P50 to P57 can be set to input or output in 1-bit units using the port 5 mode register (PM5).

(b) Control mode

P50 to P57 can be set to port or control mode in 1-bit units using the PMC5 register.

(i) TOR00, TOR01, TOR02, TOR03, TOR04 (Timer output) … Output

These pins output timer TMR0 pulse signals.

(7) P60 to P67 (Port 6) … Input/Output

Port 6 is an 8-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P60 to P67 operate as RPU input or output. The operation mode can be specified by the port 6 mode control register (PMC6) to port or control mode for each port pin individually.

(a) Port mode

P60 to P67 can be set to input or output in 1-bit units using the port 6 mode register (PM6).

(b) Control mode

P60 to P67 can be set to port or control mode in 1-bit units using the PMC6 register.

(i) TIR10, TIR11, TIR12, TIR13 (Timer capture input) … Input

These are timer TMR1 capture trigger input pins.

(ii) TEVTR1 (Timer event input) … Input

This is a timer TMR1 external event counter input pin.

(iii) TTRGR1 (Timer trigger) … Input

This is a timer TMR1 external trigger input pin.

(iv) TOR10, TOR11, TOR12, TOR13, TOR14 (Timer output) … Output

These pins output timer TMR1 pulse signals.

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(8) P70 to P75 (Port 7) … Input/Output

Port 7 is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P70 to P75 operate as RPU input or output, and auxiliary frequency output. Additionally an external interrupt request signal input is available in port input mode. The operation mode can be specified by the port 7 mode control register (PMC7) to port or control mode for each port pin individually.

(a) Port mode

P70 to P75 can be set to input or output in 1-bit units using the port 7 mode register (PM7).

(i) INTP12 (Interrupt request from peripherals) … Input

This is an external interrupt request input pin, which is simultaneously enabled in port input mode.

(b) Control mode

P70 to P75 can be set to port or control mode in 1-bit units using the PMC7 register.

(i) TIT00, TIT01, TIT10, TIT11 (Timer capture input) … Input

These are timer TMT0 and TMT1 capture trigger input pins.

(ii) TEVTT0, TEVTT1 (Timer event input) … Input

These are timer TMT0 and TMT1 external event counter input pins.

(iii) TTRGT0, TTRGT1 (Timer trigger) … Input

These are timer TMT0 and TMT1 external trigger input pins.

(iv) TECRT0, TECRT1 (Timer clear) … Input

These are timer TMT0 and TMT1 external clear input pins.

(v) TENCT00, TENCT01, TENCT10, TENCT11 (Timer encoder input … Input

These are timer TMT0 and TMT1 encoder input pins.

(vi) TOT00, TOT01, TOT10, TOT11 (Timer output) … Output

These pins output timer TMT0 and TMT1 pulse signals.

(vii)AFO (Auxiliary frequency) … Output

This is an auxiliary frequency output signal pin of baudrate generator BGR2.

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Chapter 2 Pin Functions

(9) P80 to P86 (Port 8) … Input/Output

Port 8 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P80 to P86 operate as serial interface (CSI30, CSIB0). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 8 mode control register (PMC8) to port or control mode for each port pin individually.

(a) Port mode

P80 to P86 can be set to input or output in 1-bit units using the port 8 mode register (PM8).

(i) INTP6, INTP7, INTP8 (Interrupt request from peripherals) … Input

These are external interrupt request input pins, which are simultaneously enabled in port input mode.

(b) Control mode

P80 to P86 can be set to port or control mode in 1-bit units using the PMC8 register.

(i) SO30 (Serial output) … Output

This pin outputs CSI30 serial transmit data.

(ii) SI30 (Serial input) … Input

This pin inputs CSI30 serial receive data.

(iii) SCK30

This is the CSI30 serial clock I/O pin.

(iv) SCS300 to SCS303 (Serial chip select) … Output

These pins output CSI30 serial chip select signals.

(v) SSB0

This pin inputs CSIB0 slave select signal.

(Serial clock) … I/O

(Serial slave select signal) … Input

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Chapter 2 Pin Functions

(10) P90 to P96 (Port 9) … Input/Output

Port 9 is a 7-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P90 to P96 operate as serial interface

(CSI31

Note

, CSIB1

Note

). Additionally external interrupt request signal inputs are available in port input mode. The operation mode can be specified by the port 9 mode control register (PMC9) to port or control mode for each port pin individually.

(a) Port mode

P90 to P96 can be set to input or output in 1-bit units using the port 9 mode register (PM9).

(i) INTP9, INTP10, INTP11 (Interrupt request from peripherals) … Input

These are external interrupt request input pins, which are simultaneously enabled in port input mode.

(b) Control mode

P90 to P96 can be set to port or control mode in 1-bit units using the PMC9 register.

(i) SO31 (Serial output) … Output

This pin outputs CSI31 serial transmit data.

(ii) SI31 (Serial input) … Input

This pin inputs CSI31 serial receive data.

(iii) SCK31

(Serial clock) … I/O

This is the CSI31 serial clock I/O pin.

(iv) SCS310 to SCS313 (Serial chip select) … Output

These pins output CSI31 serial chip select signals.

(v) SSB1

(Serial slave select input) … Input

This pin inputs CSIB1 slave select signal.

Note: not available on μPD70F3447

Note

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Chapter 2 Pin Functions

(11) P100 to P102 (Port 10) … Input/Output

Port 10 is a 3-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as an I/O port, in control mode, P100 to P102 operate as RPU input or output The operation mode can be specified by the port 10 mode control register (PMC10) to port or control mode for each port pin individually.

(a) Port mode

P100 to P102 can be set to input or output in 1-bit units using the port 10 mode register (PM10).

(b) Control mode

P100 to P102 can be set to port or control mode in 1-bit units using the PMC4 register.

(i) TIUD1 (Timer count pulse input) … Input

Note

This is an external count clock input pin to the up/down counter (TMENC10).

(ii) TCUD1 (Timer control pulse input) … Input

Note

This is an input count operation switching signal to the up/down counter (TMENC10).

(iii) TCLR1 (Timer clear) … Input

Note

This is a clear signal input pin to the up/down counter (TMENC10).

(iv) TICC10, TICC11 (Timer capture input) … Input

Note

These are timer TMENC10 external capture trigger input pins.

(v) TO1 (Timer output) … Output

Note

This pin outputs timer TMENC10 pulse signals.

(vi) TOP80 (Timer output) … Output

This pin outputs timer TMP8 pulse signals.

(12) PAL0 to PAL15 (Port AL) … I/O

Port AL is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the address bus (A0 to A15) when memory is expanded externally. The operation mode can be specified by the port AL mode control register (PMCAL) to port or control mode for each port pin individually.

(a) Port mode

PAL0 to PAL15 can be set to input or output in 1-bit units using the port AL mode register (PMAL).

(b) Control mode

PAL0 to PAL15 can be set to port or control mode in 1-bit units using the PMCAL register.

(i) A0 to A15 (Address bus) … 3-state output

Note

These are the address output pins of the lower 16 bits of the 22-bit address bus when the external memory is accessed.

Note: not available on μPD70F3447

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Chapter 2 Pin Functions

(13) PAH0 to PAH5 (Port AH) … I/O

Port AH is a 6-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the address bus (A16 to A21) when memory is expanded externally. The operation mode can be specified by the port AH mode control register (PMCAH) to port or control mode for each port pin individually.

(a) Port mode

PAH0 to PAH5 can be set to input or output in 1-bit units using the port AH mode register (PMAH).

(b) Control mode

PAH0 to PAH6 can be set to port or control mode in 1-bit units using the PMCAH register.

(i) A16 to A21 (Address bus) … 3-state output

Note

These are the address output pins of the higher 6 bits of the 22-bit address bus when the external memory is accessed.

(14) PDL0 to PDL15 (Port DL) … I/O

Port DL is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as the data bus (D0 to D15) when memory is expanded externally. The operation mode can be specified by the port DL mode control register (PMCDL) to port or control mode for each port pin individually.

(a) Port mode

PDL0 to PDL15 can be set to input or output in 1-bit units using the port DL mode register (PMDL).

(b) Control mode

PDL0 to PDL15 can be set to port or control mode in 1-bit units using the PMCDL register.

(i) D0 to D15 (Address bus) … 3-state I/O

Note

These are the data I/O pins of the lower 16 bits of the 32-bit data bus when the external memory is accessed.

Note: not available on μPD70F3447

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Chapter 2 Pin Functions

(15) PDH0 to PDH15 (Port DH) … I/O

Port DH is an 8-bit or a 16-bit I/O port in which input or output can be set for each port pin individually.

Besides functioning as a port, in control mode, these pins operate as the data bus

Note

(D16 to D31) when memory is expanded externally. The operation mode can be specified by the port DH mode control register (PMCDH) to port or control mode for each port pin individually.

(a) Port mode

PDH0 to PDH15 can be set to input or output in 1-bit units using the port DH mode register (PMDH).

(b) Control mode

PDH0 to PDH15 can be set to port or control mode in 1-bit units using the PMCDH register.

(i) D16 to D31 (Address bus) … 3-state I/O

Note

These are the data I/O pins of the higher 16 bits of the 32-bit data bus when the external memory is accessed.

(16) PCD2 to PCD5 (Port CD) … I/O

Port CD is a 4-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal outputs

when memory is expanded externally. The operation mode can be specified by the port CD mode control register (PMCCD) to port or control mode for each port pin individually.

(a) Port mode

PCD2 to PCD5 can be set to input or output in 1-bit units using the port CD mode register (PMCD).

(b) Control mode

PCD2 to PCD5 can be set to port or control mode in 1-bit units using the PMCCD register.

(i) BEN0

to BEN3 (Byte enable) … 3-state output

Note

These are the byte enable control signal pins, which indicate the validity of the corresponding byte on the 32-bit data bus.

Note

Note: not available on μPD70F3447

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Chapter 2 Pin Functions

(17) PCM0, PCM1, PCM6, PCM7 (Port CM) … I/O

Port CM is a 4-bit I/O port in which input or output can be set for each port pin individually.

Besides functioning as a port, in control mode, these pins operate as control signal input memory is expanded externally. The operation mode can be specified by the port CM mode control register (PMCCM) to port or control mode for each port pin individually.

(a) Port mode

PCM0, PCM1, PCM6, and PCM7 can be set to input or output in 1-bit units using the port CM mode register (PMCM).

(b) Control mode

PCM0 can be set to port or control mode in 1-bit units using the PMCCM register.

Note

when

(i) WAIT

(Wait) … Input

Note

This is the control signal input pin at which an external data wait is inserted into the bus cycle. The WAIT

signal can be input asynchronously, and is sampled at the falling edge of the BCLK signal. When the setup or hold time is terminated within the sampling timing, wait insertion may not be executed.

(18) PCS0, PCS1, PCS3, PCS4 (Port CS) … I/O

Port CS is a 4-bit I/O port in which input or output can be set for each port pin individually. Besides functioning as a port, in control mode, these pins operate as control signal outputs

when memory is expanded externally. The operation mode can be specified by the port CS mode control register (PMCCS) to port or control mode for each port pin individually.

(a) Port mode

PCS0, PCS1, PCS3, and PCS4 can be set to input or output in 1-bit units using the port CS mode register (PMCS).

(b) Control mode

PCS0, PCS1, PCS3, and PCS4 can be set to port or control mode in 1-bit units using the PMCCS register.

Note

(i) CS0

, CS1, CS3, CS4 (Chip select) … 3-state output

These are the chip select signal output pins for the external memory or peripheral I/O extension areas. The CSn

signal is assigned to the memory block n (n = 0, 1, 3, 4). It becomes active while the bus cycle that accesses the corresponding memory block is activated. In the idle state (TI), it becomes inactive.

Note: not available on μPD70F3447

User’s Manual U16580EE3V1UD00

Note

Chapter 2 Pin Functions

(19) PCT4, PCT5 (Port CT) … I/O

Port CT is a 2-bit I/O port in which input or output can be set for each port pin individually.

Besides functioning as a port, in control mode, these pins operate as control signal outputs when memory is expanded externally. The operation mode can be specified by the port CT mode control register (PMCCT) to port or control mode for each port pin individually.

(a) Port mode

PCT4 and PCT5 can be set to input or output in 1-bit units using the port CT mode register (PMCT).

(b) Control mode

PCT4 and PCT5 can be set to port or control mode in 1-bit units using the PMCCT register.

Note

(i) RD

(Read strobe) … 3-state output

This is a strobe signal output pin that shows whether the bus cycle currently being executed is a read cycle for the external memory or peripheral I/O extension area. In the idle state (TI), it becomes inactive.

(ii) WR

(Write strobe) … 3-state output

This is a strobe signal output pin that shows whether the bus cycle currently being executed is a write cycle for the external memory or peripheral I/O extension area.

Note: not available on μPD70F3447

Note

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

(20) DCK (Debug clock) … Input

This pin inputs a debug clock. At the rising edge of the DCK signal, the DMS and DDI signals are sampled, and data is output from the DDO pin at the falling edge of the DCK signal. Keep this pin high when the debug function is not used.

(21) DDI (Debug data input) … Input

This pin inputs debug data, which is sampled at the rising edge of the DCK signal when the debug serial interface is in the shift state. Data is input with the LSB first. Keep this pin high when the debug function is not used.

(22) DDO (Debug data output) … Output

This pin outputs debug data at the falling edge of the DCK signal when the debug serial interface is in the shift state. Data is output with the LSB first.

(23) DMS (Debug mode select) … Input

This input pin selects a debug mode. Depending on the level of the DMS signal, the state machine of the debug serial interface changes. This pin is sampled at the rising edge of the DCK signal. Keep this pin high when the debug function is not used.

(24) DRST

(Debug reset) … Input

This pin inputs a debug reset signal that is a negative-logic signal to initialize the DCU asynchronously. When this signal goes low, the DCU is reset/invalidated. Keep this pin low when the debug function is not used.

(25) MODE0 to MODE2 (Mode) … Input

These are input pins used to specify the operating mode.

(26) FLMD0, FLMD1 (flash programming mode)

These are input pins used to specify the flash programming mode.

(27) RESET

RESET

(Reset) … Input

is a signal that is input asynchronously and that has a constant low level width regardless of the operating clock’s status. When this signal is input, a system reset is executed as the first priority ahead of all other operations. In addition to being used for ordinary initialization/start operations, this pin can also be used to release a standby mode (HALT).

(28) X1, X2 (Crystal)

These pins are used to connect the resonator that generates the system clock.

(29) ANI00 to ANI09, ANI10 to ANI19 (Analog input) … Input

These are analog input pins of the corresponding A/D converter (ADC0, ADC1).

(30) AV

REF0

, AV

(Analog reference voltage) … Input

REF1

These are reference voltage supply pins for the corresponding A/D converter (ADC0, ADC1).

(31) AV

(Analog power supply)

This is the positive power supply pin for the A/D converters.

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Chapter 2 Pin Functions

(32) AV

(Analog ground)

This is the analog ground pin for the A/D converters.

(33) CV

(Power supply for clock generator)

This is the positive power supply pin for the clock generator.

(34) CV

(Ground for clock oscillator)

This is the ground pin for the clock generator.

(35) V

DD10

to V

(Power supply)

DD15

These are the positive power supply pins for the internal CPU.

(36) V

DD30

to V

(Power supply)

DD37

These are the positive power supply pins for the peripheral interface.

(37) V

SS10

to V

SS15

(Ground)

These are the ground pins for the internal CPU.

(38) V

SS30

to V

SS37

(Ground)

These are the ground pins for the peripheral interface.

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Chapter 2 Pin Functions

2.4 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-4: I/O Circuit Types (1/4)

Terminal I/O circuit type Recommended termination

μPD70F3187 μPD70F3447

P00/NMI 2 Connect independently to V

P01/INTP0/ESO0

P02/INTP1/ESO1

P03INTP2/ADTRG0

P04INTP3/ADTRG1

P10/TIP00/TEVTP1/TOP00 5-K Input: Connect independently to V

P11/TIP01/TTRGP1/TOP01

P12/TIP10/TTRGP0/TOP10

P13/TIP11/TEVTP0/TOP11

P14/TIP20/TEVTP3/TOP20

P15/TIP21/TTRGP3/TOP21

P16/TIP30/TTRGP2/TOP30

P17/TIP31/TEVTP2/TOP31

P20/TIP40/TEVTP5/TOP40

P21/TIP41/TTRGP5/TOP41

P22/TIP50/TTRGP4/TOP50

P23/TIP51/TEVTP4/TOP51

P24/TIP60/TEVTP7/TOP60

P25/TIP61/TTRGP7/TOP61

P26/TIP70/TTRGP6/TOP70

P27/TIP71/TEVTP6/TOP71

P30/RXDC0/INTP4

P31/TXDC0

P32/RXDC1/INTP5

P33/TXDC1

P34/FCRXD0

P35/FCTXD0

P36/FCRXD1 P36

P37/FCTXD1 P37

P40/SIB0

P41/SOB0

P42/SCKB0

P43/SIB1 P43

P44/SOB1 P44

P45/SCKB1

P50/TOR00 to P57/TOR07

P45

resistor Output: leave open

SS3

via a resistor

or V

DD3

SS3

via a

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Chapter 2 Pin Functions

Table 2-4: I/O Circuit Types (2/4)

Terminal I/O circuit type Recommended termination

μPD70F3187 μPD70F3447

P60/TOR10/TTRGR1 5-K Input: Connect independently to V

P61/TOR11/TIR10

P62/TOR12/TIR11

P63/TOR13/TIR12

P64/TOR14/TIR13

P65/TOR15

P66/TOR16

P67/TOR17/TEVTR1

P70/TIT00/TEVTT1/TOT00/TENCT00

P71/TIT01/TTRGT1/TOT01/TENCT01

P72/TECRT0/INTP12

P73/TIT10/TTRGT0/TOT10/TENCT10

P74/TIT11/TEVTT0/TOT11/TENCT11

P75/TECRT1/AFO

P80/SI30

P81/SO30

P82/SCK30

P83/SCS300/INTP6

P84/SCS301/INTP7

P85/SCS302/INTP8

P86/SCS303/SSB0

P90/SI31 P90

P91/SO31 P91

P92/SCK31

P93/SCS310/ INTP9

P94/SCS311/ INTP10

P95/SCS312 /INTP11

P96/SCS313/ SSB1

P100/TCLR1/ TICC10/TOP80

P101/TCUD1/ TICC11

P102/TIUD1/TO1 P102

P92

P93/INTP9

P94/INTP10

P95/INTP11

P96

P100/TOP80

P101

resistor Output: leave open

DD3

or V

SS3

via a

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Chapter 2 Pin Functions

Table 2-4: I/O Circuit Types (3/4)

Terminal I/O circuit type Recommended termination

μPD70F3187 μPD70F3447

PAH0/A16 to PA H5 /A 2 1

PA L 0 / A 0 t o PAL15/A15

PDH0/D16 to PDH15/D31

PDL0/D0 to PDL15/D15

PCS0/CS0 PCS0

PCS1/CS1 PCS1

PCS3/CS3

PCS4/CS4

PCD2/BEN0 to PCD5/BEN3

PCT4/RD PCT4 5 Input: Connect independently to V

PCT5/WR PCT5

PCM0/WAIT

PCM1 PCM1

PCM6 PCM6

PCM7 PCM7

RESET

MODE0/FLMD0 2

MODE1/FLMD1 2

MODE2 2

DCK 1 Connect independently to V

DRST

DMS 1 Connect independently to V

DDI

DDO 3 Leave open (always level output during reset)

ANI00 to ANI09 7 Connect independently to AV

ANI10 to ANI19

REF0

REF1

PAH0 to PAH5 5 Input: Connect independently to V

resistor

PAL0 to PAL15

Output: leave open

PDH0 to PDH15

PDL0 to PDL15

PCS3

PCS4

PCD2 to PCD5

resistor Output: leave open

PCM0

2 Pin must be used in the intended way

–

via a resistor

DD3

2-I Leave open (on-chip pull-down resistor

via a resistor

DD3

or AVSS via a resis-

tor

–

Connect independently to AVSS via a resistor

DD3

or V

SS3

via a

User’s Manual U16580EE3V1UD00

Terminal I/O circuit type Recommended termination

μPD70F3187 μPD70F3447

SS0

SS1

to V

DD10

SS10

DD30

SS30

to V

DD15

SS15

DD37

SS37

Chapter 2 Pin Functions

Table 2-4: I/O Circuit Types (4/4)

–

Pin must be used in the intended way

User’s Manual U16580EE3V1UD00

Chapter 2 Pin Functions

Figure 2-1: Pin I/O Circuits

Type 1

P-ch

N-ch

Type 2

Schmitt trigger input with hysteresis characteristics

Type 5

data

output

disable

input

enable

Type 5-K

data

output

disable

input

enable

P-ch

N-ch

P-ch

N-ch

IN/OUT

Type 2-I

Schmitt trigger input with hysteresis characteristics

Type 3

P-ch

N-ch

OUT

Type 7

P-ch

N-ch

(threshold voltage)

REF

comparator

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Chapter 2 Pin Functions

2.5 Noise Suppression

The V850E/PH2 has a digital or analog delay circuits for noise suppression on all edge sensitive inputs. The digital delay circuit suppresses input pulses shorter than the internally generated edge detection signal to assure the hold time for these signals. The noise suppression is only effective on alternate pin functions, and it is not effective when the port input function is selected.

Table 2-5: Noise Suppression Timing

Pin Function Noise removal time Clock Source

NMI 4 to 5 clocks f

INTP0, INTP1, ESO0, ESO1 Analog delay (60ns to 200ns)

INTP2 to INTP11, ADTRG0, ADTRG1 4 to 5 clocks f

INTP12,

TICC00

TCUD0

Note

, TICC01

, TIUD0

Note

, TCLR0

Note

4 to 5 clocks fXX/16 or fXX/64

TIT00, TIT01, TIT10, TIT11, TECRT0, TECRT1, TEVTT0, TEVTT1, TTRGT0, TTRGT1, TENCT00, TENCT01, TENCT10, TENCT11

TIP00, TIP01, TIP10, TIP11,

4 to 5 clocks f

TEVTP0, TEVTP1, TTRGP0, TTRGP1

TIP20, TIP21, TIP30, TIP31,

4 to 5 clocks fXX/16 or fXX/64

TEVTP2, TEVTP3, TTRGP2, TTRGP3

TIP40, TIP41, TIP50, TIP51,

4 to 5 clocks f

TEVTP4, TEVTP5, TTRGP4, TTRGP5

TIP60, TIP61, TIP70, TIP71,

4 to 5 clocks fXX/16 or fXX/64

TEVTP6, TEVTP7, TTRGP6, TTRGP7

TIR10 to TIR13, TEVTR1, TTRGR1 4 to 5 clocks f

/16 or fXX/64

(set by NCR0 bit of NRC register)

/16 or fXX/64

(set by NCR1 bit of NRC register)

(set by NCR2 bit of NRC register)

/16 or fXX/64

(set by NCR3 bit of NRC register)

(set by NCR4 bit of NRC register)

/16 or fXX/64

(set by NCR5 bit of NRC register)

(set by NCR6 bit of NRC register)

/16 or fXX/64

(set by NCR7 bit of NRC register)

Note: Not available on μPD70F3447

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Chapter 2 Pin Functions

(1) Noise removal time control register (NRC)

The NRC register specifies the noise removal clock setting for different edge sensitive inputs. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H.

Figure 2-2: Noise Removal Time Control Register (1/2)

After reset: 00H R/W Address: FFFFF7A0H

76543210

NRC NCR7 NCR6 NCR5 NCR4 NCR3 NCR2 NCR1 NCR0

NCR7 Noise removal clock setting for input pins TIR10 to TIR13, TEVTR1, TTRGR1

NCR6 Noise removal clock setting for input pins TIP60, TIP61, TIP70, TIP71,

1fXX/64

/16

/64

TEVTP6, TEVTP7, TTRGP6, TTRGP7

/16

NCR5 Noise removal clock setting for input pins TIP40, TIP41, TIP50, TIP51,

TEVTP4, TEVTP5, TTRGP4, TTRGP5

/16

1fXX/64

NCR4 Noise removal clock setting for input pins TIP20, TIP21, TIP30, TIP31,

TEVTP2, TEVTP3, TTRGP2, TTRGP3

/16

1fXX/64

NCR3 Noise removal clock setting for input pins TIP00, TIP01, TIP10, TIP11,

TEVTP0, TEVTP1, TTRGP0, TTRGP1

/16

1fXX/64

NCR2 Noise removal clock setting for input pins INTP12, TICC00, TICC01, TCLR0,

TCUD0, TIUD0, TIT00, TIT01, TIT10, TIT11, TECRT0, TECRT1, TEVTT0,

TEVTT1, TTRGT0, TTRGT1, TENCT00, TENCT01, TENCT10, TENCT11

Note

0fXX/16

1fXX/64

Note: Input pins TIC00, TIC01, TCRL0, TCUD0, and TIUD0 are not available on μPD70F3447

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Chapter 2 Pin Functions

Figure 2-2: Noise Removal Time Control Register (2/2)

NCR1 Noise removal clock setting for input pins INTP2 to INTP11, ADTRG0,

ADTRG1

0fXX/16

1fXX/64

NCR0 Noise removal clock setting for NMI input pin

1fXX/64

/16

User’s Manual U16580EE3V1UD00

[MEMO]

Chapter 2 Pin Functions

User’s Manual U16580EE3V1UD00

Chapter 3 CPU Functions

The CPU of the V850E/PH2 microcontroller is based on the RISC architecture and executes most instructions in one clock cycle by using a 5-stage pipeline control.

3.1 Features

• Number of instructions: 96

• Minimum instruction execution time: 15.6 ns (@ 64 MHz operation)

• Memory space Program space: 64 MB linear

Data space: 4 GB linear

• General-purpose registers: 32 bits × 32

• Internal 32-bit architecture

• 5-stage pipeline control

• Multiply/divide instructions (32 bits × 32 bits → 64 bits in 1 to 2 clocks)

• Saturated operation instructions

• Floating point arithmetic unit (single precision, 32 bits, IEEE754-85 standard)

• 32-bit shift instruction: 1 clock

• Load/store instruction with long/short format

• Four types of bit manipulation instructions

- SET1

- CLR1

-NOT1

-TST1

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Chapter 3 CPU Functions

3.2 CPU Register Set

The CPU registers of the V850E/PH2 can be classified into three categories: a general-purpose program register set, a dedicated system register set and a dedicated floating point arithmetic register set. All the registers have 32-bit width. In addition, the V850E/PH2 contains special system control registers that should be initialized before CPU operation, and a specific register controlling its clock.

For detailed description of V850E1 core, refer to V850E1 Core Architecture Manual and the addendum for floating point arithmetic.

Figure 3-1: CPU Register Set

(1) Program register set (2) System register set

31 0

r0 (Zero register)

r1 (Assembler-reserved register)

r5 (Text pointer (TP))

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r20

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30 (Element pointer (EP))

r31 (Link pointer (LP))

31 0

PC (Program counter)

(Stack pointer (SP))

(Global pointer (GP))

31 0

EIPC

EIPSW

FEPC

FEPSW

ECR

PSW (Program status word)

CTPC

CTPSW

DBPC

DBPSW

CTBP (CALLT base pointer)

(Status saving register during interrupt)

(Status saving register during NMI)

(Interrrupt source register)

(Status saving register during CALLT execution)

(Status saving register during exception/debug trap)

(3) Floating point arithmetic register set

31 0

EFG

ECT (Control register)

(Flag register)

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Chapter 3 CPU Functions

3.2.1 Program register set

The program register set includes general-purpose registers and a program counter.

(1) General-purpose registers (r0 to r31)

Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 or offset 0 addressing. r30 is used as a base pointer when performing memory access with the SLD and SST short instructions. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after use. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register.

Table 3-1: Program Registers

Name Usage Operation

r0 Zero register Always holds 0

r1 Assembler-reserved register Working register for generating 32-bit immediate

r2 Address/data variable register (when r2 is not used by the real-time OS to be used)

r3 Stack pointer Used to generate stack frame when function is called

r4 Global pointer Used to access global variable in data area

r5 Text pointer Register to indicate the start of the text area (area for placing program

code)

r6 to r29 Address/data variable register

r30 Element pointer Base pointer when memory is accessed

r31 Link pointer Used by compiler when calling function

(2) Program counter (PC)

This register holds the address of the instruction under execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed.

Figure 3-2: Program Counter (PC)

31 26 25 10

PC Fixed to 0 Instruction address under execution

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After reset

00000000H

Chapter 3 CPU Functions

3.2.2 System register set

System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions).

Table 3-2: System Register Numbers

System Register Operand Specification

Enabled for instruction

No. Name Function LDSR STSR

0EIPC

1 EIPSW

2 FEPC PC value at NMI handler entry Yes Yes

3 FEPSW PSW value at NMI handler entry Yes Yes

4 ECR Exception Cause Register No Yes

5 PSW Program status word Yes Yes

6 to 15 - Reserved numbers for future function expansion

16 CTPC

17 CTPSW

18 DBPC PC value at exception/debug trap entry Yes Yes

19 DBPSW PSW value at exception/debug trap entry Yes Yes

20 CTBP CALLT base pointer Yes Yes

21 to 31 - Reserved numbers for future function expansion

PC value at Interrupt handler entry

PSW value at Interrupt handler entry

(The operation is not guaranteed if accessed.)

PC value at CALLT subroutine entry

PSW value at CALLT subroutine entry

(The operation is not guaranteed if accessed.)

Note 1

Note 2

Ye s Ye s

No No

Ye s Ye s

No No

Notes: 1. Since only one set of registers is available, the contents of these registers must be saved by

the program when multiple interrupt servicing is enabled.

2. Since only one set of registers is available, the contents of these registers must be saved by the program when CALLT instructions nesting is used.

Caution: Even if bit 0 of EIPC, FEPC, or CTPC is set to (1) by the LDSR instruction, bit 0 is

ignored during return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). If setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0).

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Chapter 3 CPU Functions

(1) Interrupt status saving registers (EIPC, EIPSW)

There are two context saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the content of the program counter (PC) is saved to EIPC and the content of the program status word (PSW) is saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for the DIVH instruction (see Chapter 7 ”Interrupt/Exception Processing Function” on page 219).

Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion.

Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW)

31 26 25 0

EIPC

EIPSW

000000

31 87 0

000000000000000000000000

(PC contents)

(PSW contents)

The values of EIPC and EIPSW are restored to PC and PSW during execution of a RETI instruction.

After reset

0xxxxxxxH

(x: Undefined)

After reset 000000xxH

(x: Undefined)

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Chapter 3 CPU Functions

(2) NMI status saving registers (FEPC, FEPSW)

There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the content of the program counter (PC) is saved to FEPC and the content of the program status word (PSW) is saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for the DIVH instruction. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.

Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW)

31 26 25 0

FEPC

FEPSW

000000

31 87 0

000000000000000000000000

(PC contents)

(PSW contents)

The values of FEPC and FEPSW are restored to PC and PSW during execution of a RETI instruction.

(3) Exception cause register (ECR)

Upon occurrence of an interrupt or an exception, the Exception Cause Register (ECR) holds the source of the interrupt or the exception. The value held by ECR is an exception code, coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction.

Figure 3-5: Interrupt Source Register (ECR)

After reset 0xxxxxxxH

(x: Undefined)

After reset 000000xxH

(x: Undefined)

31 16 15 0

ECR FECC EICC

Bit position Bit name Description

31 to 16 FECC Non-maskable interrupt (NMI) exception code

15 to 0 EICC Exception, maskable interrupt exception code

The list of exception codes is tabulated in Table 7-1, “Interrupt/Exception Source List,” on

page 219.

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After reset 00000000H

Chapter 3 CPU Functions

(4) Program status word (PSW)

The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of the LDSR instruction execution. However, if the ID flag is set to 1, interrupt request acknowledgement during LDSR instruction execution is prohibited. Bits 31 to 8 are reserved (fixed to 0) for future function expansion.

Figure 3-6: Program Status Word (PSW)

31 2625 8765 4 3210

PSW RFU

Bit position Bit name Description

31 to 8 RFU Reserved field. Fixed to 0.

7 NP Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to

1 when a NMI request is acknowledged, and disables multiple interrupts.

0: NMI servicing not in progress 1: NMI servicing in progress

6 EP Indicates that exception processing is in progress. This flag is set to 1 when an

exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set.

0: Exception processing not in progress 1: Exception processing in progress

5 ID Indicates whether maskable interrupt request acknowledgment is enabled.

0: Interrupt enabled 1: Interrupt disabled

Note

3 CY Indicates whether carry or borrow occurred as the result of an operation.

0 Z Indicates whether operation result is 0.

SAT

Note

Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed.

0: Not saturated 1: Saturated

0: No carry or borrow occurred 1: Carry or borrow occurred

Note

Indicates whether overflow occurred during an operation.

0: No overflow occurred 1: Overflow occurred.

Indicates whether the result of an operation is negative.

0: Operation result is positive or 0. 1: Operation result is negative.

0: Operation result is not 0. 1: Operation result is 0.

NP EP ID SAT CY OV S

After reset

00000020H

Note: During saturated operation, the saturated operation results are determined by the contents of

the OV flag and S flag. The SAT flag is set to 1 only when the OV flag is set to 1 during saturated operation. This is explained on the following table.

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Chapter 3 CPU Functions

Table 3-3: Saturated Operation Results

Operation result status Flag status Saturated

SAT OV S

Maximum positive value exceeded 1 1 0 7FFFFFFFH

Maximum negative value exceeded 1 1 1 80000000H

Positive (maximum value not exceeded) Holds value

Negative (maximum value not exceeded) 1

before operation

0 0 Actual

operation result

(5) CALLT execution status saving registers (CTPC, CTPSW)

There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. Bits 31 to 26 CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion.

Figure 3-7: CALLT Execution Status Saving Registers (CTPC, CTPSW)

31 26 25 0

CTPC

CTPSW

000000

31 87 0

000000000000000000000000

(PC contents)

(x: Undefined)

(PSW contents)

(x: Undefined)

The values of CTPC and CTPSW are restored to PC and PSW during execution of the CTRET instruction.

After reset 0xxxxxxxH

After reset 000000xxH

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Chapter 3 CPU Functions

(6) Exception/debug trap status saving registers (DBPC, DBPSW)

There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion.

Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC, DBPSW)

31 26 25 0

DBPC

DBPSW

000000

31 87 0

000000000000000000000000

(PC contents)

(PSW contents)

The values of DBPC and DBPSW are restored to PC and PSW during execution of the DBRET instruction.

(7) CALLT base pointer (CTBP)

The CALLT base pointer (CTBP) is used to specify CALLT table start address and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion.

Figure 3-9: CALLT Base Pointer (CTBP)

After reset

0xxxxxxxH

(x: Undefined)

After reset 000000xxH

(x: Undefined)

CTBP

31 26 25 10

000000

(Base address)

(x: Undefined)

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After reset

0xxxxxxxH

Chapter 3 CPU Functions

3.2.3 Floating point arithmetic unit register set

The floating point arithmetic unit is provided with one flag register and one control register.

Table 3-4: Floating Point Arithmetic Unit Registers

Name Usage Operation

ECT Control register Sets the operation of the EFG register

EFG Flag register Holds the status of the FPU

(1) Floating point arithmetic control register (ECT)

This register is used for controlling the setting conditions of the TR flag: TR is a logical OR between all the invalid operations the FPU can detect and each bit of ECT is a mask bit for each condition.

Figure 3-10: Floating Point Arithmetic Control Register (ECT)

31 1312111098765 4 3210

ECT RFU

ITZTVTUTPT000 0 000

After reset 00000000H

Bit position Bit name Description

31 to 13 RFU Reserved field. Fixed to 0.

12 IT Enables invalid operation detection in the TR value calculation

0: IV is set when an invalid operation is detected 1: IV and TR are set when an invalid operation is detected

11 ZT Enables zero divide operation detection in the TR value calculation

0: ZD is set when a zero divide operation is detected 1: ZD and TR are set when a zero divide operation is detected

10 VT Enables overflow detection in the TR value calculation

0: VF is set when an overflow is detected 1: VF and TR are set when an overflow is detected

9 UT Enables underflow detection in the TR value calculation

0: UD is set when an underflow is detected 1: UD and TR are set when an underflow is detected

8 PT Enables accuracy fail detection in the TR value calculation

0: PR is set when an accuracy fail is detected 1: PR and TR are set when an accuracy fail is detected

7 to 0 0 Reserved field. Fixed to 0.

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Chapter 3 CPU Functions

(2) Floating point arithmetic status register (EFG)

Figure 3-11: Floating Point Arithmetic Status Register (EFG)

31 141312111098765 4 3210

EFG RFU

Bit position Bit name Description

31 to 14 RFU Reserved field. Fixed to 0.

13 RO Running Operation: indicates whether the floating point arithmetic unit is running

0: operation in progress 1: FPU idle

12 IV InValid operation: Indicates that an invalid operation has been requested.

0: normal operation 1: invalid operation detected

11 ZD Zero Divide: Indicates whether a division by 0 has been detected.

0: normal operation 1: division by 0 detected

10 VF oVerFlow: indicates that the result of executing a floating point operation has

overflowed.

0: no overflow generated 1: overflow generated

9 UD Undervalue: indicates that the result of executing a floating point operation has

underflowed.

0: no underflow generated 1: underflow generated

8 PR PRecision error: indicates that an accuracy failure occurred.

0: no accuracy failure occurred 1: accuracy failure occurred

7 to 5 0 Reserved field. Fixed to 0.

4 TR This flag summarizes the state of the FPU:

0: normal state 1: abnormal condition detected: one of the bits 13 to 8 is set.

The setting conditions of this flag depends on the ECT register value.

3 0 Reserved field. Fixed to 0.

2 OV Indicates whether an overflow occurred during floating point to integer conversion

0: no overflow generated 1: overflow generated

1 S Indicates whether floating point operation result is negative.

0: Operation result is not negative. 1: Operation result is negative.

0 Z Indicates whether floating point operation result is 0.

0: Operation result is not 0. 1: Operation result is 0.

RO IV ZD VF UD PR 0 0 0 TR 0 OV S

After reset

00000000H

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Chapter 3 CPU Functions

3.3 Operating Modes

The V850E/PH2 has the following operating modes.

3.3.1 Operating modes outline

(1) Normal operating mode

(a) Single-chip mode 0

Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is released, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts. By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM registers to control mode by instruction, an external device can be connected to the external memory area.

(b) Single-chip mode 1 (μPD70F3187 only)

Note

In single-chip mode 1 enters the control mode, program execution branches to the external device’s (memory) reset entry address, and instruction processing starts. The internal ROM area is mapped from address 100000H.

, after the system reset is released, each pin related to the bus interface

After the system reset is released, each pin related to the bus interface enters the control mode, program execution branches to the external device’s (memory) reset entry address, and instruction processing starts. Fetching of instructions and data access for internal ROM becomes impossible. In ROM-less mode the data bus width is 32 bits.

(2) Flash memory programming mode

In this mode the internal flash memory can be written or erased with an external flash writer, using the CSIB0 or UARTC0 as serial interface.

Note: Single-chip mode 1 is not available on μPD70F3447.

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Chapter 3 CPU Functions

3.3.2 Operation mode specification

The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation.

MODE2 MODE1 MODE0 Mode Remark

L L L Single chip mode 0 Internal ROM area is allocated from

address 00000000H.

L L H Flash memory programming mode CSIB0/IUARTC0 selected by

MODE0 pin toggling.

LHL

LHH

other value than above Setting prohibited

ROM-less mode

Single chip mode 1

Note 2

Note 1

External 32-bit data bus

Internal ROM area is allocated from address 00100000H. External 32-bit data bus

Remark: L: Low-level input

H: High-level input

Notes: 1. Single-chip mode 1 is not available on μPD70F3447.

2. ROM-less mode is not available on μPD70F3447.

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Chapter 3 CPU Functions

3.4 Address Space

3.4.1 CPU address space

The CPU of the V850E/PH2 uses a 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). When addressing instructions, a linear address space (program space) of up to 64 MB is supported. However, both the program and data spaces include areas whose use is prohibited. For details, refer to Figure 3-13, “Address Space Image,” on page 99. Figure 3-12 shows the CPU address space.

Figure 3-12: CPU Address Space

CPU address space

FFFFFFFFH

04000000H

03FFFFFFH

00000000H

Data area

(4 GB linear)

Program area

(64 MB linear)

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Chapter 3 CPU Functions

3.4.2 Images

When addressing an instruction address, up to 64 MB of linear address space (program space) and Internal RAM area are supported. For operand addressing (data access), up to 4 GB of linear address space (data area) is supported. On this 4 GB address space, however, 256 MB physical address spaces can be seen as an image. Therefore, whatever the values of bits 31 to 29 of an address may be, a physical address space of the same 256 MB is accessed.

Figure 3-13: Address Space Image

CPU address space

FFFFFFFFH

Image

F0000000H

EFFFFFFFH

E0000000H

DFFFFFFFH

20000000H

1FFFFFFFH

10000000H

0FFFFFFFH

00000000H

Image

Physical address space

Peripheral I/O

Internal RAM

External memory

Internal ROM

FFFFFFFH

0000000H

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Chapter 3 CPU Functions

3.4.3 Wrap-around of CPU address space

(1) Program space

Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address, 03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses.

Caution: No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH

because this area is a peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area.

Figure 3-14: Program Space

03FFFFFEH

03FFFFFFH

00000000H

00000001H

Program space

(+) direction (–) direction

Program space

(2) Data space

The result of an operand address calculation that exceeds 32 bits is truncated to 32 bits. Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address, FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses.

Figure 3-15: Data Space

100

FFFFFFFEH

FFFFFFFFH

00000000H

00000001H

Data space

(+) direction (–) direction

Data space

User’s Manual U16580EE3V1UD00

NEC V850E/PH2, MuPD70F3187 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Chapter 1 Introduction

1.1 Outline

1.2 Device Features

1.3 Applications

1.4 Ordering Information

1.5 Pin Configuration (Top View)

Figure 1-1: Pin Configuration 208-pin Plastic LQFP

Table 1-1: Differences in Pin Assignment of 256-pin Plastic BGA (1/4)

1.6 Function Blocks

1.6.1 Internal block diagrams

1.6.2 On-chip units

Chapter 2 Pin Functions

2.1 List of Pin Functions

Table 2-1: Port Pins (1/5)

Table 2-2: Non-Port Pins (1/6)

2.2 Pin Status

Table 2-3: Pin Status in Reset and Standby Mode

2.3 Description of Pin Functions

2.4 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-4: I/O Circuit Types (1/4)

Figure 2-1: Pin I/O Circuits

2.5 Noise Suppression

Table 2-5: Noise Suppression Timing

Figure 2-2: Noise Removal Time Control Register (1/2)

Chapter 3 CPU Functions

3.1 Features

3.2 CPU Register Set

Figure 3-1: CPU Register Set

3.2.1 Program register set

Table 3-1: Program Registers

Figure 3-2: Program Counter (PC)

3.2.2 System register set

Table 3-2: System Register Numbers

Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW)

Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW)

Figure 3-5: Interrupt Source Register (ECR)

Figure 3-6: Program Status Word (PSW)

Table 3-3: Saturated Operation Results

Figure 3-7: CALLT Execution Status Saving Registers (CTPC, CTPSW)

Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC, DBPSW)

Figure 3-9: CALLT Base Pointer (CTBP)

3.2.3 Floating point arithmetic unit register set

Table 3-4: Floating Point Arithmetic Unit Registers

Figure 3-10: Floating Point Arithmetic Control Register (ECT)

Figure 3-11: Floating Point Arithmetic Status Register (EFG)

3.3 Operating Modes

3.3.1 Operating modes outline

3.3.2 Operation mode specification

3.4 Address Space

3.4.1 CPU address space

Figure 3-12: CPU Address Space

3.4.2 Images

Figure 3-13: Address Space Image

3.4.3 Wrap-around of CPU address space

Figure 3-14: Program Space

Figure 3-15: Data Space