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µ
µ
µ
µ
User’s Manual
78K0/KC1
8-Bit Single-Chip Microcontrollers
PD780111
µ
PD780112
µ
PD780113
µ
PD780114
µ
PD78F0114 µPD78F0114(A) µPD78F0114(A1)
Document No. U16227EJ2V0UD00 (2nd edition)
Date Published November 2003 N CP(K)
PD780111(A)
µ
PD780112(A)
µ
PD780113(A)
µ
PD780114(A)
PD780111(A1)
µ
PD780112(A1)
µ
PD780113(A1)
µ
PD780114(A1)
PD780111(A2)
µ
PD780112(A2)
µ
PD780113(A2)
µ
PD780114(A2)
©
Printed in Japan
Page 2
[MEMO]
2
User’s Manual U16227EJ2V0UD
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
DD or GND with a resistor, if it is considered to have a possibility of
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U16227EJ2V0UD
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Page 4
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of May, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
•
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
•
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
•
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard":
"Special":
"Specific":
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
4
User’s Manual U16227EJ2V0UD
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
N
EC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-558-3737
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
J03.4
User’s Manual U16227EJ2V0UD
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INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0/KC1 and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0/KC1:
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0/KC1 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
µ
PD780111, 780112, 780113, 780114, 78F0114, 780111(A), 780112(A),
780113(A), 780114(A), 78F0114(A), 780111(A1), 780112(A1), 780113(A1),
780114(A1), 78F0114(A1), 780111(A2), 780112(A2), 780113(A2), and
780114(A2)
78K0/KC1
User’s Manual
(This Manual)
78K/0 Series
Instructions
User’s Manual
• Pin functions
• Internal block functions
• Interrupts
• CPU functions
• Instruction set
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications
6
User’s Manual U16227EJ2V0UD
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How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• When using this manual as the manual for (A) grade products, (A1) grade products,
and (A2) grade products:
→ Only the quality grade differs between standard products and (A), (A1), and (A2)
grade products. Read the part number as follows.
•
µ
PD780111 → µPD780111(A), 780111(A1), 780111(A2)
• µPD780112 → µPD780112(A), 780112(A1), 780112(A2)
•
µ
PD780113 → µPD780113(A), 780113(A1), 780113(A2)
•
µ
PD780114 → µPD780114(A), 780114(A1), 780114(A2)
• µPD78F0114 → µPD78F0114(A), 78F0114(A1)
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points.
• How to interpret the register format:
→ For a bit number enclosed in brackets, the bit name is defined as a reserved word
in the assembler, and is already defined in the header file named sfrbit.h in the C
compiler.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX C REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Caution Examples in this manual employ the “standard” quality grade for
general electronics. When using examples in this manual for the
“special” quality grade, review the quality grade of each part and/or
circuit actually used.
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
Decimal
Hexadecimal
...
×××× or ××××B
...
××××
...
××××H
User’s Manual U16227EJ2V0UD
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Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0/KC1 User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
RA78K0 Assembler Package
ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E
Project Manager Ver. 3.12 or Later (Windows Based) U14610E
Operation U14445E
Language U14446E
Structured Assembly Language U11789E
Operation U14297E CC78K0 C Compiler
Language U14298E
Operation (WindowsTM Based) U15373E SM78K Series System Simulator Ver. 2.30 or Later
External Part User Open Interface
Specifications
Fundamentals U11537E RX78K0 Real-Time OS
Installation U11536E
U15802E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
IE-78K0-NS In-Circuit Emulator U13731E
IE-78K0-NS-A In-Circuit Emulator U14889E
IE-78K0K1-ET In-Circuit Emulator To be prepared
IE-780148-NS-EM1 Emulation Board To be prepared
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP3 Flash Memory Programmer User’s Manual U13502E
PG-FP4 Flash Memory Programmer User’s Manual U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
8
User’s Manual U16227EJ2V0UD
Page 9
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U16227EJ2V0UD
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CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features ...................................................................................................................................... 17
1.2 Applications................................................................................................................................ 18
1.3 Ordering Information ................................................................................................................. 19
1.4 Pin Configuration (Top View).................................................................................................... 21
1.5 K1 Family Lineup........................................................................................................................ 23
1.5.1 78K0/Kx1 product lineup................................................................................................................ 23
1.5.2 V850ES/Kx1 product lineup........................................................................................................... 25
1.6 Block Diagram ............................................................................................................................ 27
1.7 Outline of Functions .................................................................................................................. 28
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 30
2.1 Pin Function List ........................................................................................................................ 30
2.2 Description of Pin Functions .................................................................................................... 33
2.2.1 P00 and P01 (port 0) ..................................................................................................................... 33
2.2.2 P10 to P17 (port 1) ........................................................................................................................ 34
2.2.3 P20 to P27 (port 2) ........................................................................................................................ 34
2.2.4 P30 to P33 (port 3) ........................................................................................................................ 35
2.2.5 P60 to P63 (port 6) ........................................................................................................................ 35
2.2.6 P70 to P73 (port 7) ........................................................................................................................ 35
2.2.7 P120 (port 12)................................................................................................................................ 36
2.2.8 P130 (port 13)................................................................................................................................ 36
2.2.9 AVREF ............................................................................................................................................. 36
2.2.10 AVSS............................................................................................................................................... 36
2.2.11 RESET........................................................................................................................................... 36
2.2.12 X1 and X2...................................................................................................................................... 36
2.2.13 XT1 and XT2.................................................................................................................................. 36
2.2.14 VDD and EVDD................................................................................................................................. 36
2.2.15 VSS and EVSS ................................................................................................................................. 36
2.2.16 VPP (flash memory versions only) .................................................................................................. 36
2.2.17 IC (mask ROM versions only) ........................................................................................................ 37
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 38
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 41
3.1 Memory Space ............................................................................................................................ 41
3.1.1 Internal program memory space .................................................................................................... 47
3.1.2 Internal data memory space .......................................................................................................... 48
3.1.3 Special function register (SFR) area .............................................................................................. 48
3.1.4 Data memory addressing............................................................................................................... 49
3.2 Processor Registers .................................................................................................................. 54
3.2.1 Control registers ............................................................................................................................ 54
3.2.2 General-purpose registers ............................................................................................................. 58
3.2.3 Special function registers (SFRs) .................................................................................................. 59
3.3 Instruction Address Addressing ..............................................................................................63
3.3.1 Relative addressing ....................................................................................................................... 63
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3.3.2 Immediate addressing ....................................................................................................................64
3.3.3 Table indirect addressing ...............................................................................................................65
3.3.4 Register addressing........................................................................................................................65
3.4 Operand Address Addressing..................................................................................................66
3.4.1 Implied addressing .........................................................................................................................66
3.4.2 Register addressing........................................................................................................................67
3.4.3 Direct addressing............................................................................................................................68
3.4.4 Short direct addressing...................................................................................................................69
3.4.5 Special function register (SFR) addressing .................................................................................... 70
3.4.6 Register indirect addressing ...........................................................................................................71
3.4.7 Based addressing...........................................................................................................................72
3.4.8 Based indexed addressing .............................................................................................................73
3.4.9 Stack addressing ............................................................................................................................74
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 75
4.1 Port Functions............................................................................................................................ 75
4.2 Port Configuration ..................................................................................................................... 77
4.2.1 Port 0..............................................................................................................................................78
4.2.2 Port 1..............................................................................................................................................80
4.2.3 Port 2..............................................................................................................................................85
4.2.4 Port 3..............................................................................................................................................86
4.2.5 Port 6..............................................................................................................................................88
4.2.6 Port 7..............................................................................................................................................89
4.2.7 Port 12............................................................................................................................................90
4.2.8 Port 13............................................................................................................................................91
4.3 Registers Controlling Port Function........................................................................................ 92
4.4 Port Function Operations.......................................................................................................... 96
4.4.1 Writing to I/O port ...........................................................................................................................96
4.4.2 Reading from I/O port.....................................................................................................................96
4.4.3 Operations on I/O port ....................................................................................................................96
CHAPTER 5 CLOCK GENERATOR ...................................................................................................... 97
5.1 Functions of Clock Generator .................................................................................................. 97
5.2 Configuration of Clock Generator............................................................................................97
5.3 Registers Controlling Clock Generator ................................................................................... 99
5.4 System Clock Oscillator.......................................................................................................... 106
5.4.1 X1 oscillator ..................................................................................................................................106
5.4.2 Subsystem clock oscillator............................................................................................................106
5.4.3 When subsystem clock is not used...............................................................................................109
5.4.4 Ring-OSC oscillator ......................................................................................................................109
5.4.5 Prescaler ......................................................................................................................................109
5.5 Clock Generator Operation ..................................................................................................... 110
5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock .......................... 117
5.7 Time Required for CPU Clock Switchover ............................................................................ 118
5.8 Clock Switching Flowchart and Register Setting................................................................. 119
5.8.1 Switching from Ring-OSC clock to X1 input clock ........................................................................119
5.8.2 Switching from X1 input clock to Ring-OSC clock ........................................................................120
5.8.3 Switching from X1 input clock to subsystem clock........................................................................121
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5.8.4 Switching from subsystem clock to X1 input clock........................................................................122
5.8.5 Register settings ...........................................................................................................................123
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ........................................................................... 124
6.1 Functions of 16-Bit Timer/Event Counter 00 ......................................................................... 124
6.2 Configuration of 16-Bit Timer/Event Counter 00................................................................... 125
6.3 Registers Controlling 16-Bit Timer/Event Counter 00 .......................................................... 129
6.4 Operation of 16-Bit Timer/Event Counter 00 ......................................................................... 135
6.4.1 Interval timer operation .................................................................................................................135
6.4.2 PPG output operations .................................................................................................................137
6.4.3 Pulse width measurement operations...........................................................................................140
6.4.4 External event counter operation ..................................................................................................148
6.4.5 Square-wave output operation......................................................................................................150
6.4.6 One-shot pulse output operation...................................................................................................152
6.5 Cautions for 16-Bit Timer/Event Counter 00 ......................................................................... 157
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 160
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................. 160
7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ...................................................... 162
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................. 164
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51........................................................... 169
7.4.1 Operation as interval timer............................................................................................................169
7.4.2 Operation as external event counter.............................................................................................171
7.4.3 Square-wave output operation......................................................................................................172
7.4.4 PWM output operation ..................................................................................................................173
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51............................................................. 177
CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 178
8.1 Functions of 8-Bit Timers H0 and H1 ..................................................................................... 178
8.2 Configuration of 8-Bit Timers H0 and H1............................................................................... 178
8.3 Registers Controlling 8-Bit Timers H0 and H1 ...................................................................... 182
8.4 Operation of 8-Bit Timers H0 and H1 ..................................................................................... 186
8.4.1 Operation as interval timer/square-wave output ...........................................................................186
8.4.2 Operation as PWM output mode...................................................................................................189
8.4.3 Carrier generator mode operation (8-bit timer H1 only) ................................................................195
CHAPTER 9 WATCH TIMER................................................................................................................ 202
9.1 Functions of Watch Timer ....................................................................................................... 202
9.2 Configuration of Watch Timer................................................................................................. 204
9.3 Register Controlling Watch Timer .......................................................................................... 204
9.4 Watch Timer Operations.......................................................................................................... 206
9.4.1 Watch timer operation...................................................................................................................206
9.4.2 Interval timer operation .................................................................................................................207
9.5 Cautions for Watch Timer ....................................................................................................... 208
CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 209
10.1 Functions of Watchdog Timer ................................................................................................ 209
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10.2 Configuration of Watchdog Timer.......................................................................................... 211
10.3 Registers Controlling Watchdog Timer ................................................................................. 212
10.4 Operation of Watchdog Timer ................................................................................................ 214
10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask option ......214
10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected
by mask option .............................................................................................................................215
10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped
by software” is selected by mask option)......................................................................................216
10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped
by software” is selected by mask option)......................................................................................218
CHAPTER 11 A/D CONVERTER ......................................................................................................... 219
11.1 Functions of A/D Converter .................................................................................................... 219
11.2 Configuration of A/D Converter.............................................................................................. 220
11.3 Registers Used in A/D Converter ........................................................................................... 222
11.4 A/D Converter Operations....................................................................................................... 227
11.4.1 Basic operations of A/D converter ................................................................................................227
11.4.2 Input voltage and conversion results ............................................................................................229
11.4.3 A/D converter operation mode......................................................................................................230
11.5 How to Read A/D Converter Characteristics Table .............................................................. 233
11.6 Cautions for A/D Converter..................................................................................................... 235
CHAPTER 12 SERIAL INTERFACE UART0 ...................................................................................... 240
12.1 Functions of Serial Interface UART0 ..................................................................................... 240
12.2 Configuration of Serial Interface UART0 ............................................................................... 241
12.3 Registers Controlling Serial Interface UART0 ...................................................................... 244
12.4 Operation of Serial Interface UART0...................................................................................... 249
12.4.1 Operation stop mode .................................................................................................................... 249
12.4.2 Asynchronous serial interface (UART) mode................................................................................250
12.4.3 Dedicated baud rate generator .....................................................................................................256
CHAPTER 13 SERIAL INTERFACE UART6 ...................................................................................... 261
13.1 Functions of Serial Interface UART6 ..................................................................................... 261
13.2 Configuration of Serial Interface UART6 ............................................................................... 265
13.3 Registers Controlling Serial Interface UART6 ...................................................................... 268
13.4 Operation of Serial Interface UART6...................................................................................... 276
13.4.1 Operation stop mode .................................................................................................................... 276
13.4.2 Asynchronous serial interface (UART) mode................................................................................277
13.4.3 Dedicated baud rate generator .....................................................................................................292
CHAPTER 14 SERIAL INTERFACE CSI10 ........................................................................................ 299
14.1 Functions of Serial Interface CSI10 ....................................................................................... 299
14.2 Configuration of Serial Interface CSI10 ................................................................................. 299
14.3 Registers Controlling Serial Interface CSI10 ........................................................................ 301
14.4 Operation of Serial Interface CSI10........................................................................................ 304
14.4.1 Operation stop mode ....................................................................................................................304
14.4.2 3-wire serial I/O mode ..................................................................................................................305
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CHAPTER 15 INTERRUPT FUNCTIONS ............................................................................................ 313
15.1 Interrupt Function Types ......................................................................................................... 313
15.2 Interrupt Sources and Configuration ..................................................................................... 313
15.3 Registers Controlling Interrupt Functions ............................................................................ 316
15.4 Interrupt Servicing Operations ............................................................................................... 323
15.4.1 Maskable interrupt request acknowledgment................................................................................323
15.4.2 Software interrupt request acknowledgment.................................................................................325
15.4.3 Multiple interrupt servicing ............................................................................................................326
15.4.4 Interrupt request hold....................................................................................................................329
CHAPTER 16 KEY INTERRUPT FUNCTION ..................................................................................... 330
16.1 Functions of Key Interrupt ...................................................................................................... 330
16.2 Configuration of Key Interrupt ................................................................................................ 330
16.3 Register Controlling Key Interrupt ......................................................................................... 331
CHAPTER 17 STANDBY FUNCTION .................................................................................................. 332
17.1 Standby Function and Configuration..................................................................................... 332
17.1.1 Standby function ...........................................................................................................................332
17.1.2 Registers controlling standby function ..........................................................................................334
17.2 Standby Function Operation ................................................................................................... 336
17.2.1 HALT mode...................................................................................................................................336
17.2.2 STOP mode..................................................................................................................................341
CHAPTER 18 RESET FUNCTION........................................................................................................ 345
18.1 Register for Confirming Reset Source................................................................................... 351
CHAPTER 19 CLOCK MONITOR ........................................................................................................ 352
19.1 Functions of Clock Monitor..................................................................................................... 352
19.2 Configuration of Clock Monitor .............................................................................................. 352
19.3 Register Controlling Clock Monitor........................................................................................ 353
19.4 Operation of Clock Monitor ..................................................................................................... 354
CHAPTER 20 POWER-ON-CLEAR CIRCUIT...................................................................................... 359
20.1 Functions of Power-on-Clear Circuit...................................................................................... 359
20.2 Configuration of Power-on-Clear Circuit ............................................................................... 360
20.3 Operation of Power-on-Clear Circuit...................................................................................... 360
20.4 Cautions for Power-on-Clear Circuit ...................................................................................... 361
CHAPTER 21 LOW-VOLTAGE DETECTOR ....................................................................................... 363
21.1 Functions of Low-Voltage Detector........................................................................................ 363
21.2 Configuration of Low-Voltage Detector ................................................................................. 363
21.3 Registers Controlling Low-Voltage Detector ........................................................................ 364
21.4 Operation of Low-Voltage Detector........................................................................................ 367
21.5 Cautions for Low-Voltage Detector ........................................................................................ 371
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CHAPTER 22 MASK OPTIONS ........................................................................................................... 375
CHAPTER 23 µPD78F0114................................................................................................................... 376
23.1 Internal Memory Size Switching Register ............................................................................. 377
23.2 Writing with Flash Programmer.............................................................................................. 378
23.3 Programming Environment..................................................................................................... 385
23.4 Communication Mode ............................................................................................................. 385
23.5 Handling of Pins on Board ...................................................................................................... 388
23.5.1 VPP pin ..........................................................................................................................................388
23.5.2 Serial interface pins ......................................................................................................................389
23.5.3 RESET pin.................................................................................................................................... 391
23.5.4 Port pins .......................................................................................................................................391
23.5.5 Other signal pins........................................................................................................................... 391
23.5.6 Power supply ................................................................................................................................391
23.6 Programming Method.............................................................................................................. 392
23.6.1 Controlling flash memory..............................................................................................................392
23.6.2 Flash memory programming mode ...............................................................................................393
23.6.3 Selecting communication mode....................................................................................................393
23.6.4 Communication commands ..........................................................................................................394
CHAPTER 24 INSTRUCTION SET ...................................................................................................... 395
24.1 Conventions Used in Operation List...................................................................................... 395
24.1.1 Operand identifiers and specification methods .............................................................................395
24.1.2 Description of operation column ...................................................................................................396
24.1.3 Description of flag operation column ............................................................................................396
24.2 Operation List........................................................................................................................... 397
24.3 Instructions Listed by Addressing Type ............................................................................... 405
CHAPTER 25 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS, (A) GRADE PRODUCTS)................................................ 408
CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................ 426
CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 445
CHAPTER 28 PACKAGE DRAWING .................................................................................................. 458
CHAPTER 29 RECOMMENDED SOLDERING CONDITIONS........................................................... 459
CHAPTER 30 CAUTIONS FOR WAIT ................................................................................................ 461
30.1 Cautions for Wait ..................................................................................................................... 461
30.2 Peripheral Hardware That Generates Wait ............................................................................ 462
30.3 Example of Wait Occurrence .................................................................................................. 463
APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 464
A.1 Software Package .................................................................................................................... 467
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Page 16
A.2 Language Processing Software.............................................................................................. 467
A.3 Control Software ...................................................................................................................... 468
A.4 Flash Memory Writing Tools ................................................................................................... 468
A.5 Debugging Tools (Hardware) .................................................................................................. 469
A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A .................................................469
A.5.2 When using in-circuit emulator IE-78K0K1-ET..............................................................................470
A.6 Debugging Tools (Software) ................................................................................................... 471
A.7 Embedded Software................................................................................................................. 472
APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 473
APPENDIX C REGISTER INDEX ......................................................................................................... 475
C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 475
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 478
APPENDIX D REVISION HISTORY ..................................................................................................... 481
D.1 Major Revisions in This Edition .............................................................................................. 481
16
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CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.2
input clock) to ultra low-speed (122
{ General-purpose registers: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
µ
s: @ 32.768 kHz operation with subsystem clock)
µ
s: @ 10 MHz operation with X1
Item
Part Number
µ
PD780111 8 KB
µ
PD780112 16 KB
µ
PD780113 24 KB
µ
PD780114
µ
PD78F0114 Flash memory 32 KB
Mask ROM
Program Memory
(ROM)
32 KB
512 bytes
1024 bytes
Note
1024 bytes
Note
Data Memory
(Internal High-Speed RAM)
Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the on-chip Ring-OSC
{ On-chip clock monitor function using on-chip Ring-OSC
{ On-chip watchdog timer (operable with Ring-OSC clock)
{ On-chip key interrupt function
{ I/O ports: 32 (N-ch open drain: 4)
{ Timer: 7 channels
{ Serial interface: 3 channels
(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART
Note
: 1 channel)
{ 10-bit resolution A/D converter: 8 channels
{ Supply voltage: V
DD = 2.7 to 5.5 V (standard product, (A) grade product)
VDD = 3.3 to 5.5 V ((A1) grade product, (A2) grade product)
{ Operating ambient temperature: T
T
A = −40 to +85°C (standard product, (A) grade product)
A = −40 to +105°C (flash memory version of (A1) grade product)
TA = −40 to +110°C (mask ROM version of (A1) grade product)
T
A = −40 to +125°C (mask ROM version of (A2) grade product)
Note Select either of the functions of these alternate-function pins.
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CHAPTER 1 OUTLINE
1.2 Applications
{ Automotive equipment
• System control for body electricals (power windows, keyless entry reception, etc.)
• Sub-microcontrollers for control
{ Home audio, car audio
{ AV equipment
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
• Outdoor air conditioner units
• Microwave ovens, electric rice cookers
{ Industrial equipment
• Pumps
• Vending machines
• FA (Factory Automation)
18
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Page 19
CHAPTER 1 OUTLINE
1.3 Ordering Information
Part Number Package Quality Grade
µ
PD780111GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD780112GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD780113GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD780114GB-×××-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD780111GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780112GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780113GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780114GB(A)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780111GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780112GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780113GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780114GB(A1)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780111GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780112GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780113GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD780114GB(A2)-×××-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M1GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M2GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M3GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M4GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M5GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M6GB-8ES 44-pin plastic LQFP (10 × 10) Standard
µ
PD78F0114M1GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M2GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M3GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M4GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M5GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M6GB(A)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M1GB(A1)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M2GB(A1)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M5GB(A1)-8ES 44-pin plastic LQFP (10 × 10) Special
µ
PD78F0114M6GB(A1)-8ES 44-pin plastic LQFP (10 × 10) Special
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Electronics Corporation to know the specification of the quality grade on the device and its
recommended applications.
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Page 20
CHAPTER 1 OUTLINE
Mask ROM versions (µPD780111, 780112, 780113, and 780114) include mask options. When ordering, it is
possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be
stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to
P63)”.
Flash memory versions corresponding to the mask options of the mask ROM versions are as follows.
Table 1-1. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions
Flash Memory Versions
(Part Number)
µ
PD78F0114M1GB-8ES
µ
PD78F0114M1GB(A)-8ES
µ
PD78F0114M1GB(A1)-8ES
µ
PD78F0114M2GB-8ES
µ
PD78F0114M2GB(A)-8ES
µ
PD78F0114M2GB(A1)-8ES
µ
PD78F0114M3GB-8ES
µ
PD78F0114M3GB(A)-8ES
µ
PD78F0114M4GB-8ES
µ
PD78F0114M4GB(A)-8ES
µ
PD78F0114M5GB-8ES
µ
PD78F0114M5GB(A)-8ES
µ
PD78F0114M5GB(A1)-8ES
µ
PD78F0114M6GB-8ES
µ
PD78F0114M6GB(A)-8ES
µ
PD78F0114M6GB(A1)-8ES
POC Circuit Ring-OSC
POC cannot be used
POC used (VPOC = 2.85 V ±0.15 V)
POC used (VPOC = 3.5 V ±0.2 V)
Mask Option
Cannot be stopped
Can be stopped by software
Cannot be stopped
Can be stopped by software
Cannot be stopped
Can be stopped by software
20
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Page 21
1.4 Pin Configuration (Top View)
• 44-pin plastic LQFP (10 × 10)
44 43 42 41 40 39 38 37 36 35 34
REF
AV
AV
IC (VPP)
V
V
X1
X2
RESET
XT1
XT2
P130
SS
DD
SS
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
P20/ANI0
P21/ANI1
P22/ANI2
CHAPTER 1 OUTLINE
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P70/KR0
P71/KR1
P72/KR2
33
32
31
30
29
28
27
26
25
24
23
P73/KR3
P00/TI000
P01/TI010/TO00
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
DD
EV
P60
P61
P62
P63
P32/INTP3
P31/INTP2
P120/INTP0
P33/TI51/TO51/INTP4
P30/INTP1
P17/TI50/TO50
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVSS pin to VSS.
3. Connect the V
PP pin to EVSS or VSS during normal operation.
Remark Figures in parentheses apply only to the
µ
PD78F0114.
SS
EV
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CHAPTER 1 OUTLINE
Pin Identification
ANI0 to ANI7: Analog input
AV
REF: Analog reference voltage
AV
SS: Analog ground
EV
DD: Power supply for port
EV
SS: Ground for port
IC: Internally connected
INTP0 to INTP5: External interrupt input
KR0 to KR3: Key return
P00, P01: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P33: Port 3
P60 to P63: Port 6
P70 to P73: Port 7
P120: Port 12
P130: Port 13
RESET: Reset
RxD0, RxD6: Receive data
SCK10: Serial clock input/output
SI10: Serial data input
SO10: Serial data output
TI000, TI010,
TI50, TI51: Timer input
TO00, TO50, TO51,
TOH0, TOH1: Timer output
TxD0, TxD6: Transmit data
V
DD: Power supply
V
PP: Programming power supply
V
SS: Ground
X1, X2: Crystal oscillator (X1 input clock)
XT1, XT2: Crystal oscillator (Subsystem clock)
22
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1.5 K1 Family Lineup
1.5.1 78K0/Kx1 product lineup
78K0/KB1: 30-pin (7.62 mm 0.65 mm pitch)
µ
PD78F0103 Flash memory: 24 KB, RAM: 768 bytes
PD780103
µ
PD780102
µ
PD780101
µ
78K0/KC1: 44-pin (10 × 10 mm 0.8 mm pitch)
PD78F0114 Flash memory: 32 KB, RAM: 1 KB
µ
µ
PD780114
PD780113
µ
PD780112
µ
Mask ROM: 24 KB, RAM: 768 bytes
Mask ROM: 16 KB, RAM: 768 bytes
Mask ROM: 8 KB, RAM: 512 bytes
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
PD780111
µ
Mask ROM: 8 KB, RAM: 512 bytes
CHAPTER 1 OUTLINE
78K0/KD1: 52-pin (10 × 10 mm 0.65 mm pitch)
PD78F0124 Flash memory: 32 KB, RAM: 1 KB
µ
PD780124
µ
PD780123
µ
PD780122
µ
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
PD780121
µ
Mask ROM: 8 KB, RAM: 512 bytes
78K0/KE1: 64-pin (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
PD78F0134 Flash memory:
µ
PD780134
µ
PD780133
µ
PD780132
µ
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
PD780131
µ
32 KB, RAM: 1 KB
Mask ROM: 16 KB, RAM: 512 bytes
Mask ROM: 8 KB, RAM: 512 bytes
PD78F0138 Flash memory:
µ
PD780138
µ
PD780136
µ
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM:
78K0/KF1: 80-pin (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
PD78F0148 Flash memory: 60 KB, RAM: 2 KB
µ
PD780148
µ
PD780146
µ
PD780144
µ
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM: 48 KB, RAM: 2 KB
Mask ROM: 32 KB, RAM: 1 KB
PD780143
µ
Mask ROM: 24 KB, RAM: 1 KB
60 KB, RAM: 2 KB
48 KB, RAM
:
2 KB
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CHAPTER 1 OUTLINE
The list of functions in the 78K0/Kx1 is shown below.
Part Number
Item
Package 30 pins 44 pins 52 pins 64 pins 80 pins
Internal
memory
(bytes)
Flash memory
RAM 512 768 512 1 K 512 1 K 512 1 K 2 K 1 K 2 K
Power supply voltage VDD = 2.7 to 5.5 V
Minimum instruction execution time 0.2 µs (when 10 MHz, VDD =
Clock
X1 input 2 to 10 MHz
Sub
Ring-OSC 240 kHz (TYP.)
Port
CMOS I/O 17 19 26 38 54
CMOS input 4 8
CMOS output 1
N-ch open-drain I/O
Timer
16 bits (TM0) 1 ch 2 ch 1 ch 2 ch
8 bits (TM5) 1 ch 2 ch
8 bits (TMH) 2 ch
For watch
WDT 1 ch
Serial
interface
3-wire CSI
Automatic transmit/
Note
1 ch 2 ch 1 ch 2 ch
receive 3-wire CSI
Note
UART
UART supporting LIN-bus 1 ch
10-bit A/D converter 4 ch 8 ch
External 6 7 8 9 9 Interrupt
Internal 11 12 15 16 19 17 20
Key return input
Reset
RESET pin Provided
POC 2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by mask option)
LVI 3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software)
Clock monitor Provided
WDT Provided
Multiplier/divider
ROM correction
Standby function HALT/STOP mode
Operating ambient temperature Standard products, special (A) products: −40 to +85°C
78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1
16 K 8 K 24 K 8 K 24 K 8 K 24 K 48 K 24 K 48 KMask ROM 8 K
−
24 K
−
16 K 32 K
24 K
4.0 to 5.5 V)
µ
s (when 8.38 MHz, VDD =
0.24
3.3 to 5.5 V)
µ
s (when 5 MHz, VDD = 2.7
0.4
−
−
16 K 32 K
32 K
32 K
−
<Connect REGC pin to V
µ
s (when 10 MHz, VDD = 4.0 to 5.5 V)
0.2
µ
s (when 8.38 MHz, VDD = 3.3 to 5.5 V)
0.24
µ
s (when 5 MHz, VDD = 2.7 to 5.5 V)
0.4
−
16 K 32 K
−
DD>
−
32 K
60 K
−
−
60 K
32 K 60 K
−
to 5.5 V)
−
−
−
−
−
−
4 ch 8 ch
−
−
32.768 kHz
4
1 ch
1 ch
16 bits × 16 bits, 32 bits ÷ 16 bits
Provided
1 ch
−
Special (A1) products: −40 to +110°C (mask ROM version),
−40 to +105°C (flash memory version)
Special (A2) products: −40 to +125°C (mask ROM version)
−
60 K
Note Select either of the functions of these alternate-function pins.
24
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1.5.2 V850ES/Kx1 product lineup
V850ES/KF1
CHAPTER 1 OUTLINE
80-pin plastic QFP (14 ×
14)
80-pin plastic TQFP (fine pitch) (12 ×
µ
PD703208
µ
PD703208Y
µ
PD703209
µ
PD703209Y
PD703210
µ
PD703210Y
µ
µ
PD70F3210
µ
PD70F3210Y
Mask ROM: 64 KB, RAM: 4 KB
2
I
C products
Mask ROM: 96 KB, RAM: 4 KB
2
I
C products
Mask ROM: 128 KB, RAM: 6 KB
2
I
C products
Flash memory: 128 KB, RAM: 6 KB
2
I
C products
12)
V850ES/KG1
V850ES/KJ1
100-pin plastic LQFP (fine pitch) (14 ×
µ
PD703212
PD703212Y
µ
PD703213
µ
PD703213Y
µ
µ
PD703214
µ
PD703214Y
PD70F3214
µ
µ
PD70F3214Y
Mask ROM: 64 KB, RAM: 4 KB
2
I
C products
Mask ROM: 96 KB, RAM: 4 KB
2
I
C products
Mask ROM: 128 KB, RAM: 6 KB
2
I
C products
Flash memory: 128 KB, RAM: 6 KB
2
I
C products
14)
144-pin plastic LQFP (fine pitch) (20 × 20)
µ
PD703216
µ
PD703216Y
µ
PD703217
µ
PD703217Y
Mask ROM: 96 KB, RAM: 6 KB
2
I
C products
Mask ROM: 128 KB, RAM: 6 KB
2
I
C products
PD70F3217
µ
PD70F3217Y
µ
Flash memory: 128 KB, RAM: 6 KB
2
I
C products
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Page 26
CHAPTER 1 OUTLINE
The list of functions in the V850ES/Kx1 is shown below.
Timer Serial Interface Function
Part No.
µ
PD703208
µ
PD703208Y
µ
PD703209
µ
PD703209Y
µ
PD703210
V850ES/KF1
µ
PD703210Y
µ
PD70F3210
µ
PD70F3210Y
µ
PD703212
µ
PD703212Y
µ
PD703213
µ
PD703213Y
µ
PD703214
V850ES/KG1
µ
PD703214Y
µ
PD70F3214
µ
PD70F3214Y
µ
PD703216
µ
PD703216Y
µ
PD703217
µ
PD703217Y
V850ES/KJ1
µ
PD70F3217
µ
PD70F3217Y
8-Bit 16-Bit TMH Watch WDT CSI CSIA UART I
2 ch 2 ch 2 ch 1 ch 2 ch 2 ch 1 ch 2 ch
2 ch 4 ch 2 ch 1 ch 2 ch 2 ch 2 ch 2 ch
2 ch 6 ch 2 ch 1 ch 2 ch 3 ch 2 ch 3 ch
A/D D/A RTO I/O Other
2
C
8 ch – 6 ch 67 –
–
1 ch
–
1 ch
–
1 ch
–
1 ch
8 ch 2 ch 6 ch 84 –
–
1 ch
–
1 ch
–
1 ch
–
1 ch
16 ch 2 ch 12 ch 128 –
–
2 ch
–
2 ch
–
2 ch
26
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1.6 Block Diagram
CHAPTER 1 OUTLINE
TO00/TI010/P01
TI000/P00
TOH0/P15
TOH1/P16
TI50/TO50/P17
TI51/TO51/P33
RxD0/P11
TxD0/P10
RxD6/P14
TxD6/P13
16-bit timer/
event counter 00
8-bit timer H0
8-bit timer H1
8-bit timer/
event counter 50
8-bit timer/
event counter 51
Watch timer
Watchdog timer
Serial
interface UART0
Serial
interface UART6
78K/0
CPU
core
Internal
high-speed
RAM
ROM
(flash
memory)
Port 0
Port 1
Port 2
Port 3
Port 6
Port 7
Port 12
Port 13 P130
Clock monitor
Power on clear/
low voltage
indicator
Key return
2
P00, P01
8
P10 to P17
8
P20 to P27
4
P30 to P33
4
P60 to P63
4
P70 to P73
P120
POC/LVI
control
KR0/P70 to
4
KR3/P73
SI10/P11
SO10/P12
SCK10/P10
ANI0/P20 to
ANI7/P27
AV
REF
AV
SS
Serial
interface CSI10
8
A/D converter
INTP0/P120
INTP1/P30 to
INTP4/P33
4
Interrupt control
INTP5/P16
Remark Items in parentheses are available only in the
V
EV
VSS,
DD
,
EV
DD
µ
IC
(V
SS
PP
)
PD78F0114.
Reset control
Ring-OSC
System control
RESET
X1
X2
XT1
XT2
User’s Manual U16227EJ2V0UD
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CHAPTER 1 OUTLINE
1.7 Outline of Functions
Item
Internal memory
ROM 8 KB 16 KB 24 KB 32 KB 32 KB
High-speed RAM 512 bytes 1 KB 1 KB
Memory space 64 KB
X1 input clock (oscillation frequency) Ceramic/crystal/external clock oscillation
Standard
products, (A)
grade products
(A1) grade
products
(A2) grade
products
Ring-OSC clock
(oscillation frequency)
Subsystem clock
(oscillation frequency)
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
Instruction set • 16-bit operation
I/O ports
Timers • 16-bit timer/event counter: 1 channel
Timer outputs 5 (PWM outputs: 3)
A/D converter 10-bit resolution × 8 channels
Serial interface • UART mode supporting LIN-bus: 1 channel
Notes 1. The internal flash memory capacity and internal high-speed RAM capacity can be changed using the
internal memory size switching register (IMS).
2. Select either of the functions of these alternate-function pins.
µ
PD780111
µ
PD780112
µ
PD780113
µ
PD780114
µ
PD78F0114
Note 1
(flash memory)
Note 1
10 MHz (V
10 MHz (V
8.38 MHz (V
DD = 4.0 to 5.5 V), 8.38 MHz (VDD = 3.3 to 5.5 V), 5 MHz (VDD = 2.7 to 5.5 V)
DD = 4.5 to 5.5 V), 8.38 MHz (VDD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V)
DD = 4.0 to 5.5 V), 5 MHz (VDD = 3.3 to 5.5 V)
On-chip Ring oscillation (240 kHz (TYP.))
Crystal/external clock oscillation (32.768 kHz)
0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (X1 input clock: @ fXP = 10 MHz operation)
8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.)
operation)
122
µ
s (subsystem clock: @ fXT = 32.768 kHz operation)
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
Total: 32
CMOS I/O 19
CMOS input 8
CMOS output 1
N-ch open-drain I/O 4
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 2 channels
• Watch timer 1 channel
• Watchdog timer: 1 channel
• 3-wire serial I/O mode/UART mode
Note 2
: 1 channel
(1/2)
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CHAPTER 1 OUTLINE
Item
µ
PD780111
µ
PD780112
µ
PD780113
µ
PD780114
µ
PD78F0114
Internal 15 Vectored interrupt
sources
External 7
Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR3).
Reset • Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by clock monitor
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
Supply voltage
Operating ambient temperature
Standard products, (A) grade products: V
(A1) grade products, (A2) grade products: V
• Standard products, (A) grade products: T
• (A1) grade products: T
A = −40 to +110°C (mask ROM versions),
DD = 2.7 to 5.5 V
DD = 3.3 to 5.5 V
A = −40 to +85°C
−40 to +105°C (flash memory versions)
• (A2) grade products: T
A = −40 to +125°C (mask ROM versions)
Package • 44-pin plastic LQFP (10 × 10)
An outline of the timer is shown below.
Operation
mode
Function
16-Bit Timer/
Event Counter 00
8-Bit Timer/
Event Counters
8-Bit Timers H0 and
H1
Watch
Timer
50 and 51
TM00 TM50 TM51 TMH0 TMH1
Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel
External event counter 1 channel 1 channel 1 channel
Timer output 1 output 1 output 1 output 1 output 1 output
PPG output 1 output
PWM output
−
Pulse width measurement 2 inputs
− − − − − −
1 output 1 output 1 output 1 output
− − − − − −
Square-wave output 1 output 1 output 1 output 1 output 1 output
− − − −
− −
− −
− −
Interrupt source 2 1 1 1 1 1
Note
Watchdog
Timer
1 channel
Note The watch timer function and interval timer function can be used simultaneously.
Remark TM51 and TMH1 can be used in combination as a carrier generator mode.
(2/2)
−
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CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AV
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
EVDD Port pins other than P20 to P27
VDD Pins other than port pins
(1) Port pins (1/2)
Pin Name I/O Function After Reset Alternate Function
P00 TI000
P01
P10 SCK10/TxD0
P11 SI10/RxD0
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
P20 to P27 Input
P30 to P32 INTP1 to INTP3
P33
P60 to P63 I/O
P70 to P73 I/O
I/O
I/O
I/O
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 2.
8-bit input-only port.
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 6.
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
Port 7.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
REF, EVDD, and VDD. The relationship between these
Input
TI010/TO00
Input
TI50/TO50
Input ANI0 to ANI7
Input
INTP4/TI51/TO51
Input
Input KR0 to KR3
−
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CHAPTER 2 PIN FUNCTIONS
(1) Port pins (2/2)
Pin Name I/O Function After Reset Alternate Function
P120 I/O
P130 Output
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 13.
1-bit output-only port.
Input INTP0
Output
−
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name I/O Function After Reset Alternate Function
INTP0 P120
Input
INTP1 to INTP3 P30 to P32
INTP4 P33/TI51/TO51
INTP5
External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Input
P16/TOH1
SI10 Input Serial data input to serial interface Input P11/RxD0
SO10 Output Serial data output from serial interface Input P12
SCK10 I/O Clock input/output for serial interface Input P10/TxD0
RxD0 P11/SI10
RxD6
TxD0 P10/SCK10
TxD6
TI000
Input Serial data input to asynchronous serial interface Input
Output Serial data output from asynchronous serial interface Input
Input
External count clock input to 16-bit timer/event counter 00
Input
P14
P13
P00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
TI010
Capture trigger input to capture register (CR000) of 16-bit
P01/TO00
timer/event counter 00
TO00 Output 16-bit timer/event counter 00 output Input P01/TI010
TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50
TI51
TO50 8-bit timer/event counter 50 output P17/TI50
Input
Output
External count clock input to 8-bit timer/event counter 51
Input
P33/TO51/INTP4
Input
TO51 8-bit timer/event counter 51 output P33/TI51/INTP4
TOH0 8-bit timer H0 output P15
TOH1
8-bit timer H1 output
P16/INTP5
ANI0 to ANI7 Input A/D converter analog input Input P20 to P27
AVREF Input
A/D converter reference voltage input and positive power
− −
supply for port 2
AVSS
A/D converter ground potential. Make the same potential as
−
SS or VSS.
EV
− −
KR0 to KR3 Input Key interrupt input Input P70 to P73
RESET Input System reset input
X1 Input
X2
XT1 Input
XT2
VDD
EVDD
VSS
EVSS
IC
VPP
Connecting resonator for X1 input clock
−
Connecting resonator for subsystem clock
−
Positive power supply (except for ports)
−
Positive power supply for ports
−
Ground potential (except for ports)
−
Ground potential for ports
−
Internally connected. Connect directly to EVSS or VSS.
−
Flash memory programming mode setting. High-voltage
−
application for program write/verify. Connect to EV
SS or VSS in
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
− −
normal operation mode.
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CHAPTER 2 PIN FUNCTIONS
2.2 Description of Pin Functions
2.2.1 P00 and P01 (port 0)
P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 and P01 function as a 2-bit I/O port. P00 and P01 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 and P01 function as timer I/O.
(a) TI000
This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000 or CR001) of 16-bit timer/event counter 00.
(b) TI010
This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event
counter 00.
(c) TO00
This is a timer output pin.
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CHAPTER 2 PIN FUNCTIONS
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD0 and RxD6
These are the serial data input pins of the asynchronous serial interface.
(e) TxD0 and TxD6
These are the serial data output pins of the asynchronous serial interface.
(f) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit input-only port.
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI7/P27 in 11.6 Cautions for A/D Converter.
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CHAPTER 2 PIN FUNCTIONS
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins and timer I/O pins.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
2.2.5 P60 to P63 (port 6)
P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for
mask ROM versions.
2.2.6 P70 to P73 (port 7)
P70 to P73 function as a 4-bit I/O port. These pins also function as key interrupt input pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P73 function as a 4-bit I/O port. P70 to P73 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P73 function as key interrupt input pins.
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CHAPTER 2 PIN FUNCTIONS
2.2.7 P120 (port 12)
P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.
The following operation modes can be specified.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of
an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
(2) Control mode
P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.8 P130 (port 13)
P130 functions as a 1-bit output-only port.
2.2.9 AV
REF
This is the A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin directly to EV
DD or VDD
Note
.
Note Connect port 2 directly to EV
DD when it is used as a digital port.
2.2.10 AV
SS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EV
SS pin or VSS pin.
2.2.11 RESET
This is the active-low system reset input pin.
2.2.12 X1 and X2
These are the pins for connecting a resonator for X1 input clock.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
2.2.13 XT1 and XT2
These are the pins for connecting a resonator for subsystem clock.
When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.
2.2.14 V
DD and EVDD
V
DD is the positive power supply pin for other than ports.
EV
DD is the positive power supply pin for ports.
2.2.15 V
SS and EVSS
V
SS is the ground potential pin for other than ports.
EV
SS is the ground potential pin for ports.
2.2.16 V
PP (flash memory versions only)
This is a pin for flash memory programming mode setting and high-voltage application for program write/verify.
Connect to EV
SS or VSS in the normal operation mode.
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CHAPTER 2 PIN FUNCTIONS
2.2.17 IC (mask ROM versions only)
The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KC1 at shipment. Connect it
directly to EV
When a potential difference is produced between the IC pin and the EV
SS or VSS pin with the shortest possible wire in the normal operation mode.
SS or VSS pin because the wiring between
these two pins is too long or external noise is input to the IC pin, the user’s program may not operate normally.
• Connect the IC pin directly to EV
SS or VSS.
SS
or V
ICEV
SS
As short as possible
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CHAPTER 2 PIN FUNCTIONS
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
P12/SO10
8-A
5-A
I/O
Input: Independently connect to EV
Output: Leave open.
P13/TxD6
P14/RxD6 8-A
P15/TOH0 5-A
P16/TOH1/INTP5
8-A
P17/TI50/TO50
P20/ANI0 to P27/ANI7 9-C Input Connect to EVDD or EVSS.
P30/INTP1 to P32/INTP3
8-A
P33/TI51/TO51/INTP4
P60, P61 (Mask ROM version) 13-S
P60, P61 (Flash memory version) 13-R
P62, P63 (Mask ROM version) 13-V
I/O
Input: Independently connect to EV
Output: Leave open.
Input: Connect to EV
SS.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
P62, P63 (Flash memory version) 13-W
P70/KR0 to P73/KR3
P120/INTP0
8-A
Input: Independently connect to EV
Output: Leave open.
P130 3-C Output Leave open.
RESET 2
XT1
16
XT2
AVREF Connect directly to EVDD or VDD
−
AVSS
Input
Connect directly to EVDD or VDD.
Leave open.
−
Connect directly to EV
SS or VSS.
IC
VPP
Connect to EVSS or VSS.
Note Connect port 2 directly to EV
DD when it is used as a digital port.
DD or EVSS via a resistor.
DD or EVSS via a resistor.
DD or EVSS via a resistor.
−
Note
.
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CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (1/2)
Type 2
Type 8-A
EV
DD
IN
Schmitt-triggered input with hysteresis characteristics
Type 3-C
EV
DD
P-ch
Data
OUT
N-ch
Pull-up
enable
Data
Output
disable
Type 9-C
IN
P-ch
N-ch
AV
SS
(threshold voltage)
V
V
P-ch
DD
P-ch
IN/OUT
N-ch
Comparator
+
–
REF
Type 5-A
Pull-up
enable
Data
Output
disable
Input
enable
V
DD
P-ch
N-ch
EV
DD
P-ch
IN/OUT
Type 13-R
Output disable
Data
Input
enable
IN/OUT
N-ch
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Type 13-S
Output disable
Data
CHAPTER 2 PIN FUNCTIONS
Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-W
EV
N-ch
DD
IN/OUT
Output disable
Mask
option
Input
enable
Data
Middle-voltage input buffer
IN/OUT
N-ch
Type 13-V
Output disable
Input
enable
Data
Middle-voltage input buffer
Mask
option
N-ch
EV
Type 16
DD
Feedback
cut-off
IN/OUT
P-ch
XT1 XT2
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
78K0/KC1 products can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory maps.
Caution Regardless of the internal memory capacity, the initial value of the internal memory size
switching register (IMS) of all 78K0/KC1 products is fixed (IMS = CFH). Therefore, set the value
corresponding to each product as indicated below.
Table 3-1. Set Value of Internal Memory Size Switching Register (IMS)
Internal Memory Size Switching Register (IMS)
µ
PD780111 42H
µ
PD780112 44H
µ
PD780113 C6H
µ
PD780114 C8H
µ
PD78F0114 Value corresponding to mask ROM version
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Data memory
space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-1. Memory Map (µPD780111)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FD00H
FCFFH
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
1FFFH
Program area
1000H
0FFFH
Program
memory
space
2000H
1FFFH
0000H
Reserved
Internal ROM
8192 × 8 bits
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
CALLF entry area
Program area
CALLT table area
Vector table area
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Data memory
space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (µPD780112)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FD00H
FCFFH
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
Reserved
3FFFH
Program area
1000H
0FFFH
CALLF entry area
0800H
07FFH
Program area
0080H
007FH
0040H
003FH
0000H
CALLT table area
Vector table area
Program
memory
space
4000H
3FFFH
Internal ROM
16384 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (µPD780113)
Data memory
space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Reserved
5FFFH
Program area
1000H
0FFFH
CALLF entry area
0800H
07FFH
Program area
0080H
007FH
0040H
003FH
0000H
CALLT table area
Vector table area
Program
memory
space
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
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Data memory
space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Memory Map (µPD780114)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
7FFFH
Program area
1000H
0FFFH
Program
memory
space
8000H
7FFFH
0000H
Reserved
Internal ROM
32768 × 8 bits
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
CALLF entry area
Program area
CALLT table area
Vector table area
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Data memory
space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-5. Memory Map (µPD78F0114)
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
Special function
registers (SFRs)
256 × 8 bits
General-purpose
registers
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Reserved
7FFFH
Program area
1000H
0FFFH
CALLF entry area
0800H
07FFH
Program area
0080H
007FH
0040H
003FH
0000H
CALLT table area
Vector table area
Program
memory
space
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/KC1 products incorporate internal ROM (mask ROM or flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
µ
PD780111 8192 × 8 bits (0000H to 1FFFH)
µ
PD780112 16384 × 8 bits (0000H to 3FFFH)
µ
PD780113 24576 × 8 bits (0000H to 5FFFH)
µ
PD780114
µ
PD78F0114 Flash memory 32768 × 8 bits (0000H to 7FFFH)
Mask ROM
32768 × 8 bits (0000H to 7FFFH)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address Interrupt Source Vector Table Address Interrupt Source
RESET input, POC, LVI,
clock monitor, WDT
0004H INTLVI 001CH INTTMH0
0006H INTP0 001EH INTTM50
0008H INTP1 0020H INTTM000
000AH INTP2 0022H INTTM010
000CH INTP3 0024H INTAD
000EH INTP4 0026H INTSR0
0010H INTP5 0028H INTWTI
0012H INTSRE6 002AH INTTM51
0014H INTSR6 002CH INTKR
0016H INTST6 002EH INTWT
0018H INTCSI10/INTST0 0000H
001AH INTTMH1
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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CHAPTER 3 CPU ARCHITECTURE
3.1.2 Internal data memory space
78K0/KC1 products incorporate the following internal high-speed RAMs.
Table 3-4. Internal High-Speed RAM Capacity
Part Number Internal Expansion RAM
µ
PD780111
µ
PD780112
µ
PD780113
µ
PD780114
µ
PD78F0114
512 × 8 bits (FD00H to FEFFH)
1024 × 8 bits (FB00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-5 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
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3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/KC1, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-6 to 3-10 show correspondence between data memory and addressing. For the details of
each addressing mode, see 3.4 Operand Address Addressing.
Figure 3-6. Correspondence Between Data Memory and Addressing (
µ
PD780111)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
General-purpose registers
Special function
registers (SFRs)
256 × 8 bits
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
SFR addressing
Register addressing
Short direct
addressing
FD00H
FCFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
2000H
1FFFH
Internal ROM
8192 × 8 bits
0000H
Based indexed
addressing
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Figure 3-7. Correspondence Between Data Memory and Addressing (µPD780112)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
FD00H
FCFFH
General-purpose registers
Special function
registers (SFRs)
256 × 8 bits
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Reserved
4000H
3FFFH
Internal ROM
16384 × 8 bits
0000H
Based indexed
addressing
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Figure 3-8. Correspondence Between Data Memory and Addressing (µPD780113)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
FB00H
FAFFH
General-purpose registers
Special function
registers (SFRs)
256 × 8 bits
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Reserved
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
Based indexed
addressing
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Figure 3-9. Correspondence Between Data Memory and Addressing (µPD780114)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
FB00H
FAFFH
General-purpose registers
Special function
registers (SFRs)
256 × 8 bits
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Reserved
8000H
7FFFH
Internal ROM
32768 × 8 bits
0000H
Based indexed
addressing
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Figure 3-10. Correspondence Between Data Memory and Addressing (µPD78F0114)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
FE20H
FE1FH
FB00H
FAFFH
General-purpose registers
Special function
registers (SFRs)
256 × 8 bits
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
SFR addressing
Register addressing
Short direct
addressing
Direct addressing
Register indirect
addressing
Based addressing
Reserved
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
Based indexed
addressing
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3.2 Processor Registers
78K0/KC1 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses, and stack memory. The control registers consist of
a program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI, and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-12. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 0 ISP CY
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(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupts are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L) (refer
to 15.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) cannot be acknowledged. Actual
interrupt request acknowledgment is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
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Figure 3-13. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using
the stack.
Figure 3-14. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) Interrupt, BRK instructions (when SP = FEE0H)
SP
FEE0H
FEE0H
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SP
FEDDH
FEDFH
FEDEH
FEDDH
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PC15 to PC8
PC7 to PC0
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Figure 3-15. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
Register pair higher
Register pair lower
(b) RET instruction (when SP = FEDEH)
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
PC15 to PC8
PC7 to PC0
(c) RETI, RETB instructions (when SP = FEDDH)
SP
FEE0H
FEE0H
SP
FEDDH
FEDFH
FEDEH
FEDDH
PSW
PC15 to PC8
PC7 to PC0
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-16. Configuration of General-Purpose Registers
(a) Absolute name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
RP3
RP2
RP1
RP0
15 0 7 0
R7
R6
R5
R4
R3
R2
R1
R0
(b) Function name
16-bit processing 8-bit processing
FEFFH
FEF8H
FEF0H
FEE8H
FEE0H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
AX
15 0 7 0
H
L
D
E
B
C
A
X
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3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols
can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon RESET input.
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Table 3-5. Special Function Register List (1/3)
FF00H Port register 0 P0 R/W
FF01H Port register 1 P1 R/W
FF02H Port register 2 P2 R
FF03H Port register 3 P3 R/W
FF06H Port register 6 P6 R/W
FF07H Port register 7 P7 R/W
FF08H
FF09H
FF0AH Receive buffer register 6 RXB6 R
FF0BH Transmit buffer register 6 TXB6 R/W
FF0CH Port register 12 P12 R/W
FF0DH Port register 13 P13 R/W
FF0FH Serial I/O shift register 10 SIO10 R
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H 8-bit timer counter 50 TM50 R
FF17H 8-bit timer compare register 50 CR50 R/W
FF18H 8-bit timer H compare register 00 CMP00 R/W
FF19H 8-bit timer H compare register 10 CMP10 R/W
FF1AH 8-bit timer H compare register 01 CMP01 R/W
FF1BH 8-bit timer H compare register 11 CMP11 R/W
FF1FH 8-bit timer counter 51 TM51 R
FF20H Port mode register 0 PM0 R/W
FF21H Port mode register 1 PM1 R/W
FF23H Port mode register 3 PM3 R/W
FF26H Port mode register 6 PM6 R/W
FF27H Port mode register 7 PM7 R/W
FF28H A/D converter mode register ADM R/W
FF29H Analog input channel specification register ADS R/W
FF2AH Power-fail comparison mode register PFM R/W
FF2BH Power-fail comparison threshold register PFT R/W
FF2CH Port mode register 12 PM12 R/W
FF30H Pull-up resistor option register 0 PU0 R/W
FF31H Pull-up resistor option register 1 PU1 R/W
FF33H Pull-up resistor option register 3 PU3 R/W
FF37H Pull-up resistor option register 7 PU7 R/W
A/D conversion result register ADCR R
16-bit timer counter 00 TM00 R
16-bit timer capture/compare register 000 CR000 R/W
16-bit timer capture/compare register 010 CR010 R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− − √
− √ −
− √ −
√ √ −
√ √ −
− √ −
− − √
− − √
− − √
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
After
Reset
00H
00H
Undefined
00H
00H
00H
Undefined
FFH
FFH
00H
00H
00H
0000H
0000H
0000H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
FFH
00H
00H
00H
00H
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Table 3-5. Special Function Register List (2/3)
FF3CH Pull-up resistor option register 12 PU12 R/W
FF41H 8-bit timer compare register 51 CR51 R/W
FF43H 8-bit timer mode control register 51 TMC51 R/W
FF48H External interrupt rising edge enable register EGP R/W
FF49H External interrupt falling edge enable register EGN R/W
FF4FH Input switch control register ISC R/W
FF50H
FF53H
FF55H
FF56H Clock selection register 6 CKSR6 R/W
FF57H Baud rate generator control register 6 BRGC6 R/W
FF58H Asynchronous serial interface control register 6 ASICL6 R/W
FF69H 8-bit timer H mode register 0 TMHMD0 R/W
FF6AH Timer clock selection register 50 TCL50 R/W
FF6BH 8-bit timer mode control register 50 TMC50 R/W
FF6CH 8-bit timer H mode register 1 TMHMD1 R/W
FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W
FF6EH Key return mode register KRM R/W
FF6FH Watch timer operation mode register WTM R/W
FF70H
FF71H Baud rate generator control register 0 BRGC0 R/W
FF72H Receive buffer register 0 RXB0 R
FF73H
FF74H Transmit shift register 0 TXS0 W
FF80H Serial operation mode register 10 CSIM10 R/W
FF81H Serial clock selection register 10 CSIC10 R/W
FF84H Transmit buffer register 10 SOTB10 R/W
FF8CH Timer clock selection register 51 TCL51 R/W
FF98H Watchdog timer mode register WDTM R/W
FF99H Watchdog timer enable register WDTE R/W
FFA0H Ring-OSC mode register RCM R/W
FFA1H Main clock mode register MCM R/W
FFA2H Main OSC control register MOC R/W
FFA3H Oscillation stabilization time counter status register OSTC R
FFA4H Oscillation stabilization time select register OSTS R/W
FFA9H Clock monitor mode register CLM R/W
Asynchronous serial interface operation mode
register 6
Asynchronous serial interface reception error
status register 6
Asynchronous serial interface transmission
status register 6
Asynchronous serial interface operation mode
register 0
Asynchronous serial interface reception error
status register 0
ASIM6 R/W
ASIS6 R
ASIF6 R
ASIM0 R/W
ASIS0 R
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
− √ −
− √ −
− √ −
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ −
After
Reset
00H
00H
00H
00H
00H
00H
01H
00H
00H
00H
FFH
16H
00H
00H
00H
00H
00H
00H
00H
01H
1FH
FFH
00H
FFH
00H
00H
Undefined
00H
67H
9AH
00H
00H
00H
00H
05H
00H
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Table 3-5. Special Function Register List (3/3)
After
Reset
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
CFH
00H
Note 1
FFACH Reset control flag register RESF R
FFBAH 16-bit timer mode control register 00 TMC00 R/W
FFBBH Prescaler mode register 00 PRM00 R/W
FFBCH Capture/compare control register 00 CRC00 R/W
FFBDH 16-bit timer output control register 00 TOC00 R/W
FFBEH Low-voltage detection register LVIM R/W
FFBFH Low-voltage detection level selection register LVIS R/W
FFE0H Interrupt request flag register 0L IF0 IF0L R/W
FFE1H Interrupt request flag register 0H IF0H R/W
FFE2H Interrupt request flag register 1L IF1L R/W
FFE4H Interrupt mask flag register 0L MK0 MK0L R/W
FFE5H Interrupt mask flag register 0H MK0H R/W
FFE6H Interrupt mask flag register 1L MK1L R/W
FFE8H Priority specification flag register 0L PR0 PR0L R/W
FFE9H Priority specification flag register 0H PR0H R/W
FFEAH Priority specification flag register 1L PR1L R/W
FFF0H Internal memory size switching register
FFFBH Processor clock control register PCC R/W
Note 2
IMS R/W
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
− √ −
√ √ −
√ √ −
√ √ −
√ √ −
√ √ −
− √ −
√ √ √
√ √
√ √ −
√ √ √
√ √
√ √ −
√ √ √
√ √
√ √ −
− √ −
√ √ −
00H
FFH
FFH
Notes 1. This value varies depending on the reset source.
2. The default value of IMS is fixed (IMS = CFH) in all 78K0/KC1 products regardless of the internal memory
capacity. Therefore, set the following value to each product.
Internal Memory Size Switching Register (IMS)
µ
PD780111 42H
µ
PD780112 44H
µ
PD780113 C6H
µ
PD780114 C8H
µ
PD78F0114 Value corresponding to mask ROM version
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
PC indicates the start address
...
of the instruction after the BR instruction.
α
15 0
PC
When S = 0, all bits of are 0.
When S = 1, all bits of are 1.
α
α
S
jdisp8
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
70
CALL or BR
Low Addr.
High Addr.
15 0
PC
In the case of CALLF !addr11 instruction
15 0
PC
00001
87
70
643
10–8
fa
CALLF
7–0
fa
11 10
87
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3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
765 10
Operation code
ta
4–0
15 1
111
87
65 0
Effective address
Effective address+1
01
00000000
Memory (Table)
70
Low Addr.
High Addr.
15 0
PC
87
0
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
07
rp
15 0
PC
AX
87
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/KC1 instruction words, the following instructions employ implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 and RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code 01100010
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 10000100
Register specify code
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CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 10001110 OP code
00000000 00H
11111110 FEH
[Illustration]
07
OP code
addr16 (lower)
addr16 (upper)
Memory
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3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. Refer to [Illustration].
[Operand format]
Identifier Description
saddr Immediate data that indicates label or FE20H to FF1FH
saddrp Immediate data that indicates label or FE20H to FF1FH (even address only)
[Description example]
MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)
Operation code 11110010 OP code
00110000 30H (saddr-offset)
[Illustration]
07
OP code
saddr-offset
15
Effective address
1
111111
When 8-bit immediate data is 20H to FFH,
When 8-bit immediate data is 00H to 1FH,
87
α
α
= 0
α
= 1
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0
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3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 1 1110110 OP code
0 0100000 20H (sfr-offset)
[Illustration]
07
Effective address
OP code
sfr-offset
15
111111
1
87
1
SFR
0
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3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier Description
[DE], [HL]
−
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
16 08D7
DE
The contents of the memory
addressed are transferred.
A
7 0
E
Memory
The memory address
07
specified with the
register pair DE
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3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
[HL + byte]
−
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 10101110
00010000
[Illustration]
16 08H7
HL
The contents of the memory
addressed are transferred.
7 0
A
L
Memory
07
+10
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3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the
memory spaces.
[Operand format]
Identifier Description
[HL + B], [HL + C]
−
[Description example]
In the case of MOV A, [HL + B] (selecting B register)
Operation code 10101011
[Illustration]
16 0
78
HL
The contents of the memory
addressed are transferred.
7 0
A
H
+
L
B
Memory
07
07
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE (saving DE register)
Operation code 10110101
[Illustration]
Memory 07
SP
SP
FEE0H
FEDEH
FEE0H
FEDFH
FEDEH
D
E
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4.1 Port Functions
There are two types of pin I/O buffer power supplies: AV
supplies and the pins is shown below.
Table 4-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
EVDD Port pins other than P20 to P27
78K0/KC1 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
The functions of each port are shown in Table 4-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
REF and EVDD. The relationship between these power
Port 3
Port 6
Port 7
Port 12
Port 13
P30
P33
P60
P63
P70
P73
P120
P130
P00
P01
P10
P17
P20
P27
Port 0
Port 1
Port 2
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Table 4-2. Port Functions
Pin Name I/O Function After Reset Alternate Function
P00 TI000
P01
P10 SCK10/TxD0
P11 SI10/RxD0
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
P20 to P27 Input
P30 to P32 INTP1 to INTP3
P33
P60 to P63 I/O
P70 to P73 I/O
P120 I/O
P130 Output
I/O
I/O
I/O
Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 2.
8-bit input-only port.
Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 6.
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
Port 7.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 12.
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Port 13.
1-bit output-only port.
Input
TI010/TO00
Input
TI50/TO50
Input ANI0 to ANI7
Input
INTP4/TI51/TO51
Input
Input KR0 to KR3
Input INTP0
Output
−
−
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4.2 Port Configuration
Ports include the following hardware.
Table 4-3. Port Configuration
Item Configuration
Control registers
Ports Total: 32 (CMOS I/O: 19, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistors
Port mode register (PM0, PM1, PM3, PM6, PM7, PM12)
Port register (P0 to P3, P6, P7, P12, P13)
Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12)
• Mask ROM version
Total: 23 (software control: 19, mask option specification: 4)
• Flash memory version: Total: 19
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4.2.1 Port 0
Port 0 is a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O.
RESET input sets port 0 to input mode.
Figures 4-2 and 4-3 show block diagrams of port 0.
Figure 4-2. Block Diagram of P00
EV
DD
PU
WR
PU0
PU00
Alternate
function
RD
WR
PORT
Internal bus
WR
PM
Output latch
(P00)
PM0
PM00
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
P-ch
Selector
P00/TI000
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Figure 4-3. Block Diagram of P01
EVDD
PU
WR
PU0
Internal bus
PU01
Alternate
function
RD
WRPORT
Output latch
(P01)
WRPM
PM0
PM01
Alternate
function
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
P-ch
Selector
P01/TI010/TO00
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
RESET input sets port 1 to input mode.
Figures 4-4 to 4-8 show block diagrams of port 1.
Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not
write to serial clock selection register 10 (CSIC10).
Figure 4-4. Block Diagram of P10
EV
DD
WR
PU
PU1
Internal bus
PU10
Alternate
function
RD
WR
PORT
Output latch
(P10)
WR
PM
PM1
PM10
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P10/SCK10/TxD0
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Figure 4-5. Block Diagram of P11 and P14
EV
DD
WR
PU
PU1
PU11, PU14
Alternate
function
RD
Internal bus
WR
PORT
Output latch
(P11, P14)
WR
PM
PM1
PM11, PM14
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P11/SI10/RxD0,
P14/RxD6
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Figure 4-6. Block Diagram of P12 and P15
EV
DD
PU
WR
PU1
PU12, PU15
RD
PORT
WR
Output latch
Internal bus
WR
PM
(P12, P15)
PM1
PM12, PM15
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P12/SO10,
P15/TOH0
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Figure 4-7. Block Diagram of P13
EV
DD
PU
WR
PU1
PU13
RD
PORT
WR
Internal bus
WR
PM
Output latch
(P13)
PM1
PM13
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P13/TxD6
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Figure 4-8. Block Diagram of P16 and P17
EVDD
PU
WR
PU1
Internal bus
PU16, PU17
Alternate
function
RD
WRPORT
Output latch
(P16, P17)
WRPM
PM1
PM16, PM17
Alternate
function
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
P-ch
Selector
P16/TOH1/INTP5,
P17/TI50/TO50
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4.2.3 Port 2
Port 2 is an 8-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-9 shows a block diagram of port 2.
Figure 4-9. Block Diagram of P20 to P27
RD
Internal bus
A/D converter
P20/ANI0 to P27/ANI7
RD: Read signal
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4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input.
RESET input sets port 3 to input mode.
Figures 4-10 and 4-11 show block diagrams of port 3.
Figure 4-10. Block Diagram of P30 to P32
EV
DD
PU
WR
PU3
PU30 to PU32
Alternate
function
RD
Internal bus
WR
PORT
Output latch
(P30 to P32)
WR
PM
PM3
PM30 to PM32
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
P-ch
Selector
P30/INTP1 to
P32/INTP3
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Figure 4-11. Block Diagram of P33
EV
DD
PU
WR
PU3
Internal bus
PU33
Alternate
function
RD
WR
PORT
Output latch
(P33)
WR
PM
PM3
PM33
Alternate
function
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
P-ch
Selector
P33/INTP4/TI51/TO51
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4.2.5 Port 6
Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6).
This port has the following functions for pull-up resistors. These functions differ depending on whether the product
is a mask ROM version or a flash memory version.
Table 4-4. Pull-up Resistor of Port 6
Pins P60 to P63
Mask ROM version
Flash memory version On-chip pull-up resistors are not provided
An on-chip pull-up resistor can be
specified in 1-bit units by mask option
The P60 to P63 pins are N-ch open-drain pins.
RESET input sets port 6 to input mode.
Figure 4-12 shows a block diagram of port 6.
Figure 4-12. Block Diagram of P60 to P63
RD
WR
PORT
Output latch
Internal bus
WR
PM
(P60 to P63)
PM6
PM60 to PM63
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
Selector
DD
EV
Mask option resistor
Mask ROM versions only
No pull-up resistor for
flash memory versions
P60 to P63
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4.2.6 Port 7
Port 7 is a 4-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P73 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 7 (PU7).
This port can also be used for key return input.
RESET input sets port 7 to input mode.
Figure 4-13 shows a block diagram of port 7.
Figure 4-13. Block Diagram of P70 to P73
EV
DD
PU
WR
PU7
PU70 to PU73
Alternate
function
RD
WR
PORT
Internal bus
WR
PM
Output latch
(P70 to P73)
PM7
PM70 to PM73
PU7: Pull-up resistor option register 7
PM7: Port mode register 7
RD: Read signal
WR××: Write signal
P-ch
Selector
P70/KR0 to
P73/KR3
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4.2.7 Port 12
Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
This port can also be used for external interrupt input.
RESET input sets port 12 to input mode.
Figure 4-14 shows a block diagram of port 12.
Figure 4-14. Block Diagram of P120
EV
DD
PU
WR
PU12
PU120
Alternate
function
RD
Internal bus
WR
PORT
Output latch
(P120)
WR
PM
PM12
PM120
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
P-ch
Selector
P120/INTP0
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4.2.8 Port 13
Port 13 is a 1-bit output-only port.
Figure 4-15 shows a block diagram of port 13.
Figure 4-15. Block Diagram of P130
RD
WR
PORT
Internal bus
Output latch
(P130)
P130
RD: Read signal
WR××: Write signal
Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level immediately after
reset is released, the output signal of P130 can be dummy-output as the reset signal to the CPU.
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4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
• Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12)
• Port registers (P0 to P3, P6, P7, P12, P13)
• Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12)
(1) Port mode registers (PM0, PM1, PM3, PM6, PM7, and PM12)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-5.
Figure 4-16. Format of Port Mode Register
Symbol
PM0
7
1
6
1
5
1
4
1
3
1
2
1
1
PM010PM00
Address
FF20H
After reset
FFH
R/W
R/W
PM1
PM3
PM6
PM7
PM12
7
PM17
7
1
7
1
7
1
7
1
6
PM165PM154PM143PM132PM121PM110PM10 FF21H FFH R/W
6
1
6
1
6
1
6
1
5
1
5
1
5
1
5
1
PMmn
0 Output mode (output buffer on)
1 Input mode (output buffer off)
4
1
4
1
4
1
4
1
3
PM332PM321PM310PM30 FF23H FFH R/W
3
PM632PM621PM610PM60 FF26H FFH R/W
3
PM732PM721PM710PM70 FF27H FFH R/W
3
1
2
1
Pmn pin I/O mode selection
(m = 0, 1, 3, 6, 7, 12; n = 0 to 7)
1
1
0
PM120 FF2CH FFH R/W
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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function
Alternate Function Pin Name
Function Name I/O
P00 TI000 Input 1
P01
P10
P11
P12 SO10 Output 0 0
P13 TxD6 Output 0 1
P14 RxD6 Input 1
P15 TOH0 Output 0 0
P17
P30 to P32 INTP1 to INTP3 Input 1
P33
P70 to P73 KR0 to KR3 Input 1
P120 INTP0 Input 1
TI010 Input 1
TO00 Output 0 0
SCK10
TxD0 Output 0 1
SI10 Input 1
RxD0 Input 1
TOH1 Output 0 0 P16
INTP5 Input 1
TI50 Input 1
TO50 Output 0 0
INTP4 Input 1
TI51 Input 1
TO51 Output 0 0
Input 1
Output 0 1
PM×× P××
×
×
×
×
×
×
×
×
×
×
×
×
×
Remark ×: Don’t care
PM××: Port mode register
P××: Port output latch
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(2) Port registers (P0 to P3, P6, P7, P12, and P13)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H (but P2 is undefined).
Figure 4-17. Format of Port Register
Symbol
P0
7
0
6
0
5
0
4
0
3
0
2
0
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
P1
P2
P3
P6
P7
P12
P13
7
P17
7
P27
7
0
7
0
7
0
7
0
7
0
6
P16
6
P26
6
0
6
0
6
0
6
0
6
0
5
P15
5
P25
5
0
5
0
5
0
5
0
5
0
4
P14
4
P24
4
0
4
0
4
0
4
0
4
0
3
P13
3
P23
3
P33
3
P63
3
P73
3
0
3
0
2
P12
2
P22
2
P32
2
P62
2
P72
2
0
2
0
1
P11
1
P21
1
P31
1
P61
1
P71
1
0
1
0
m = 0 to 3, 6, 7, 12, 13; n = 0 to 7
0 Output 0 Input low level
1 Output 1 Input high level
Pmn
Output data control (in output mode) Input data read (in input mode)
0
P10 FF01H 00H (output latch) R/W
0
P20 FF02H Undefined
0
P30 FF03H 00H (output latch) R/W
0
P60 FF06H 00H (output latch) R/W
0
P70 FF07H 00H (output latch) R/W
0
P120 FF0CH 00H (output latch) R/W
0
P130 FF0DH 00H (output latch) R/W
R
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CHAPTER 4 PORT FUNCTIONS
(3) Pull-up resistor option registers (PU0, PU1, PU3, PU7, and PU12)
These registers specify whether the on-chip pull-up resistors of P00, P01, P10 to P17, P30 to P33, P70 to P73, or
P120 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode
of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, and PU12.
On-chip pull-up resistors cannot be connected for bits set to output mode and bits used as alternate-function
output pins, regardless of the settings of PU0, PU1, PU3, PU7, and PU12.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Caution Use of a pull-up resistor can be specified for P60 to P63 pins by a mask option only in the mask
ROM versions.
Figure 4-18. Format of Pull-up Resistor Option Register
Symbol
PU0
7
0
6
0
5
0
4
0
3
0
2
0
1
PU010PU00
Address
FF30H
After reset
00H
R/W
R/W
PU1
PU3
PU7
PU12
7
PU17
7
0
7
0
7
0
6
PU165PU154PU143PU132PU121PU110PU10 FF31H 00H R/W
6
0
6
0
6
0
5
0
5
0
5
0
4
0
4
0
4
0
PUmn
0 On-chip pull-up resistor not connected
1 On-chip pull-up resistor connected
3
PU332PU321PU310PU30 FF33H 00H R/W
3
PU732PU721PU710PU70 FF37H 00H R/W
3
0
Pmn pin on-chip pull-up resistor selection
2
0
(m = 0, 1, 3, 7, 12; n = 0 to 7)
1
0
0
PU120 FF3CH 00H R/W
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CHAPTER 4 PORT FUNCTIONS
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins,
the output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the
pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared by reset.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three system clock oscillators are available.
• X1 oscillator
The X1 oscillator oscillates a clock of f
XP = 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the main OSC control register (MOC) and processor clock control register (PCC).
• Ring-OSC oscillator
The Ring-OSC oscillator oscillates a clock of f
R = 240 kHz (TYP.). Oscillation can be stopped by setting the
Ring-OSC mode register (RCM) when “Can be stopped by software” is set by a mask option and the X1 input
clock is used as the CPU clock.
• Subsystem clock oscillator
The subsystem clock oscillator oscillates a clock of f
XT = 32.768 kHz. Oscillation cannot be stopped. When
subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the
processor clock control register (PCC), and the operating current can be reduced in the STOP mode.
Remarks 1. f
2. f
3. f
XP: X1 input clock oscillation frequency
R: Ring-OSC clock oscillation frequency
XT: Subsystem clock oscillation frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillators X1 oscillator
Ring-OSC oscillator
Subsystem clock oscillator
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CHAPTER 5 CLOCK GENERATOR
Figure 5-1. Block Diagram of Clock Generator
Internal bus
Oscillation
stabilization time
select register
(OSTS)
OSTS1 OSTS0OSTS2
3
X1 oscillation
MOST
MOST
MOST
14
13
15
Oscillation
stabilization
MOST
time counter
16
status
register
(OSTC)
Processor clock
control register
(PCC)
CSS PCC2CLS
PCC1 PCC0
4
Controller
Control signal
C
P
U
CPU clock
CPU
)
(f
STOP
MSTOP
Main OSC
control
register
(MOC)
MCSCLSMCC
Main clock
mode register
(MCM)
MCM0
stabilization time counter
MOST
11
X1
X2
Mask option
1: Cannot be stopped
0: Can be stopped
X1 oscillator
Ring-OSC
oscillator
Ring-OSC mode
register (RCM)
RSTOP
f
XP
Operation
clock switch
f
R
Internal bus
Prescaler
f
X
8-bit timer H1,
watchdog timer
f
X
2
Prescaler
f
X
f
2
2
2
X
f
X
3
4
2
Prescaler
Clock to peripheral
hardware
Selector
f
1/2
CPU
Subsystem
clock oscillator
f
XT
Watch clock
XT1
XT2
FRC
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CHAPTER 5 CLOCK GENERATOR
5.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator.
• Processor clock control register (PCC)
• Ring-OSC mode register (RCM)
• Main clock mode register (MCM)
• Main OSC control register (MOC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC)
The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop
and whether to use the on-chip feedback resistor
PCC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PCC to 00H.
Note The feedback resistor is required to control the bias point of the oscillation waveform so that the bias point
is in the middle of the power supply voltage.
When the subsystem clock is not used, the operating current in the STOP mode can be reduced by setting
bit 6 (FRC) of PCC to 1 (see Figure 5-11 Subsystem Clock Feedback Resistor).
Note
of the subsystem clock oscillator.
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CHAPTER 5 CLOCK GENERATOR
Address: FFFBH After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
PCC MCC FRC CLS CSS 0 PCC2 PCC1 PCC0
Note 1
Figure 5-2. Format of Processor Clock Control Register (PCC)
MCC Control of X1 oscillator operation
0 Oscillation possible
1 Oscillation stopped
Note 2
FRC Subsystem clock feedback resistor selection
0 On-chip feedback resistor used
1 On-chip feedback resistor not used
Note 3
CLS CPU clock status
0 X1 input clock or Ring-OSC clock
1 Subsystem clock
Note 4
CPU clock (fCPU) selection
0 0 0 fX fR fXP
0 0 1 fX/2 fR/2 fXP/2
0 1 0 fX/22 fR/22 fXP/22
0 1 1 fX/23 fR/23 fXP/23
0 0 0
0 0 1
0 1 0
0 1 1
Other than above Setting prohibited
CSS
PCC2 PCC1 PCC0
0
1 0 0 fX/24 fR/24 fXP/24
1
1 0 0
MCM0 = 0 MCM0 = 1
XT/2
f
Notes 1. Bit 5 is read-only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC
control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
3. This bit can be set to 1 only when the subsystem clock is not used.
4. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Caution Be sure to clear bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. f
X: Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC
clock oscillation frequency)
3. f
4. f
R: Ring-OSC clock oscillation frequency
XP: X1 input clock oscillation frequency
5. fXT: Subsystem clock oscillation frequency
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