NCE RFORM P4C1256-25CM, P4C1256-20PI, P4C1256-25CMB, P4C1256-25DM, P4C1256-25DWM Datasheet
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117
P4C1256
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
— 880 mW Active (Commercial)
Single 5V±10% Power Supply
Easy Memory Expansion Using
CECE
CECE
CE and
OEOE
OEOE
OE
Inputs
Common Data I/O
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
1519B
1Q97
Means Quality, Service and Speed
INPUT
DATA
CONTROL
262,144-BIT
MEMORY
ARRAY
COLUMN I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
OE
CE
• • •
• • •
• • •
ROW SELECT
A
A
• • •
A
• • •
A
(7)
(8)
• • •
• • •
• • •
• • •
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—28-Pin 300 mil DIP and SOJ
—28-Pin 600 mil Ceramic DIP
—28-Pin LCC(350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
FEATURES
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of P ACE RAM™ products offering fast access times.
The P4C1256 device provides asynchronous operation with
matching access and cycle times. Memory locations are
specified on address pins A0 to A14. Reading is accomplished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Package options for the P4C1256 include 28-pin 300 mil
DIP and SOJ packages. For military temperature range,
Ceramic DIP and LCC packages are available.
DIP (P5, C5, D5-1), SOJ (J5)
TOP VIEW
32 LCC (L6)
TOP VIEW
See Selection Guide page for 28-pin LCC
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CE
WE
A
11
OE
I/0
2
I/0
3
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/0
1
A14
A13
A12
VCC
A
2
A
3
NC
CE
A
12
A
11
NC
GND
V
CC
29
28
27
26
25
24
23
5
6
7
8
9
10
11
12
13
22
21
14 18
3
1
162153217
I/O
1
A
10
OE
I/O
8
I/O
7
WE
I/O
3
NC
I/O4
I/O
5
4
31 30
19 20
A
4
A
5
A
6
A
7
A
8
A
9
I/O
2
I/O
6
A
13
A1A
0
A
14
NC
118
P4C1256
P4C1256
MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
V
CC
Power Supply Pin with –0.5 to +7 V
Respect to GND
Terminal Voltage with –0.5 to
V
TERM
Respect to GND VCC +0.5 V
(up to 7.0V)
T
A
Operating Temperature –55 to +125 °C
Symbol Parameter Value Unit
T
BIAS
Temperature Under –55 to +125 °C
Bias
T
STG
Storage Temperature –65 to +150 °C
P
T
Power Dissipation 1.0 W
I
OUT
DC Output Current 50 mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE ≥ VIH or Mil.
CE2 ≤VIL, VCC= Max Ind./Com’l.
f = Max., Outputs Open
___
___
45
30
20
10
___
___
CE ≥ VHC or Mil.
CE2 ≤VLC, VCC= Max Ind./Com’l.
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ V
HC
Standby Power Supply
Current
(CMOS Input Levels)
I
SB1
Industrial
Grade(2)
Ambient
Temperature
GND
V
CC
0V
0V
5.0V ± 10%
5.0V ± 10%
0V
5.0V ± 10%
–55°C to +125°C
Military
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
V
OUT
= 0V
8
10
Unit
pF
pF
CAPACITANCES
(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
IH
V
IL
V
HC
V
LC
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Leakage Current
Test Conditions
VCC = Max. Mil.
VIN = GND to VCC Ind./Com’l.
VCC = Max., CE = VIH, Mil.
V
OUT
= GND to VCC Ind./Com’l.
Min
2.2
–0.5
(3)
VCC –0.2
–0.5
(3)
–10
–5
–10
–5
Max
VCC +0.5
0.8
VCC +0.5
0.2
+10
+5
+10
+5
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Commercial
–40°C to +85°C
0°C to +70°C
Unit
V
V
V
V
µA
µA
mA
mA
V
OL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
0.4
V
Output High Voltage
(TTL Load)
V
OH
IOH = –4 mA, VCC = Min. 2.4 V
Output Leakage Current
119
P4C1256
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
I
CC
Symbol Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Industrial
Military
N/A
N/A
–15
N/A
–12
–20 –25 –35 –45 –55 –70
Unit
N/AmAmA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
N/A
N/AN/A
170 160
170
155
165
170
150 145
160 155 150
150150155160165
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
Output Enable
Low to Data
Valid
Min Max Min MaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax
-20 -25 -35 -45 -55 -70-12 -15
Unit
12
2
0
0
12
12
2
5
5
5
12
15
2
2
0
0
15
15
8
7
7
15
20
2
2
0
0
20
20
9
9
9
20
25
3
3
0
0
25
25
11
10
11
20
35
3
3
0
0
35
35
15
15
15
20
45
3
3
0
0
45
45
20
20
20
25
55
3
3
0
0
55
55
25
25
25
30
70
3
3
0
0
70
70
30
30
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
P4C1256
Notes:
1. WE is HIGH for READ cycle.
2. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with CE
1
transition
LOW .
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
READ CYCLE NO. 1 (
OEOE
OEOE
OE CONTROLLED)
(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CECE
CECE
CE CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALIDPREVIOUS DATA VALID
(5)
RC
OLZ
ADDRESS
OE
t
RC
DATA OUT
(5)
t
OH
CE
t
t
AC
t
OHZ
t
HZ
(4)
(4)
(4)
(4)
t
OE
t
AA
t
AC
t
AC
CE
DATA OUT
t
RC
t
LZ
(8)
DATA VAL ID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
VCC SUPPLY
CURRENT
121
P4C1256
Notes:
6. CE1 and WE must be LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show tWZ and tOW.
8. If CE1 goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
-35
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)
(2)
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Sym.
t
WC
t
CW
t
AS
t
WP
t
AH
t
DW
t
DH
Parameter
Write Cycle Time
Chip Enable
Time to End of
Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Date Hold Time
Data Valid to
End of Write
Min Max Min MaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMax
-20 -25 -45 -55 -70-12 -15
Unit
12
0
0
9
0
8
15
11
0
20
15
0
25
0
18
0
35
0
22
0
45
0
25
0
55
0
30
0
70
0
35
0
9
10
0
9
15
0
11
18
20
0
13
22
25
0
15
30
35
0
20
35
40
0
25
40
45
0
30
ns
ns
ns
ns
ns
ns
ns
ns
t
AW
Address Valid to
End of Write
9
10 15
00
Write Enable to
Output in High Z
t
WZ
7 8 10 11 15 18 25 30 ns
Output Active
from End of Write
t
OW
33335500ns
WRITE CYCLE NO. 1 (
WEWE
WEWE
WE CONTROLLED)
(6)
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT DATA UNDEFINED
(9)
(4)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
t
WZ
(4,7)
(7)
122
P4C1256
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns
Input Timing Reference Level 1.5V
Output Timing Reference Level 1.5V
Output Load See Figures 1 and 2
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CECE
CECE
CE CONTROLLED)
(6)
Mode
CECE
CECE
CE
1
CE
2
OEOE
OEOE
OE
WEWE
WEWE
WE I/O Power
Standby H X X X High Z Standby
Standby X L X X High Z Standby
D
OUT
Disabled L H H H High Z Active
Read L H L H D
OUT
Active
Write L H X L High Z Active
AC TEST CONDITIONS TRUTH TABLE
Figure 1. Output Load Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1256, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
OLZ
D
OUT
255Ω
480Ω
+5V
30pF* (5pF* for t
HZ
, t
LZ
t
WZ OW
and t
,
)
t
OHZ
t
,
,
30pF* (5pF* for tHZ, t
LZ
t
WZ OW
and t
,
)
D
OUT
166.5 Ω
VTH= 1.73 V
=R
TH
, t
OHZ
,
t
OLZ
,
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with D
OUT
to match 166Ω (Thevenin Resistance).
t
DW
WE
ADDRESS
CE
DATA OUT
(6)
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(9)
t
AS
t
CW
t
AW
t
WP
t
DH
t
AH
123
P4C1256
PACKAGE SUFFIX
Package
Suffix
P Plastic DIP, 300 mil wide standard
J Plastic SOJ, 300 mil wide standard
C Sidebrazed DIP, 300 mil wide
D CERDIP, 300 mil wide
DW CERDIP, 600 mil wide
L28 Leadless Chip Carrier, 350 x 550 mils
L32 Leadless Chip Carrier, 450 x 550 mils
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
C Commercial Temperature Range,
0°C to +70°C.
I Industrial Temperature Range,
–40˚C to +85˚C.
M Military Temperature Range,
–55°C to +125°C.
MB Mil. Temp. with MIL-STD-883
Class B compliance.
Description Description
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
The P4C1256 is also available per SMD 5962-88662
1256
P4C
ss p t
Temperature Range
Package Code
Static RAM Prefix
Speed (Access/Cycle Time)
Device Number
I = Ultra-low standby power designator L, if available.
ss = Speed (access/cycle time in n s). e.g. 25, 35.
p = Package code, i.e., P, J, C, D, DW, L28, L32.
t = Temperature range, i.e., C, M. MB.
124
P4C1256
28 LCC PIN CONFIGURATION
SELECTION GUIDE
The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available only
over the military temperature range.
SpeedTemp.
Range
Com'l
Ind.
Package
Plastic DIP
Plastic SOJ
Plastic DIP
Plastic SOJ
Sidebrazed (300 mil)
CERDIP (300 mil)
CERDIP (600 mil)
L28
L32
N/A
N/A
N/A
N/A
-70CM
-70DM
-70DWM
-70L28M
-70L32M
70
Mil.
Temp.
12
-12PC
-12JC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
15
-15PC
-15JC
-15PI
-15JI
N/A
N/A
N/A
N/A
N/A
20
-20PI
-20JI
-20CM
-20DM
-20DWM
-20L28M
-20L32M
25
-25PC
-25JC
-25CM
-25DM
-25DWM
-25L28M
-25L32M
35
-35PC
-35JC
-35PI
-35JI
-35CM
-35DM
-35DWM
-35L28M
-35L32M
45 55
N/A
N/A
N/A
N/A
-45PI
-425JI
N/A
N/A
-45CM
-45DM
-45DWM
-45L28M
-45L32M
-55CM
-55DM
-55DWM
-55L28M
-55L32M
-20PC
-20JC
-25PI
-25JI
Military
Proc'd*
-20CMB
-20DMB
-20DWMB
-20L28MB
-20L32MB
-35CMB
-35DMB
-35DWMB
-35L28MB
-35L32MB
-45CMB
-45DMB
-45DWMB
-45L28MB
-45L32MB
-55CMB
-55DMB
-55DWMB
-55L28MB
-55L32MB
-70CMB
-70DMB
-70DWMB
-70L28MB
-70L32MB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Sidebrazed (300 mil)
CERDIP (300 mil)
CERDIP (600 mil)
L28
L32
-25CMB
-25DMB
-25DWMB
-25L28MB
-25L32MB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A
2
A
5
A
6
A
7
A
8
A
9
I/O
1
CE
A
13
A
12
A
11
GND
A
0
A
1
V
CC
26
25
24
23
22
21
20
4
5
6
7
8
9
10
11
12
19
18
13 17
327
1
15
21428
16
I/O
2
A
10
OE
I/O
8
I/O
7
WE
I/O3I/O4I/O5I/O
6
A
4
A
3
A
14
28 LCC (L5)
TOP VIEW
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