NCE RFORM P4C1024L-55PI, P4C1024L-70PC, P4C1024L-70SI, P4C1024L-70SC, P4C1024L-55PC Datasheet
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151
P4C1024L
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
Means Quality, Service and Speed
locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or OE is HIGH or WE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin 445 mil SOP
as well as a 600 mil PDIP.
The P4C1024L is a 1,048,576-bit low power CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS
is utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous operation with matching access and cycle times. Memory
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil DIP
—32-Pin 445 mil SOP
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE
1, CE2
and
OE Inputs
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
CE
1
• • •
• • •
• • •
ROW SELECT
A
A
• • •
A
• • •
A
(8)
(9)
• • •
• • •
• • •
• • •
CE
2
OE
CONTROL
CIRCUIT
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
WE
A
11
OE
I/O
7
I/O
6
I/O
5
NC
A
13
V
CC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
15
16 17
18
I/O
3
I/O
4
CE
1
A
9
A
8
CE
2
A
15
DIP (P600), SOP (S12)
TOP VIEW
152
P4C1024L
GND ≤ VIN ≤ V
CC
Ind'l.
Com'l.
I
LO
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only . Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Temperature Range (Ambient) Supply Voltage
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C) 4.5 ≤ VCC ≤ 5.5V
Commercial (0°C to 70°C)
Symbol Parameter Min Max Unit
V
CC
Supply Voltage with Respect to GND -0.5 7.0 V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5 V
T
A
Operating Ambient Temperature -55 125 °C
S
TG
-65 150 °C
I
OUT
Output Current into Low Outputs 25 mA
I
LAT
Latch-up Current
>200
mA
Storage Temperature
Symbol
Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
SB
I
SB1
Output High Voltage
(I/O0 - I/O7)
Output Low Voltage
(I/O0 - I/O7)
Input High Voltage
Input Low Voltage
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC Current
TTL Standby Current
(TTL Input Levels)
Output Leakage Current
Input Leakage Current
IOH = –1mA, VCC = 4.5V
IOL = 2.1mA
VCC = 5.5V, I
OUT
= 0 mA
CE
1
≥ V
CC
-0.2V, CE2 ≤ 0.2V
VCC = 5.5V, I
OUT
= 0 mA
CE
1
= VIH or CE2 = V
IL
GND ≤ V
OUT
≤ V
CC
Ind'l.
CE
1
≥ VIH or CE2 ≤ V
IL
Com'l.
Test Conditions
Min
Max Unit
2.4
2.2
-0.5
-5
-2
-5
-2
V
V
V
V
µA
µA
mA
µA
0.4
VCC + 0.3
0.8
+5
+2
+5
+2
3
100
153
P4C1024L
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and VIL/ VIH = 0V/ VCC.
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
POWER DISSIPATION CHARACTERISTICS VS. SPEED
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
Test Conditions Max
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
VIN = 0V
V
OUT
= 0V
7
9
pF
pF
Symbol Parameter
-55 -70
Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
70
85
70
85
15
25
15
25
mA
mA
-55 -70
Temperature
Range
Symbol
Parameter
-55
Min
Max
-70
Min
Max
Unit
t
RC
55
ns
t
AA
Address Access Time
55 70 ns
t
AC
Chip Enable Access
Time
55 70
ns
t
OH
Output Hold from
Address Change
55
ns
t
LZ
Chip Enable to
Output in Low Z
10 10
ns
t
HZ
Chip Disable to
Output in High Z
20
25
ns
t
OE
Output Enable Low
to Data Valid
30
35
ns
t
OLZ
Output Enable Low
to Low Z
55
ns
t
OHZ
Output Enable High
to High Z
20
25
ns
t
PU
Chip Enable to
Power Up Time
00
ns
t
PD
Chip Disable to
Power Down Time
55
70 ns
Read Cycle Time
70
*
**
154
P4C1024L
Notes:
1. WE is HIGH for READ cycle.
2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transition LOW or CE2 transition HIGH.
READ CYCLE NO. 1 (
OEOE
OEOE
OE CONTROLLED)
(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CECE
CECE
CE
CONTROLLED)
ADDRESS
OE
t
RC
(5)
DATA OUT
t
OH
CE
t
OLZ
t
AC
t
LZ
t
OHZ
t
HZ
CE
2
t
AA
t
OE
4. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
t
AC
CE
1
DATA O UT
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
CURRENT
V
CC
SUPPLY
CE
2
t
AA
ADDRESS
DATA OUT
t
RC
t
OH
DATA VALID
PREVIOUS DATA VALID
(5)
155
P4C1024L
-55
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
WRITE CYCLE NO. 1 (
WEWE
WEWE
WE CONTROLLED)
(6)
Symbol Parameter
Max
-70
Max
Unit
Min Min
t
WC
t
CW
t
AS
t
WP
t
AH
t
DH
t
WZ
t
OW
Write Cycle Time 55 70 ns
Chip Enable Time
to End of Write
50 60 ns
Address Valid to
End of Write
50 60 ns
Address Set-up
Time
00ns
Write Pulse Width 40 50 ns
Address Hold
Time
00ns
Data Valid to End
of Write
25 30 ns
Data Hold Time 0 0 ns
Write Enable to
Output in High Z
25 30 ns
Output Active from
End of Write
55ns
t
AW
t
DW
ADDRESS
CE
1
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT DATA UNDEFINED
(9)
(4)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
t
WZ
(4,7)
(7)
CE
2
156
P4C1024L
Write
Active
Read
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CECE
CECE
CE CONTROLLED)
(6)
* including scope and test fixture.
Note:
Because of the high speed of the P4C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.77V (Thevenin Voltage) at the comparator input, and a
589Ω resistor must be used in series with D
OUT
to match 639Ω
(Thevenin Resistance).
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
Mode
Standby
Standby
D
OUT
Disabled
Standby
Power
I/OI/O
I/OI/O
I/O
WEWE
WEWE
WE
OEOE
OEOE
OECE
2
CECE
CECE
CE
1
High Z
High Z
D
OUT
High Z
X
X
H
H
L
X
X
H
L
X
X
L
H
H
H
H
X
L
L
L
Standby
Active
Active
High Z
Figure 2. Thevenin Equivalent
30pF* (5pF* for tHZ, t
LZ
t
WZ OW
and t
,
)
D
OUT
638.7 Ω
VTH= 1.77 V
=R
TH
, t
OHZ
,
t
OLZ
,
OLZ
D
OUT
990 Ω
1800 Ω
+5V
30pF* (5pF* for t
HZ
, t
LZ
t
WZ OW
and t
,
)
t
OHZ
t
,
,
Figure 1. Output Load
t
DW
WE
ADDRESS
CE
1
DATA OUT
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(9)
t
AS
t
CW
t
AW
t
WP
t
DH
t
AH
(12)
CE
2
157
P4C1024L
DATA RETENTION
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 ≤ 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
LOW VCC DATA RETENTION WAVEFORM 1 (
CECE
CECE
CE
1
CONTROLLED)
Symbol
Parameter
Test Conditions Unit
Max
Min
V
DR
I
CCDR
(1)
VCC for Data Retention
Data Retention Current
CE
1
≥ VCC -0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
2.0 5.5 V
VDR = 2.0V
VDR = 3.0V
30 µA
50
µA
t
R
Operating Recovery Time
Chip Deselect to Data
Retention Time
See Retention Waveform
5
0
ms
ns
t
CDR
CE
1
4.5V
t
CDR
Data Retention Mode
V
DR
CE1≥ VDR -0.2V
2.2V
V
CC
4.5V
t
R
2.2V
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
CE
2
4.5V
t
CDR
Data Retention Mode
V
DR
CE2 ≤ 0.2V
2.2V
V
CC
4.5V
t
R
V
IL
V
IL
158
P4C1024L
Package
Suffix
P
Plastic DIP, 600 mil wide standard
Description
S
SOP, 445 mil wide standard
PACKAGE SUFFIX
TEMPERATURE RANGE SUFFIX
Temperature
Range Suffix
Description
C
I
Commercial Temperature Range,
0˚C to +70˚C
Industrial Temperature Range,
-40˚C to +85˚C
SELECTION GUIDE
The P4C1024L is available in the following temperature, speed and package options.
Temperature
Range
Package
Speed (ns)
-55
-70
Commercial
Temperature
Plastic DIP 600 -55PC -70PC
Plastic SOP 445 -55SC -70SC
Industrial
Temperature
Plastic DIP 600
-55PI
-70PI
-55SI
-70SI
Plastic SOP 445
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
P4C 1024L
ss p t
Temperature Range: C, I
Package Code: P, S
Speed (Access/Cycle Time): 55, 70
Device Number: 1024L
Static RAM Prefix
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