National Semiconductor MM54C48, MM74C48 Technical data
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MM54C48/MM74C48
BCD-to-7 Segment Decoder
MM54C48/MM74C48 BCD-to-7 Segment Decoder
March 1988
General Description
The MM54C48/MM74C48 BCD-to-7 segment decoder is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with N- and P-channel enhancement transistors. Seven NAND gates and one driver are connected in
pairs to make binary-coded decimal (BCD) data and its complement available to the seven decoding AND-OR-INVERT
gates. The remaining NAND gate and three input buffers
provide test-blanking input/ripple-blanking output, and ripple-blanking inputs.
Connection Diagram
Dual-In-Line Package
Features
Y
Wide supply voltage range 3.0V to 15V
Y
Guaranteed noise margin 1.0V
Y
High noise immunity 0.45 VCC(typ.)
Y
Low power fan out of 2
TTL compatibility driving 74L
Y
High current sourcing output (up to 50 mA)
Y
Ripple blanking for leading or trailing zeros (optional)
Y
Lamp test provision
Top View
Order Number MM54C48 or MM74C48
Segment Identification
TL/F/5883– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5883
Numerical Designations
and Resultant Displays
TL/F/5883– 1
TL/F/5883– 3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
MM54C48
MM74C48
Storage Temperature Range
b
0.3V to V
b
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
65§Ctoa150§C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
Absolute Maximum V
Range 3.0V to 15V
CC
CC
Lead Temperature (Soldering, 10 seconds) 260
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS to CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
(RB Output Only)
Logical ‘‘0’’ Output Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
(RB Output Only)
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)
I
SOURCE
I
SINK
I
SINK
I
SOURCE
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
AN-90.
Output Source Current V
(P-Channel)(RB Output Only)
Output Sink Current V
(N-Channel) T
Output Sink Current V
(N-Channel) T
Output Source Current V
(NPN Bipolar)
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note,
PD
e
5.0V 3.5 V
CC
e
V
10V 8.0 V
CC
e
5.0V 1.5 V
CC
e
V
10V 2.0 V
CC
CC
V
CC
CC
V
CC
CC
CC
CC
74C, V
74C, V
74C, V
74C, V
CC
V
CC
CC
e
A
CC
e
A
CC
V
CC
V
CC
V
CC
e
e
e
e
e
e
e
e
e
e
25§C
e
25§C
e
e
e
e
eb
5.0V, I
10V, I
5.0V, I
10V, I
15.0V, V
15.0V, V
10 mA 4.5 V
O
eb
10 mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
e
15V 0.005 1.0 mA
IN
e
0V
IN
b
1.0
b
0.005 mA
15V 0.05 300 mA
e
4.5V V
CC
e
4.75V V
CC
e
4.5V 0.8 V
CC
e
4.75V 0.8 V
CC
e
CC
e
CC
e
CC
e
CC
4.75V, V
10V, V
5.0V, V
10V, V
5.0V, V
5.0V, V
10V, V
10V, V
4.5V, I
4.75V, I
4.5V, I
4.75V, I
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
eb
50 mA 2.4 V
O
eb
50 mA 2.4 V
O
e
360 mA 0.4 V
O
e
360 mA 0.4 V
O
e
0.4V
e
0.5V
e
V
CC
e
V
CC
e
3.4V
e
3.0V
e
8.4V
e
8.0V
b
1.5 V
CC
b
1.5 V
CC
1.75 3.6 mA
8.0 16 mA
b
20
b
20
b
50 mA
b
65 mA
b
50 mA
b
65 mA
b
0.80 mA
b
4.0 mA
18V
C
§
2
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