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MM54C240/MM74C240 Inverting
MM54C244/MM74C244 Non-Inverting
Octal Buffers and Line Drivers with TRI-STATE
February 1988
Outputs
É
MM54C240/MM74C240 Inverting, MM54C244/MM74C244 Non-Inverting
Octal Buffers and Line Drivers with TRI-STATE Outputs
General Description
These octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with TRI-STATE
outputs. These outputs have been specially designed to
drive highly capacitive loads such as bus-oriented systems.
These devices have a fan out of 6 low power Schottky
loads. A high logic level on the output disable control input
G makes the outputs go into the high impedance state. For
improved TTL input compatibility see MM74C941.
Logic and Connection Diagrams
MM54C240/MM74C240
TL/F/5905– 1
Features
Y
Wide supply voltage range (3V to 15V)
Y
High noise immunity (0.45 VCCtyp)
Y
Low power consumption
Y
High capacitive load drive capability
Y
TRI-STATE outputs
Y
Input protection
Y
TTL compatibility
Y
20-pin dual-in-line package
Y
High speed 25 ns (typ.)@10V, 50 pF (MM74C244)
MM54C240/MM74C240 Dual-In-Line Package
Top View
Order Number MM54C240 or MM74C240
TL/F/5905– 2
MM54C244/MM74C244
TL/F/5905– 3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5905
MM54C244/MM74C244 Dual-In-Line Package
TL/F/5905– 4
Top View
Order Number MM54C244 or MM74C244
Absolute Maximum Ratings (Note 1)
b
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
MM54C240, MM54C244
MM74C240, MM74C244
b
0.3V to V
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
Absolute Maximum V
Range 3V to 15V
CC
CC
Lead Temperature (Soldering, 10 seconds) 260§C
65§Ctoa150§C
DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
OZ
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not
meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Output Source Current V
(P-Channel) T
Output Sink Current V
(N-Channel) T
e
5V 3.5 V
CC
e
V
10V 8.0 V
CC
e
5V 1.5 V
CC
e
V
10V 2.0 V
CC
e
eb
5V, I
CC
e
V
10V, I
CC
e
5V, I
CC
e
V
10V, I
CC
e
10V, ODeV
CC
e
15V, V
CC
e
15V, V
CC
e
15V 0.05 300 mA
CC
CC
74C, V
CC
CC
74C, V
CC
CC
74C, V
CC
54C, V
CC
74C, V
CC
CC
74C, V
CC
e
5V, V
CC
e
25§C
A
e
V
10V, V
CC
e
25§C
T
A
e
5V, V
CC
e
25§C
A
e
V
10V, V
CC
e
25§C
T
A
10 mA 4.5 V
O
eb
10 mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
IH
e
15V 0.005 1.0 mA
IN
e
0V
IN
e
4.5V V
e
4.75V V
e
4.5V 0.8 V
e
4.75V 0.8 V
e
e
e
e
e
e
4.5V, I
4.75V, I
4.5V, I
4.75V, I
4.5V, I
4.75V, I
e
OUT
OUT
e
OUT
OUT
eb
450 mAV
O
eb
450 mAV
O
eb
2.2 mA 2.4 V
O
eb
2.2 mA 2.4 V
O
e
2.2 mA 0.4 V
O
e
2.2 mA 0.4 V
O
0V
e
0V
V
CC
e
V
CC
CC
CC
CC
CC
b
1.0
b
b
b
b
b
14
b
36
b
0.005 mA
1.5 V
1.5 V
0.4 V
0.4 V
b
30 mA
b
70 mA
12 20 mA
48 70 mA
g
10 mA
18V
2