National Semiconductor MM54C240, MM74C240 Technical data

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MM54C240/MM74C240 Inverting MM54C244/MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE
February 1988
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MM54C240/MM74C240 Inverting, MM54C244/MM74C244 Non-Inverting
Octal Buffers and Line Drivers with TRI-STATE Outputs
General Description
These octal buffers and line drivers are monolithic comple­mentary MOS (CMOS) integrated circuits with TRI-STATE outputs. These outputs have been specially designed to drive highly capacitive loads such as bus-oriented systems. These devices have a fan out of 6 low power Schottky loads. A high logic level on the output disable control input G makes the outputs go into the high impedance state. For improved TTL input compatibility see MM74C941.
Logic and Connection Diagrams
MM54C240/MM74C240
TL/F/5905– 1
Features
Y
Wide supply voltage range (3V to 15V)
Y
High noise immunity (0.45 VCCtyp)
Y
Low power consumption
Y
High capacitive load drive capability
Y
TRI-STATE outputs
Y
Input protection
Y
TTL compatibility
Y
20-pin dual-in-line package
Y
High speed 25 ns (typ.)@10V, 50 pF (MM74C244)
MM54C240/MM74C240 Dual-In-Line Package
Top View
Order Number MM54C240 or MM74C240
TL/F/5905– 2
MM54C244/MM74C244
TL/F/5905– 3
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5905
MM54C244/MM74C244 Dual-In-Line Package
TL/F/5905– 4
Top View
Order Number MM54C244 or MM74C244
Absolute Maximum Ratings (Note 1)
b
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
MM54C240, MM54C244 MM74C240, MM74C244
b
0.3V to V
b
b
a
0.3V
CC
55§Ctoa125§C
40§Ctoa85§C
Storage Temperature Range
Power Dissipation
Dual-In-Line 700 mW Small Outline 500 mW
Operating V
Absolute Maximum V
Range 3V to 15V
CC
CC
Lead Temperature (Soldering, 10 seconds) 260§C
65§Ctoa150§C
DC Electrical Characteristics Min/Max limits apply across temperature range, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
OZ
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Supply Current V
CMOS/LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage 54C, V
Logical ‘‘0’’ Input Voltage 54C, V
Logical ‘‘1’’ Output Voltage 54C, V
Logical ‘‘0’’ Output Voltage 54C, V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SINK
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Output Source Current V (P-Channel) T
Output Sink Current V (N-Channel) T
e
5V 3.5 V
CC
e
V
10V 8.0 V
CC
e
5V 1.5 V
CC
e
V
10V 2.0 V
CC
e
eb
5V, I
CC
e
V
10V, I
CC
e
5V, I
CC
e
V
10V, I
CC
e
10V, ODeV
CC
e
15V, V
CC
e
15V, V
CC
e
15V 0.05 300 mA
CC
CC
74C, V
CC
CC
74C, V
CC
CC
74C, V
CC
54C, V
CC
74C, V
CC
CC
74C, V
CC
e
5V, V
CC
e
25§C
A
e
V
10V, V
CC
e
25§C
T
A
e
5V, V
CC
e
25§C
A
e
V
10V, V
CC
e
25§C
T
A
10 mA 4.5 V
O
eb
10 mA 9.0 V
O
e
10 mA 0.5 V
O
e
10 mA 1.0 V
O
IH
e
15V 0.005 1.0 mA
IN
e
0V
IN
e
4.5V V
e
4.75V V
e
4.5V 0.8 V
e
4.75V 0.8 V
e e
e e
e e
4.5V, I
4.75V, I
4.5V, I
4.75V, I
4.5V, I
4.75V, I
e
OUT
OUT
e
OUT
OUT
eb
450 mAV
O
eb
450 mAV
O
eb
2.2 mA 2.4 V
O
eb
2.2 mA 2.4 V
O
e
2.2 mA 0.4 V
O
e
2.2 mA 0.4 V
O
0V
e
0V
V
CC
e
V
CC
CC
CC
CC
CC
b
1.0
b b
b b
b
14
b
36
b
0.005 mA
1.5 V
1.5 V
0.4 V
0.4 V
b
30 mA
b
70 mA
12 20 mA
48 70 mA
g
10 mA
18V
2
AC Electrical Characteristics* T
e
A
25§C, C
e
50 pF, unless otherwise specified
L
Symbol Parameter Conditions Min Typ Max Units
t
PD(1),tPD(0)
t1H,t
0H
tH1,t
H0
t
T(HL),tT(LH)
C
PD
Propagation Delay (Data In to Out)
MM54C240/MM74C240 V
MM54C244/MM74C244 V
Propagation Delay Output R Disable to High Impedance V State (from a Logic Level) V
Propagation Delay Output R Disable to Logic Level V (from High Impedance State) V
Transition Time V
e
CC
e
V
CC
e
V
CC
e
V
CC
e
CC
e
V
CC
e
V
CC
e
V
CC
e
L
e
CC
e
CC
e
L
e
CC
e
CC
e
CC
e
V
CC
e
V
CC
e
V
CC
Power Dissipation (Note 3) Capacitance
e
5V, C 10V, C 5V, C 10V, C
5V, C 10V, C 5V, C 10V, C
1k, C
5V 45 80 ns
50 pF 60 90 ns
L
e
50 pF 40 70 ns
L
e
150 pF 80 110 ns
L
e
150 pF 60 90 ns
L
e
50 pF 45 70 ns
L
e
50 pF 25 50 ns
L
e
150 pF 60 90 ns
L
e
150 pF 40 70 ns
L
e
50 pF
L
10V 35 60 ns
e
1k, C
50 pF
L
5V 50 90 ns 10V 30 60 ns
e
5V, C 10V, C 5V, C 10V, C
50 pF 45 80 ns
L
e
50 pF 30 60 ns
L
e
150 pF 75 140 ns
L
e
150 pF 50 100 ns
L
(Output Enabled per Buffer)
MM54C240/MM74C240 100 pF MM54C244/MM74C244 100 pF
(Output Disabled per Buffer)
MM54C240/MM74C240 10 pF MM54C244/MM74C244 0 pF
C
IN
C
O
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
PD
AN-90.
Input Capacitance V (Any Input)
Output Capacitance V (Output Disabled)
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note,
e
0V, fe1 MHz, T
IN
e
0V, fe1 MHz, T
IN
e
25§C
A
e
25§C
A
10 pF
10 pF
Typical Application
TL/F/5905– 5
3
Truth Tables
MM54C240/MM74C240
ODA IA OA
1XZ 1XZ 001 010
MM54C244/MM74C244
ODA IA OA
1XZ 1XZ 000 011
e
1
High
e
0
Low
e
X
Don’t Care
e
Z
TRI-STATE
Typical Performance Characteristics
N-Channel Output Drive at 25
C
§
ODB IB OB
1XZ 1XZ 001 010
ODB IB OB
1XZ 1XZ 000 011
P-Channel Output Drive at 25
C
§
MM54C240/MM74C240 Propagation Delay vs. Load Capacitance
TL/F/5905– 6
TL/F/5905– 8
TL/F/5905– 7
MM54C244/MM74C244 Propagation Delay vs. Load Capacitance
TL/F/5905– 9
4
AC Test Circuits and Switching Time Waveforms
t
pd0,tpd1
TL/F/5905– 10
CMOS to CMOS
TL/F/5905– 11
t1Hand t
H1
t0Hand t
H0
Note: Delays measured with input t
TL/F/5905– 12
TL/F/5905– 14
s
20 ns.
r,tf
t
1H
Note: VOHis defined as the DC output high voltage when the device is loaded with
a1kXresistor to ground.
t
0H
Note: VOLis defined as the DC output low voltage when the device is loaded with a
1kXresistor to V
.
CC
t
H1
TL/F/5905– 13
t
H0
TL/F/5905– 15
5
Physical Dimensions inches (millimeters)
Order Number MM54C240J, MM54C244J, MM74C240J or MM74C244J
Ceramic Dual-In-Line Package (J)
See NS Package Number J20A
Octal Buffers and Line Drivers with TRI-STATE Outputs
Order Number MM54C240N, MM54C244N, MM74C240N or MM74C244N
LIFE SUPPORT POLICY
MM54C240/MM74C240 Inverting, MM54C244/MM74C244 Non-Inverting
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.
Molded Dual-In-Line Package (N)
See NS Package Number N20A
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