Datasheet MM5452, MM5453 Datasheet (National Semiconductor)

MM5452/MM5453 Liquid Crystal Display Drivers
Y
General Description
The MM5452 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devic­es. It is available in a 40-pin molded package. The chip can drive up to 32 segments of LCD and can be paralleled to increase this number. The chip is capable of driving a 4 (/2­digit 7-segment display with minimal interface between the display and the data source.
The MM5452 stores display data in latches after it is clocked in, and holds the data until new display data is re­ceived.
Features
Y
Serial data input
Y
No load signal required
Block Diagram
DATA ENABLE (MM5452)
Y
Wide power supply operation
Y
TTL compatibility
Y
32 or 33 outputs
Y
Alphanumeric and bar graph capability
Y
Cascaded operation capability
Applications
Y
COPSTMor microprocessor displays
Y
Industrial control indicator
Y
Digital clock, thermometer, counter, voltmeter
Y
Instrumentation readouts
Y
Remote displays
MM5452/MM5453 Liquid Crystal Display Drivers
February 1995
FIGURE 1
TL/F/6137– 1
COPSTMis a trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/6137
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Voltage at Any Pin V
SS
Operating Temperature 0§Ctoa70§C
to V
a
10V
SS
Storage Temperature
Power Dissipation 300 mW ata70§C
Junction Temperature
b
65§Ctoa150§C
350 mW at
a
a
25§C
150§C
Lead Temperature (Soldering, 10 sec.) 300§C
Electrical Characteristics
TAwithin operating range, V
DD
e
3.0V to 10V, V
Parameter Conditions Min Typ Max Units
Power Supply 3 10 V
Power Supply Current Excluding Outputs
e
OSC
VSS,BPIN@32 Hz 40 mA
e
V
5V, Open Outputs, No Clock 10 mA
DD
Clock Frequency 500 kHz
Input Voltages
Logical ‘0’ Level V
Logical ‘1’ Level V
k
4.75
DD
t
V
4.75
DD
l
5.25 0.8 V
DD
s
V
5.25 2.0 V
DD
Output Current Levels
Segments
Sink V Source V
Backplane
Sink V Source V
DD
DD
DD
DD
e
3V, V
e
3V, V
e
3V, V
e
3V, V
Output Offset Voltage Segment Load 250 pF
Backplane Load 8750 pF (Note 1)
Clock Input Frequency, f
High Time, t
Low Time, t
h
l
(Notes 2 and 3) 500 kHz
C
Data Input
Set-Up Time, t Hold Time, t
DS
DH
Data Enable Input
Set-Up Time, t
Note 1: This parameter is guaranteed (not 100% production tested) over operating temperature and supply voltage ranges. Not to be used in Q.A. testing.
Note 2: AC input waveform for test purpose: t
Note 3: Clock input rise and fall times must not exceed 300 ns.
DES
r
s
20 ns, t
e
0V, unless otherwise specified
SS
e
0.3V
OUT
e
b
V
OUT
e
OUT
e
OUT
s
20 ns, fe500 kHz, 50%g10% duty cycle.
f
0.3V 20 mA
DD
0.3V
b
V
0.3V 320 mA
DD
b
0.3 0.1 V
b
0.3 0.8 V
DD
DD
V
DD
DD
b
20 mA
b
320 mA
g
50 mV
950 ns
950 ns
300 ns 300 ns
100 ns
V
V V
2
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
Top View
TL/F/6137– 2
FIGURE 2a
Plastic Chip Carrier
TL/F/6137– 11
Top View
Order Number MM5452N, MM5453N,
MM5452V or MM5453V
See NS Package Number N40A or V44A
Functional Description
The MM5452 is specifically designed to operate 4 (/2-digit 7­segment displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Since the MM5452 does not contain a character generator, the formatting of the segment information must be done prior to inputting the data to the MM5452. Using a format of a leading ‘‘1’’ followed by the 32 data bits allows data transfer without an additional load signal. The 32 data
Top View
FIGURE 2b
Plastic Chip Carrier
Top View
bits are latched after the 36th clock is complete, thus pro­viding non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time.
A block diagram is shown in DATA ENABLE DATA ENABLE be brought out. This is the MM5453 device.
is used instead of the 33rd output. If the
signal is not required, the 33rd output can
Figure 1.
TL/F/6137– 3
TL/F/6137– 12
For the MM5452 a
3
Functional Description (Continued)
Figure 4
shows the input data format. A start bit of logical ‘‘1’’ precedes the 32 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 32 bits of the shift registers into the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master-slave configura­tion. There is no clear for the master portion of the first shift register, thus allowing continuous operation.
If the clock is not continuous, there must be a complete set of 36 clocks otherwise the shift registers will not clear.
Figure 2a
bit following the start bit and it will appear on pin 18.
Figure 3
and DATA ENABLE
shows the pin-out of the MM5452. Bit 1 is the first
shows the timing relationships between data, clock
.
FIGURE 3
FIGURE 4. Input Data Format
TL/F/6137– 4
TL/F/6137– 5
4
Functional Description (Continued)
Figure 5
data maps to the output pins and the display. The MM5452 and MM5453 do not have format restrictions, as all outputs
shows a typical application. Note how the input
are controllable. This application assumes a specific display pinout. Different display/driver connection patterns will, of course, yield a different input data format.
Consult LCD manufacturer’s data sheet for specific pinouts.
FIGURE 5. Typical 4(/2-Digit Display Application
TL/F/6137– 6
5
Functional Description (Continued)
*The minimum recommended value for R for the oscillator input is 9 kX . An RC time constant of approximately
b
4
c
4.91
10
should produce a backplane frequency between 30 Hz and 150 Hz.
FIGURE 6. Parallel Backplane Outputs
FIGURE 7. External Backplane Clock
Figure 8
shows a four wire remote display that takes advan­tage of the device’s serial input to move many bits of display information on a few wires.
USING AN EXTERNAL CLOCK
The MM5452/MM5453 LCD Drivers can be used with an externally supplied clock, provided it has a duty cycle of 50%. Deviations from a 50% duty cycle result in an offset voltage on the LCD. In
Figure 7,
a flip-flop is used to assure a 50% duty cycle. The oscillator input is grounded to pre­vent oscillation and reduce current consumptions in the chips. The oscillator is not used.
Using an external clock allows synchronizing the display drive with AC power, internal clocks, or DVM integration time to reduce interference from the display.
TL/F/6137– 7
Figure 9
is a general block diagram that shows how the device’s serial input can be used to advantage in an analog display. The analog voltage input is compared with a stair­case voltage generated by a counter and a digital-to-analog converter or resistor array. The result of this comparison is clocked into the MM5452, MM5453. The next clock pulse increments the staircase and clocks the new data in.
With a buffer amplifier, the same staircase waveform can be used for many displays. The digital-to-analog converter need not be linear; logarithmic or other non-linear functions can be displayed by using weighted resistors or special DACs. This system can be used for status indicators, spec­trum analyzers, audio level and power meters, tuning indica­tors, and other applications.
6
TL/F/6137– 8
Functional Description (Continued)
FIGURE 8. Four Wire Remote Display
Data is high until staircaselinput
FIGURE 9. Analog Display
Physical Dimensions inches (millimeters)
TL/F/6137– 9
TL/F/6137– 10
Molded Dual-In-Line Package (N)
Order Number MM5452N or MM5453N
NS Package Number N40A
7
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number MM5452V or MM5453V
NS Package Number V44A
MM5452/MM5453 Liquid Crystal Display Drivers
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