National Semiconductor LP3936 Technical data

June 2005

LP3936 Lighting Management System for Six White LEDs and One RGB or FLASH LED

LP3936Lighting Management System for Six White LEDs and One RGB or FLASH LED

General Description

LP3936 is a complete lighting management system designed for portable wireless applications. It contains a boost DC/DC converter, 4 white LED drivers to drive the main LCD panel backlight, 2 white LED drivers for sub-LCD panel and 1 set of RGB LED drivers.

Both WLED groups have 8-bit programmable constant current drivers that are separately adjustable and matched to 1% (typ.). For efficient backlighting the backlight intensity can be adjusted using the 8-bit ADC with ambient light detection circuit.

The RGB LED drivers are PWM-driven with programmable color, intensity and blinking patterns. In addition, they feature a FLASH function to support picture taking with cameraenabled cellular phones.

An efficient magnetic boost converter provides the required bias operating from a single Li-Ion battery. The DC/DC converter output voltage is user programmable for adapting to different LED types and for efficiency optimization. All functions are software controllable through an I MicroWire/SPI compatible interface and 16 internal registers.

C and

Typical Application

Features

n High Efficiency 250 mA Magnetic Boost DC-DC

Converter with Programmable Output Voltage

n PWM controlled RGB LED drivers with programmable

color, brightness, turn on/off slopes and blinking

n FLASH function with 3 drivers, each up to 120 mA

current

n 4 constant current White LED drivers with

programmable 8-bit adjustment (0 … 25 mA/LED)

n 2 constant current White LED drivers with

programmable 8-bit adjustment (0 … 25 mA/LED)

n 8-bit ADC for ambient light sensor with averaging n Combined MicroWire/SPI and I

interface

n Low current Standby mode (software controlled) n Low voltage digital interface down to 1.8V n Space efficient 32-pin thin CSP laminate package

C compatible serial

Applications

n Cellular Phones n PDAs

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Connection Diagrams and Package Mark Information

LP3936

32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm pitch

See NS Package Number SLD32A

Top View

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Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably.

Bottom View

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Package Mark — Top View

Ordering Information

Order Number Package Marking Supplied As

LP3936SL LP3936SL 1000 units, Tape-and-Reel

LP3936SLX LP3936SL 2500 units, Tape-and-Reel

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Pin Description

Pin Name Type Description

1 GND_BOOST Ground Power Switch Ground

2 FB Input Boost Converter Feedback

DD2

4 GND2 Ground Ground Return for V

5 WLED1 LED Output Open Drain, White LED1 Output

6 WLED2 LED Output Open Drain, White LED2 Output

7 WLED3 LED Output Open Drain, White LED3 Output

8 WLED4 LED Output Open Drain, White LED4 Output

9 GND_WLED Ground 4+2 White LED Driver Ground

10 WLED5 LED Output Open Drain, White LED5 Output

11 WLED6 LED Output Open Drain, White LED6 Output

12 V

DDA

13 GND1 Ground Ground Return for V

14 V

DD1

15 AIN Input Ambient Light Sensor Input

16 AREF Output Reference Voltage for Ambient Light Sensor, 1.23V

17 GND_T Ground Ground

18 V

REF

19 RT Input Oscillator Resistor

20 MW_SEL Logic Input MicroWire — I

21 NRST Logic Input Low Active Reset Input

22 CS Logic

23 DO Logic Output MicroWire Data Output

24 DI Logic Input MicroWire Data Input

25 SCL Logic Input MicroWire Clock / I

26 RGB_EN Logic Input LED Control for On/Off or PWM Dimming

27 V

DD_IO

28 ROUT LED Output Open Drain Output, Red LED

29 GOUT LED Output Open Drain Output, Green LED

30 BOUT LED Output Open Drain Output, Blue LED

31 GND_RGB Ground Ground for RGB Drivers

32 OUT Output Open Drain, Boost Converter Power Switch

Power Supply Voltage for Internal Digital Circuits

(Internal Digital)

DD2

Output Internal LDO Output, 2.8V

(Internal Analog)

DD1

Power Supply Voltage for Internal Analog Circuits

Output Internal Reference Bypass Capacitor

C select (MW_SEL=1 in MicroWire Mode)

MicroWire Chip-Select (in) / I

C SDA (in/out)

Input/Output

C SCL Input

Power Supply Voltage for Logic IO signals

LP3936

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Absolute Maximum Ratings (Notes 1,

LP3936

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

DD1,VDD2,VDD_IO

Voltage on Logic Pins -0.3V to V

Voltage on LED Output Pins -0.3V to V(FB) +

Voltage on All Other Pins -0.3V to V

I (ROUT, GOUT, BOUT) 150 mA

I(V

)10µA

REF

, V(OUT, FB) -0.3V to 6.0V

0.3V, with 6.0V max

DD_IO

DD1,2

Maximum Lead Temperature 260˚C

(Reflow soldering, 3 times) (Note 4)

ESD Rating (Note 5)

Human Body Model: 2 kV

Machine Model: 200V

Operating Ratings (Notes 1, 2)

DD1,VDD2

DD_IO

Recommended Load Current 0 mA to 250 mA

Junction Temperature (T

Ambient Temperature (T

) Range −40˚C to +125˚C

) Range

(Note 6) −40˚C to +85˚C

3.0V to 6.0V

1.65V – V

Continuous Power Dissipation

(Note 3) Internally Limited

Junction Temperature (T

) 125˚C

J-MAX

Storage Temperature Range −65˚C to +150˚C

Thermal Properties

Junction-to-Ambient Thermal Resistance (θJA),

SLD32A Package (Note 7) 72˚C/W

Electrical Characteristics (Notes 2, 8)

Limits in standard typeface are for TJ= 25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ T = 3.6V, C

Symbol Parameter Condition Min Typ Max Units

DD1,2

DD_IO

REF

DDA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins (GND1, GND2, GND_T, GND_BOOST, GND_WLED, GND_RGB).

Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T

140˚C (typ.).

Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA Package (AN-1125).

Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7

≤ +85˚C). Unless otherwise noted, specifications apply to the Section Block Diagram with: V

VDD1,CVDD2,CVDDIO

= 1 µF, CIN,C

OUT

= 10 µF, C

VDDA

= 1 µF, C

VREF

= 0.1 µF, L

BOOST

DD1=VDD2=VDD_IO

= 10 µH (Note 9).

Supply Voltage 3.0 3.6 6.0 V

Standby Supply Current (V

DD1

and V

DD2

current)

No-Load Supply Current (V

DD1

and V

current, boost off)

DD2

NSTBY = L (register) CS, SCL, DI, NRST = H V

DD1,VDD2

= 3.6V

NSTBY = H (reg.) EN_BOOST = L (reg.)

1 7 µA

170 300 µA

SCL, CS, DI, NRST = H

Full Load Supply Current (V

DD1

and V

current, boost on)

DD2

NSTBY = H (register) NRST, CS, SCL, DI = H

1mA

RGB_EN = L WLED1…6=L EN_AMBADC = L

Standby Supply Current NSTBY = L (register)

DD_IO

1µA

CS, SCL, DI, NRST = H

Operating Supply Current 1 MHz Clock Frequency

DD_IO

=50pFatDOpin

Reference Voltage (Note 10) I

REF

≤ 1 nA,

Test Purposes Only

LDO Output Voltage IV

DDA

1.205

−2

1µA 2.688

–4

20 µA

1.23 1.255

2.8 2.912 +4

= 160˚C (typ.) and disengages at TJ=

DD1,2

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Electrical Characteristics (Notes 2, 8) (Continued)

Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T dissipation of the device in the application (P following equation: T

Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

Note 10: V

A-MAX=TJ-MAX-OP

pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between V

REF

) is dependent on the maximum operating junction temperature (T

A-MAX

), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

D-MAX

−(θJAxP

D-MAX

= 125˚C), the maximum power

J-MAX-OP

and GND1.

REF

Block Diagram

LP3936

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Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values. Boost output register is set to

LP3936

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low

STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is

NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be written

4.55V (register 0Dh = 07h), ext_pwm is enabled for color outputs (register 2Bh = 1Ch), EN_BOOST bit is high (register 0Bh bit 5) and all other registers are set to 00h. Reset is entered always if input NRST is LOW or internal Power On Reset is active.

power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up.

, Bias, Oscillator, etc.).

REF

To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event is present.

raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During Boost Startup all LEDs are turned off to reduce the loading.

in any sequence and any number of bits can be altered in a register in one write.

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LP3936

Logic Interface Characteristics (1.8V ≤ V

DD_IO

≤ V

DD1,2

) (Note 11)

Symbol Parameter Conditions Min Typ Max Units

LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL

SCL

Input Low Level 0.5 V

Input High Level V

− 0.5 V

DD_IO

Logic Input Current −1.0 1.0 µA

Clock Frequency I2C Mode 400 kHz

MicroWire Mode 8 MHz

LOGIC OUTPUTS DO, CS

Logic Interface Characteristics (1.65V ≤ V

Output Low Level I

Output High Level IDO=−3mA V

=3mA 0.3 0.6 V

DO, CS

DD_IO

− 0.6 V

− 0.3 V

DD_IO

Output Leakage Current VDO= 2.8V 1.0 µA

DD_IO

≤ 1.8V) (Note 11)

Symbol Parameter Conditions Min Typ Max Units

LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL

SCL

Input Low Level 0.35 V

Input High Level V

− 0.35 V

DD_IO

Logic Input Current −1.0 1.0 µA

Clock Frequency I2C Mode 200 kHz

MicroWire Mode 4 MHz

LOGIC OUTPUTS DO, CS

Note 11: In I2C mode operating ratings are limited to 3.0V ≤ V

Output Low Level I

Output High Level IDO= − 2mA V

= 2mA 0.3 0.6 V

DO, CS

DD_IO

− 0.6 V

− 0.3 V

DD_IO

Output Leakage Current VDO= 2.8V 1.0 µA

≤ 4.5V and –20˚C ≤ TA≤ +85˚C.

DD1,2

Control Interface

The LP3936 supports two different interfaces modes:

1) MicroWire/SPI interface

2) I

C compatible interface

User can define the interface by MW_SEL pin. The pin configuration will also change depending on which interface

MW_SEL Interface Pin Configuration Comment

1 MicroWire/SPI SCL

DI DO CS

C Compatible SCL

CS = SDA

(clock) (data in) (data out) (chip select)

(clock) (data in/out)

is selected. The following table shows the selections for both interface modes.

Use pull up resistor for SCL Use pull up resistor for SDA

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