National Semiconductor LP3933 Technical data

March 2004

LP3933 Lighting Management System for Six White LEDs and Two RGB or FLASH LEDs

General Description

The LP3933 is a complete lighting management system designed for portable wireless applications. It contains a boost DC/DC converter, 4 white-LED drivers to drive the main LCD panel backlight, 2 white-LED drivers for the subLCD panel and two sets of RGB/FLASH LED drivers.

Both backlight drivers have 8-bit constant current drivers that are separately adjustable and matched to 0.5% (typ.). The RGB LED drivers are PWM-driven with programmable color, intensity and blinking patterns. In addition, they feature a FLASH function to support picture taking with cameraenabled cellular phones.

An efficient magnetic boost DC/DC converter provides the required bias for LEDs, operating from a single Li-Ion battery. The DC/DC converter output voltage is user programmable from 4.1V to 5.3V for adapting to different LED types and for efficiency optimization. All functions are software controllable through a SPI interface and 19 internal registers.

Typical Application

Features

n High Efficiency Programmable 300 mA Magnetic Boost

DC-DC converter

n 2 separately controlled PWM RGB LED drivers with

programmable color, brightness, turn on/off slopes and blinking patterns

n FLASH function with up to 6 outputs, each up to 120

n 4 constant current LED drivers with programmable 8-bit

adjustment (0 … 25 mA/LED)

n 2 constant current LED drivers with programmable 8-bit

adjustment (0 … 25 mA/LED)

n Functions software controlled through SPI interface n Additional LED on/off and dimming hardware control n Programmable low current Standby mode n Low voltage digital interface down to 1.8V n Space efficient 32-pin thin CSP laminate package

Applications

n Cellular Phones n PDAs

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Connection Diagrams and Package Mark Information

LP3933

32-Lead Thin CSP Package, 4.5 x 5.5 x 0.8 mm, 0.5 mm pitch

See NS Package Number SLE32A

20080509

20080508

20080507

Package Mark — TOP VIEW

Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates

the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably.

Ordering Information

Order Number Package Marking Supplied As

LP3933SL LP3933SL 1000 units, Tape-and-Reel

LP3933SLX LP3933SL 2500 units, Tape-and-Reel

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Pin Description

Pin # Name Type Description

1 FB Input Boost Converter Feedback

2 GND_BOOST Ground Power Switch Ground

3 SW Output Open Drain, Boost Converter Power Switch

DD2

5 GND2 Ground Ground Return for V

6 CLED1 Output Open Drain, CLED1 Output

7 CLED2 Output Open Drain, CLED2 Output

8 GND_WLED Ground Ground for WLED and CLED Drivers

9 WLED1 Output Open Drain, White LED1 Output

10 WLED2 Output Open Drain, White LED2 Output

11 WLED3 Output Open Drain, White LED3 Output

12 WLED4 Output Open Drain, White LED4 Output

13 RT Input Oscillator Resistor

14 V

DD1

15 GND1 Ground Ground

16 V

REF

17 GND3 Ground Ground

18 NRST Logic Input Low Active Reset Input

19 SS Logic Input SPI Slave Select

20 SO Logic Output SPI Serial Data Output

21 SI Logic Input SPI Serial Data Input

22 SCK Logic Input SPI Clock

23 PWM_LED Logic Input LED Control for On/Off or Dimming Control

24 V

DD_IO

25 GND4 Ground Ground

26 B2 Output Open Drain Output, Blue LED 2

27 G2 Output Open Drain Output, Green LED 2

28 R2 Output Open Drain Output, Red LED 2

29 GND_RGB Ground RGB Driver Ground

30 R1 Output Open Drain Output, Red LED 1

31 G1 Output Open Drain Output, Green LED 1

32 B1 Output Open Drain Output, Blue LED 1

Power Supply Voltage for Internal Digital Circuits

(Internal Digital)

DD2

Power Supply Voltage for Internal Analog Circuits

Output Internal Reference Bypass Capacitor

Power Supply Voltage for Logic IO Signals

LP3933

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Absolute Maximum Ratings (Notes 1,

LP3933

If Military/Aerospace specified devices are required,

ESD Rating (Notes 8, 14)

Human Body Model: 2 kV

Machine Model: 200V

please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

V (SW, FB, WLED1-4, CLED1-2,

R1-2, G1-2, B1-2) pins: Voltage to GND (Notes 3, 4) −0.3V to +7.2V

DD1,VDD2,VDD_IO

−0.3V to +6.0V

Voltage on Logic Pins -0.3V to V

0.3V, with 6.0V max

I (R1, G1, B1, R2, G2, B2)

(Note 5) 150 mA

)10µA

I(V

REF

DD_IO

Operating Ratings (Notes 1, 2)

V (SW, FB, WLED1-4, CLED1-2,

R1-2, G1-2, B1-2) 3.0V to 6.0V

DD1,VDD2

DD_IO

Recommended Load Current 0 mA to 300 mA

Junction Temperature (T

Ambient Temperature (T

(Note 9) −40˚C to +85˚C

(Note 4) 2.65 to 2.9V

1.8V to V

) Range −40˚C to +125˚C

) Range

Continuous Power Dissipation

(Note 6) Internally Limited

Junction Temperature (T

) 125˚C

J-MAX

Storage Temperature Range −65˚C to +150˚C

Thermal Properties

Junction-to-Ambient Thermal Resistance (θJA),

SLE32A Package (Note 10) 72˚C/W

Maximum Lead Temperature

(Reflow soldering, 3 times) (Note 7) 260˚C

Electrical Characteristics (Notes 2, 11)

Limits in standard typeface are for TJ= 25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ T =V

DD2

Symbol Parameter Condition Min Typ Max Units

DD_IO

REF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins (GND1-4, GND_BOOST, GND_WLED, GND_RGB).

Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.

Note 4: Voltage tolerance of LP3933 above 6.0V relies on fact that V

(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.

Note 5: The total load current of the boost converter should be limited to 300 mA.

Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T

140˚C (typ.).

Note 7: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA.

Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin. MIL-STD-883 3015.7

≤ +85˚C). Unless otherwise noted, specifications apply to the LP3933 Functional Block Diagram (pg. 5) with: V

= 2.775V, C

VDD1=CVDD2=CVDDIO

Standby Supply Current (V

DD1

and V

DD2

current)

No-Load Supply Current (V

DD1

and V

current, boost off)

DD2

= 0.1 µF, C

OUT=CIN

NSTBY = L (register) SCK, SS, SI, NRST = H

NSTBY = H (reg.) EN_BOOST = L (reg.)

= 10 µF, C

= 0.1 µF, L1= 10 µH (Note 12).

VREF

1 5 µA

170 300 µA

SCK, SS, SI, NRST = H

Full Load Supply Current (V

DD1

and V

current, boost on)

DD2

NSTBY = H (reg.) EN_BOOST = H (reg.)

1mA

SCK, SS, SI, NRST = H All Outputs Active

Standby Supply Current NSTBY = L (register)

DD_IO

1 5 µA

SCK, SS, SI, NRST = H

Operating Supply Current 1 MHz Clock Frequency

DD_IO

=50pFatSOpin

Reference Voltage (Note 13) I(V

REF

) ≤ 1 nA,

Test Purposes Only

and V

DD1

1.205

−2

(2.775V) are available (ON) at all conditions. If V

DD2

20 µA

1.23 1.255

and V

DD1

DD2

= 160˚C (typ.) and disengages at TJ=

are not available

DD1,2

DD1

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Electrical Characteristics (Notes 2, 11) (Continued)

Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T dissipation of the device in the application (P following equation: T

Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.

Note 13: V

Note 14: ESD susceptibility for pin 11 and 12 is 500V for the human body model and 150V for the machine model.

A-MAX=TJ-MAX-OP

pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between V

REF

) is dependent on the maximum operating junction temperature (T

A-MAX

), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

D-MAX

−(θJAxP

D-MAX

= 125˚C), the maximum power

J-MAX-OP

and GND1.

REF

Block Diagram

LP3933

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Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values (Boost output register 3Fh

LP3933

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low

STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V

BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is

NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be written

(5.0V), all other registers 00h). Reset is entered always if input NRST is LOW or internal Power On Reset is active.

power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up.

, Bias, Oscillator etc.).

REF

To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event is present.

raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.

in any sequence and any number of bits can be altered in a register in one write.

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