National Semiconductor LP3905 Technical data
LP3905
Power Management Unit For Low Power Handheld
Applications
LP3905 Power Management Unit For Low Power Handheld Applications
August 2006
General Description
LP3905 is a multi-functional Power Management Unit,
optimized for low power handheld applications. This device
integrates two 600mA DC/DC buck regulators and two
150mA linear regulators. Fixed and adjustable buck output
versions are available. The LP3905 additionally features two
enable pins for the device output control and is offered in an
LLP package.
Features
n Two buck regulators for powering high current processor
functions or peripheral devices
n Two linear regulators for powering internal processor
functions and I/Os
n One enable pin for Buck1 and Linear Regulators1&2
n Separate enable pin for Buck2
n Thermal and current overload protection
n Small 14–Pin LLP package (4mm x 4mm x 0.8mm)
Applications
n Baseband Processors
n Peripheral Processor (Video, Audio)
n I/O Power
n FPGA Power
Key Specifications
Buck Regulators
n Fixed and adjustable voltage options, range 1.0V to
3.3V *
n Up to 90% Efficiency
n Auto-switching PFM-PWM mode and fixed PWM mode
n 2MHz PWM fixed switching frequency (Typ)
n 600mA output current
±
n
4% output voltage accuracy over temp.
n Internal softstart
n 2.2µH inductor, 10µF Input and 10µF output Caps
Linear Regulators
n Output options in the range 1.5V to 3.3V *
n 13.5µV
n PSRR - 70dB
±
n
3% output voltage accuracy over full line and load
regulation
n 0mA to 150mA output current
n C
in
C
in
80mV Dropout voltage
* Fixed output voltage devices can be customized to fit
system requirements. Please contact National Semiconductor Sales Office.
output voltage noise
rms
@
= 1.0µF, C
= 1.0µF, C
out
out
1kHz
= 0.47µF for 100mA O/P
= 1.0µF for 150mA O/P
Typical Application Circuit
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FIGURE 1. Typical Application Circuit – 14 Pin LLP Package
© 2006 National Semiconductor Corporation DS201529 www.national.com
Block Diagram
LP3905
Connection Diagram
20152902
FIGURE 2. Simplified Functional Diagram
20152907
FIGURE 3. 14 Pin LLP Package
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Connection Diagram (Continued)
Pin Descriptions
Pin # Name Description
1 EN2 Enable Pin for Buck2
2 TGND Ground Pin
3 LDO2 LDO2 Output Pin
4 VIN2 Input Power Terminal to LDO1 & 2
5 LDO1 LDO1 Output Pin
6 GND LDO1 & 2 Ground Pin
7 EN1 Enable Pin for Buck1 and LDO1&2
8 FB1 Buck1 Feedback Pin
9 GND_B1 Buck1 Ground Pin
10 SW1 Buck1 Switch Pin
11 VIN1 Input Power Terminal to Buck1 & 2
12 SW2 Buck2 Switch Pin
13 GND_B2 Buck2 Ground Pin
14 FB2 Buck2 Feedback Pin
DAP SGND Die Attach Pad (DAP)
Package Marking Diagram
LP3905
20152905
The physical placement of the package marking will vary from part to part.
•
Date Code - UZXYTT format. ’U’ - Wafer fab code; ’Z’ - assembly site code; ’XY’ 2 digit date code; ’TT’ die run code
•
See National Web site for more info - http://www.national.com/quality/marking_conventions.html
•
FIGURE 4. LP3905 14 Pin LLP Package Marking
NS package number SDA14B
Ordering Information
Buck 1 [V] Buck 2 [V] LDO 1 [V] LDO 2 [V] Order Number Package Marking Supplied As
1.2 1.875 2.8 2.8 LP3905SD-00
LP3905SDX-00 4500 units, Tape-and-Reel
1.2 Fixed
PWM
ADJ ADJ 3.0 2.8 LP3905SD-A3
1.875
Fixed
PWM
2.8 2.8 LP3905SD-30
LP3905SDX-30 4500 units, Tape-and-Reel
LP3905SDX-A3 4500 units, Tape-and-Reel
3905-00
3905-30
3905-A3
1000 units, Tape-and-Reel
1000 units, Tape-and-Reel
1000 units, Tape-and-Reel
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
LP3905
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
1,VIN2 −0.2V to 6.0V
V
IN
FB1, FB2, EN1,EN2 (GND−0.2V) to
+ 0.2V) to 6.0V
(V
IN
Continuous Power Dissipation
(Note 3)
Junction Temperature (T
) +150˚C
J-MAX
Storage Temperature Range −65˚C to +150˚C
Maximum Lead Temperature
(Soldering, 10 sec.)
Internally Limited
(max)
260˚C
Operating Ratings (Notes 1, 2)
V
1 (Buck1&2 Input
IN
Voltage),V
Voltage) (Note 7)
Recommended Load Current
(Buck)
Recommended Load Current
(LDO)
Junction Temperature (T
Range
Ambient Temperature (T
Range (Note 5)
2 (LDO1&2 Input
IN
0mA to 100mA with
0mA to 150mA with
)
J
)
A
0mA to 600 mA
0.47uF O/P cap
1.0uF O/P cap
−40˚C to +125˚C
−40˚C to +85˚C
ESD Rating (Note 4)
Human Body Model: 2.5kV
Thermal Properties
Junction-to-Ambient
Thermal Resistance (θ
)
JA
SDA14B package(Note 6)
General Electrical Characteristics (Notes 2, 8, 9)
Limits in standard typeface are for TJ= 25˚C. Limits in boldface type apply over the full junction temperature range (−40˚C ≤
≤ +125˚C). Unless otherwise noted, specifications apply to the LP3905 Typical Application Circuit (Figure. 1)
T
J
Symbol Parameter Condition Min Typ Max Units
Login Input Thresholds
V
IN
I
Q
V
IH
V
IL
I
EN
V
UVLO-R
T
SHUTDOWN
Input Voltage Range 3 5.5 V
Shutdown Supply Current All Circuits OFF except for POR and
6.5 10.0 µA
UVLO
No load Supply Current (Note 15) LDO1 & 2 and Buck1&2on 140 250
( PWM only versions ) LDO1 & 2
7 10.0 mA
and Buck1&2on
Logic High Input VIN= 3.0V to 5.5V 1.2 V
Logic Low Input VIN= 3.0V to 5.5V 0.4 V
Enable (EN1,2) Input Current
(Note 14)
EN1/EN2 = 5.5V and VIN= 5.5V 2.1 5 8.5 µA
EN1/EN2 = 0V and V
= 5.5V 0.001 0.1 µA
IN
Battery Under Voltage Lock-Out VINRising 2.7 3.1 V
Thermal Shutdown (Note 15) Temperature 160
Hysteresis 20
3V to 5.5V
o
C/W
37.3
˚C
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General Electrical Characteristics (Notes 2, 8, 9) (Continued)
Buck Regulator Electrical Characteristics
Buck1&2have a current rating of I
(Buck1)
= Vnom1 , V
OUT(Buck2)
= Vnom2 and CIN=C
type apply over the full junction temperature range (−40˚C ≤ T
LP3905 Typical Application Circuit (Figure. 1) (Notes 2, 8)
Symbol Parameter Condition Min Typ Max Units
V
FB
V
OUT
Feedback Voltage (Note 16) -4 +4 %
Line Regulation 3.0V ≤ VIN≤ 5.5V
Load Regulation 100 mA ≤ I
R
DSON (P)
R
DSON (N)
I
LIM
F
OSC
Pin-Pin Resistance for PFET VIN=VGS= 3.6V 380 500 mΩ
Pin-Pin Resistance for NFET VIN=VGS= 3.6V (Note 15) 250 400 mΩ
Switch Peak Current Limit Open Loop 650 1000 1220 mA
Internal Oscillator Frequency PWM Mode 2 MHz
η Efficiency IOUT = 5mA, PFM mode (Note 15) 88 %
= 600mA. Unless otherwise specified, limits are set with VIN=V
max
=10µF. Limits in standard typeface are for TJ= 25˚C. Limits in boldface
OUT
I
O
= 1mA
≤ +125˚C). Unless otherwise noted, specifications apply to the
J
≤ 600mA 0.002 %/mA
O
IOUT = 300mA, PWM mode (Note 15) 90
= 3.8V, V
EN1/2
OUT
0.045 %/V
LDO Regulator Electrical Characteristics
The linear regulators have a current rating of I
Unless otherwise specified, limits are set with V
standard typeface are for T
= 25˚C. Limits in boldface type apply over the full junction temperature range (−40˚C ≤ TJ≤
J
+125˚C). Unless otherwise noted, specifications apply to the LP3905 Typical Application Circuit (Figure. 1)(Notes 2, 8)
Symbol Parameter Conditions Min Typ Max Units
∆V
OUT
Output Voltage Tolerance Over Full Line and Load Regulation −3 3 %
Line Regulation Error V
Load Regulation Error I
I
LOAD
V
I
SC
I
OUT
DO
Load Current (Notes 11, 15) 0 mA
Dropout Voltage I
Short Circuit Current Limit (Note 13) 300 500 mA
Maximum Output Current C
PSRR Power Supply Rejection Ratio
(Note 15)
e
n
Output Noise Voltage
(Note 15)
= 150mA with C
max
= 3.8V, V
IN
= 3.8V to 5.5V,
IN
= 1mA
I
OUT
= 1 mA to 100mA 0.003 %/mA
OUT
= 100mA 80 150 mV
OUT
= 1.0µF 150 mA
OUT
f = 100Hz, I
f = 1kHz, I
f = 10kHz, I
f = 50kHz, I
f = 100kHz, I
BW = 10Hz to
100kHz, V
Buck1 Turned ON
with I
LOAD
Buck2 Turned OFF
= 1.0µF. A 100mA rating applies with C
OUT
= 3.8V, CIN= 1µF, C
EN1/2
= 100mA 90
OUT
= 100mA 90
OUT
= 100mA 60
OUT
= 100mA 35
OUT
= 100mA 25
OUT
= 1mA
I
OUT
= 4.2V
IN
I
= 100mA 15.5
= 0mA,
OUT
OUT
= 0.47µF, I
= 0.47µF.
OUT
= 1.0mA. Limits in
OUT
0.05 %/V
µV
13.5
LP3905
-
dB
RMS
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