National Semiconductor LP38690-ADJ, LP38692-ADJ Technical data

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LP38690-ADJ/LP38692-ADJ
1A Low Dropout CMOS Linear Regulators with
Adjustable Output

Stable with Ceramic Output Capacitors

January 2005

LP38690-ADJ/LP38692-ADJ 1A Low Dropout CMOS Linear Regulators with Adjustable Output

Stable with Ceramic Output Capacitors

General Description

The LP38690/2-ADJ low dropout CMOS linear regulators
provide 2.5% precision reference voltage, extremely low
dropout voltage (450mV
excellent AC performance utilizing ultra low ESR ceramic
output capacitors.

The low thermal resistance of the LLP and SOT-223 pack­ages allow the full operating current to be used even in high
ambient temperature environments.

The use of a PMOS power transistor means that no DC base
drive current is required to bias it allowing ground pin current
to remain below 100 µA regardless of load current, input
voltage, or operating temperature.

Dropout Voltage: 450 mV (typ)
Ground Pin Current: 55 µA (typ) at full load.
Adjust Pin Voltage: 2.5% (25˚C) accuracy.

@

1A load current, V

@

1A (typ. 5V out).

OUT

= 5V) and

Typical Application Circuits

Features

n Output voltage range of 1.25V - 9V
n 2.5% adjust pin voltage accuracy (25˚C)
n Low dropout voltage: 450mV
n Wide input voltage range (2.7V to 10V)
n Precision (trimmed) bandgap reference
n Guaranteed specs for -40˚C to +125˚C
n 1µA off-state quiescent current
n Thermal overload protection
n Foldback current limiting
n SOT-223 and 6-Lead LLP packages
n Enable pin (LP38692-ADJ)

@

1A (typ, 5V out)

Applications

n Hard Disk Drives
n Notebook Computers
n Battery Powered Devices
n Portable Instrumentation

20126701

20126702

V

Note: *Minimum value required for stability.

© 2005 National Semiconductor Corporation DS201267 www.national.com

OUT=VADJ

x (1 + R1/R2)

Connection Diagrams

LP38690-ADJ/LP38692-ADJ

6-Lead LLP, Bottom View

LP38690SD-ADJ

Pin Description

PIN DESCRIPTION

V

IN

GND Circuit ground for the regulator. This is connected to the die through the lead frame, and also

V

OUT

V

EN

ADJ The adjust pin is used to set the regulated output voltage by connecting it to the external resistors

SOT-223, Top View

20126703

LP38692MP-ADJ

20126704

20126705

6-Lead LLP, Bottom View

LP38692SD-ADJ

This is the input supply voltage to the regulator. For LLP package devices, both VINpins must be
tied together for full current operation (500mA maximum per pin).

functions as the heat sink when the large ground pad is soldered down to a copper plane.

Regulated output voltage.

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

R1 and R2 (see Typical Application Circuit).

Ordering Information

Order Number Package Marking Package Type Package Drawing Supplied As

LP38690SD-ADJ L112B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692SD-ADJ L122B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692MP-ADJ LJNB SOT-223 MP05A 1000 Units Tape and Reel

LP38690SDX-ADJ L112B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692SDX-ADJ L122B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692MPX-ADJ LJNB SOT-223 MP05A 2000 Units Tape and Reel

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LP38690-ADJ/LP38692-ADJ

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

I

OUT

Internally Limited

Junction Temperature −40˚C to +150˚C

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Operating Ratings

Storage Temperature Range −65˚C to +150˚C

Lead Temp. (Soldering, 5 seconds) 260˚C

ESD Rating (Note 3) 2 kV

Power Dissipation (Note 2) Internally Limited

V(max) All pins (with respect to GND) -0.3V to 12V

Electrical Characteristics Limits in standard typeface are for T

over the full operating temperature range. Unless otherwise specified: V
Min/Max limits are guaranteed through testing, statistical correlation, or design.

Symbol Parameter Conditions Min

V

= 2.7V 1.219 1.25 1.281

IN

V

ADJ

∆V

/∆V

O

∆V

/∆I

O

V

IN-VO

I

Q

I

(MIN) Minimum Load Current VIN-VO≤ 4V 100

L

I

FB

PSRR Ripple Rejection V

T

SD

T

SD

(HYST)

I

ADJ

ADJ Pin Voltage

Output Voltage Line Regulation

IN

(Note 6)

Output Voltage Load Regulation

L

(Note 7)

Dropout Voltage (Note 8)

3.2V ≤ V
100 µA

<

IN

≤ 10V

<

I

L

VO+ 0.5V ≤ VIN≤ 10V

= 25mA

I

L

1mA<I
V

IN=VO

(V

O

=1A

I

L

(V

O

= 0.1A

I

L

=1A

I

L

(V

O

= 0.1A

I

L

=1A

I

L

(V

O

= 0.1A

I

L

=1A

I

L

L

= 1.8V)

= 2.5V)

= 3.3V)

= 5V)

<

+1V

1A

Quiescent Current VIN≤ 10V, IL= 100 µA - 1A 55 100

≤ 0.4V, (LP38692-ADJ Only) 0.001 1

EN

IN-VO

IN=VO

>

5V 450

O

<

4V 1500

+ 2V(DC), with 1V(p-p) /

Foldback Current Limit VIN-V

V

120Hz Ripple

Thermal Shutdown Activation
(Junction Temp)

Thermal Shutdown Hysteresis
(Junction Temp)

ADJ Input Leakage Current V

ADJ

V

IN

= 0 - 1.5V

= 10V

VINSupply Voltage 2.7V to 10V

Operating Junction

−40˚C to +125˚C

Temperature Range

= 25˚C, and limits in boldface type apply

J

IN=VOUT

+ 1V, CIN=C

OUT

= 10 µF, I

Typ

(Note 4)

1A

1.187 1.25 1.313

0.03 0.1 %/V

1.8 5 %/A

950 1600

80

800

65

650

45

450

55 dB

160

10

-100 0.01 100 nA

= 10mA.

LOAD

Max Units

V

145

1300

110

mV

1000

100
800

µAV

mA

˚C

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Electrical Characteristics Limits in standard typeface are for T

over the full operating temperature range. Unless otherwise specified: V

IN=VOUT

= 25˚C, and limits in boldface type apply

J

+ 1V, CIN=C

Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued)

OUT

= 10 µF, I

LOAD

= 10mA.

Symbol Parameter Conditions Min

e

n

VO(LEAK) Output Leakage Current VO=VO(NOM) + 1V@10V

V

EN

LP38690-ADJ/LP38692-ADJ

I

EN

Output Noise BW = 10Hz to 10kHz

= 3.3V

V

O

Enable Voltage (LP38692-ADJ
Only)

Enable Pin Leakage

Output = OFF 0.4

Output = ON, V

Output = ON, V

Output = ON, V

=4V 1.8

IN

=6V 3.0

IN

= 10V 4.0

IN

VEN= 0V or 10V, VIN= 10V -1 0.001 1

IN

Typ

(Note 4)

Max Units

0.7

0.5 2 µA

(LP38692-ADJ Only)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The
junction-to-ambient thermal resistance (θ
area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the SOT-223, the θ
for the LLP package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to application note AN-1187). If power disspation
causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

) for the SOT-223 is approximately 125 ˚C/W for a PC board mounting with the device soldered down to minimum copper

J-A

drops to approximately 70 ˚C/W. The θ

J-A

J-A

µV/

V

µA

values

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