LP2997
DDR-II Termination Regulator
LP2997 DDR-II Termination Regulator
June 2005
General Description
The LP2997 linear regulator is designed to meet the JEDEC
SSTL-18 specifications for termination of DDR-II memory.
The device contains a high-speed operational amplifier to
provide excellent response to load transients. The output
stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the
application as required for DDR-II SDRAM termination. The
LP2997 also incorporates a V
load regulation and a V
chipset and DIMMs.
An additional feature found on the LP2997 is an active low
shutdown (SD) pin that provides Suspend To RAM (STR)
functionality. When SD is pulled low the VTToutput will
tri-state providing a high impedance output, but, V
remain active. A power savings advantage can be obtained
in this mode through lower quiescent current.
REF
pin to provide superior
SENSE
output as a reference for the
will
REF
Typical Application Circuit
Features
n Source and sink current
n Low output voltage offset
n No external resistors required
n Linear topology
n Suspend to Ram (STR) functionality
n Low external component count
n Thermal Shutdown
n Available in SO-8, PSOP-8 packages
Applications
n DDR-II Termination Voltage
n SSTL-18 Termination
20109418
© 2005 National Semiconductor Corporation DS201094 www.national.com
Connection Diagrams
LP2997
Pin Descriptions
SO-8 Pin or
PSOP-8 Pin
1 GND Ground
2SD
3 VSENSE Feedback pin for regulating V
4 VREF Buffered internal reference voltage of V
5 VDDQ Input for internal reference equal to V
6 AVIN Analog input pin
7 PVIN Power input pin
8 VTT Output voltage for connection to termination
PSOP-8 Layout
20109403
20109404
SO-8 Layout
Name Function
Shutdown
resistors
.
TT
/2
DDQ
/2
DDQ
Ordering Information
Order Number Package Type
LP2997M SO-8 M08A 95 Units per Rail
LP2997MX SO-8 M08A 2500 Units Tape and Reel
LP2997MR PSOP-8 MRA08A 95 Units Tape and Reel
LP2997MRX PSOP-8 MRA08A 2500 Units Tape and Reel
NSC Package
Drawing
Supplied As
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LP2997
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, VDDQ to GND
No pin should exceed AVIN −0.3V to +6V
Storage Temp. Range −65˚C to +150˚C
Junction Temperature 150˚C
SO-8 Thermal Resistance (θJA) 151˚C/W
PSOP-8 Thermal Resistance (θ
) 43˚C/W
JA
Minimum ESD Rating (Note 2) 1kV
Operating Range
Junction Temp. Range (Note 3) 0˚C to +125˚C
AVIN to GND 2.2V to 5.5V
Lead Temperature (Soldering, 10 sec) 260˚C
Electrical Characteristics Specifications with standard typeface are for T
type apply over the full Operating Temperature Range (T
= 0˚C to +125˚C) (Note 4). Unless otherwise specified,
J
= 25˚C and limits in boldface
J
AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.
Symbol Parameter Conditions Min Typ Max Units
V
Z
REF
VREF
V
Voltage PVIN = VDDQ = 1.7V
REF
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
V
REF
Output
I
= -30 to +30 µA 2.5 kΩ
REF
0.837
0.887
0.936
0.860
0.910
0.959
0.887
0.937
0.986
Impedance
V
TT
Vos
I
Q
TT/VTT
VTTOutput Voltage I
VTTOutput Voltage
Offset (V
REF-VTT
)
Quiescent Current
=0A
OUT
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
=±0.5A (Note 7)
I
OUT
PVIN = VDDQ = 1.7V
PVIN = VDDQ = 1.8V
PVIN = VDDQ = 1.9V
I
=0A
OUT
= -0.5A
I
OUT
= +0.5A
I
OUT
I
= 0A (Note 5) 320 500
OUT
0.822
0.874
0.923
0.828
0.878
0.928
-25
-25
-25
0.856
0.908
0.957
0.856
0.908
0.957
0
0
0
0.887
0.939
0.988
0.890
0.940
0.990
25
25
25
(Note 5)
Z
I
SD
VDDQ
VDDQ Input Impedance 100 kΩ
Quiescent Current in
SD = 0V 115 150 µA
Shutdown (Note 5)
I
Q_SD
Shutdown Leakage
SD=0V 2 5 µA
Current
V
IH
Minimum Shutdown
1.9 V
High Level
V
IL
Maximum Shutdown
0.8 V
Low Level
I
SENSE
T
SD
T
_HYS Thermal Shutdown
SD
V
Input Current 13 nA
SENSE
Thermal Shutdown (Note 6) 165 Celsius
10 Celsius
Hysteresis
V
V
mV
µA
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Electrical Characteristics Specifications with standard typeface are for T
apply over the full Operating Temperature Range (T
LP2997
AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. (Continued)
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θ
junction to ambient with no heat sink.
Note 4: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: Quiescent current defined as the current flow into AVIN.
Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, T
the ambient temperature, T
shutdown.
Note 7: V
load regulation is tested by using a 10 ms current pulse and measuring VTT.
TT
. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
A
= 0˚C to +125˚C) (Note 4). Unless otherwise specified,
J
J(MAX)
= 25˚C and limits in boldface type
J
, the junction to ambient thermal resistance, θJA, and
= 151.2˚ C/W
JA
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Typical Performance Characteristics
LP2997
Iq vs AVINin SD Iq vs AV
20109420 20109421
VIHand V
IL
V
vs V
REF
IN
DDQ
VTTvs V
DDQ
20109422 20109424
Iq vs AVINin SD Temperature
20109426 20109427
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Typical Performance Characteristics (Continued)
LP2997
Iq vs AV
Maximum Sinking Current vs AV
(V
IN
DDQ
Temperature
20109428 20109435
IN
= 1.8V)
Maximum Sourcing Current vs AV
(V
= 1.8V, PVIN= 1.8V)
DDQ
IN
20109436
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Block Diagram
LP2997
20109405
Description
The LP2997 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-18. The output, V
TT
is capable of sinking and sourcing current while regulating
the output voltage equal to VDDQ / 2. The output stage has
been designed to maintain excellent load regulation while
preventing shoot through. The LP2997 also incorporates two
distinct power rails that separates the analog circuitry from
the power output stage. This allows a split rail approach to
be utilized to decrease internal power dissipation. It also
permits the LP2997 to provide a termination solution for the
next generation of DDR-SDRAM memory (DDRII).
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2997.
AVIN is used to supply all the internal control circuitry. PVIN,
however, is used exclusively to provide the rail voltage for
the output stage used to create V
capability to work off separate supplies, under the condition
that AVIN is always greater than or equal to PVIN. For
SSTL-18 applications, it is recommended to connect PVIN to
the 1.8V rail used for the memory core and AVIN to a rail
within its operating range of 2.2V to 5.5V (typically a 2.5V
supply). PVIN should always be used with either a 1.8V or
2.5V rail. This prevents the thermal limit from tripping because of excessive internal power dissipation. If the junction
temperature exceeds the thermal shutdown than the part will
enter a shutdown state identical to the manual shutdown
where V
is tri-stated and V
TT
REF
such as 1.5V can be used but it will reduce the maximum
output current, therefore it is not recommended for most
termination schemes.
VDDQ
VDDQ is the input used to create the internal reference
voltage for regulating V
. The reference voltage is gener-
TT
ated from a resistor divider of two internal 50kΩ resistors.
This guarantees that V
will track VDDQ / 2 precisely. The
TT
optimal implementation of VDDQ is as a remote sense. This
can be achieved by connecting VDDQ directly to the 1.8V
rail at the DIMM instead of PVIN. This ensures that the
reference voltage tracks the DDR memory rails precisely
without a large voltage drop from the power lines. For
SSTL-18 applications VDDQ will be a 1.8V signal, which will
. These pins have the
TT
remains active. A lower rail
create a 0.9V termination voltage at V
Characteristics Table for exact values of V
(See Electrical
TT
over tempera-
TT
ture).
V
SENSE
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termination resistors will connect to V
in a long plane. If the
TT
output voltage was regulated only at the output of the
LP2997 then the long trace will cause a significant IR drop
resulting in a termination voltage lower at one end of the bus
than the other. The V
pin can be used to improve this
SENSE
performance, by connecting it to the middle of the bus. This
will provide a better distribution across the entire termination
bus. If remote load regulation is not used then the V
SENSE
pin must still be connected to VTT. Care should be taken
when a long V
to the memory. Noise pickup in the V
problems with precise regulation of V
ramic capacitor placed next to the V
trace is implemented in close proximity
SENSE
trace can cause
SENSE
. A small 0.1uF ce-
TT
pin can help filter
SENSE
any high frequency signals and preventing errors.
SHUTDOWN
The LP2997 contains an active low shutdown pin that can be
used for suspend to RAM functionality. In this condition the
output will tri-state while the V
V
TT
output remains active
REF
providing a constant reference signal for the memory and
chipset. During shutdown V
should not be exposed to
TT
voltages that exceed PVIN. With the shutdown pin asserted
low the quiescent current of the LP2997 will drop, however,
VDDQ will always maintain its constant impedance of 100kΩ
for generating the internal reference. Therefore, to calculate
the total power loss in shutdown both currents need to be
considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal
pull-up current; therefore, to turn the part on the shutdown
pin can either be connected to AVIN or left open
V
REF
V
provides the buffered output of the internal reference
REF
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since these inputs are typically an extremely high impedance, there should be little current drawn from V
REF
. For
improved performance, an output bypass capacitor can be
used, located close to the pin, to help with noise. A ceramic
capacitor in the range of 0.1 µF to 0.01 µF is recommended.
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Pin Descriptions (Continued)
LP2997
This output remains active during the shutdown state and
thermal shutdown events for the suspend to RAM functionality.
V
TT
VTTis the regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2997 is
designed to handle continuous currents of up to +/- 0.5A with
excellent load regulation. If a transient is expected to last
above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should
be sized large enough to prevent an excessive voltage drop.
If the LP2997 is to operate in elevated temperatures for long
durations care should be taken to ensure that the maximum
junction temperature is not exceeded. Proper thermal derating should always be used. (Please refer to the Thermal
Dissipation section) If the junction temperature exceeds the
thermal shutdown point than V
will tri-state until the part
TT
returns below the temperature hysteresis trip-point
Component Selections
INPUT CAPACITOR
The LP2997 does not require a capacitor for input stability,
but it is recommended for improved performance during
large load transients to prevent the input rail from dropping.
The input capacitor should be located as close as possible to
the PVIN pin. Several recommendations exist dependent on
the application required. A typical value recommended for AL
electrolytic capacitors is 22 µF. Ceramic capacitors can also
be used. A value in the range of 10 µF with X5R or better
would be an ideal choice. The input capacitance can be
reduced if the LP2997 is placed close to the bulk capacitance from the output of the 1.8V DC-DC converter. For the
AVIN pin, a small 0.1uF ceramic capacitor is sufficient to
prevent excessive noise from coupling into the device.
very low ESR (typically less than 10 mΩ). However, some
dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the
typically low value of capacitance it is recommended to use
ceramic capacitors in parallel with another capacitor such as
an aluminum electrolytic. A dielectric of X5R or better is
recommended for all ceramic capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP
are available from several manufacturers. These offer a
large capacitance while maintaining a low ESR. These are
the best solution when size and performance are critical,
although their cost is typically higher than any other capacitors.
Thermal Dissipation
Since the LP2997 is a linear regulator any current flow from
will result in internal power dissipation generating heat.
V
TT
To prevent damaging the part from exceeding the maximum
allowable junction temperature, care should be taken to
derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (T
given the maximum ambient temperature (T
application and the maximum allowable junction temperature
).
(T
Jmax
T
Rmax=TJmax−TAmax
From this equation, the maximum power dissipation (P
of the part can be calculated:
P
Dmax=TRmax
The θJAof the LP2997 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θ
is 163˚C/W with the package mounted to a standard 8x4
2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to
151.2˚C/W by changing to a 3x4 board with 2 oz. copper that
is the JEDEC standard. Figure 1 shows how the θ
with airflow for the two boards mentioned.
) can be calculated
Rmax
Amax
/ θ
JA
of the SO-8
JA
)ofthe
Dmax
varies
JA
)
OUTPUT CAPACITOR
The LP2997 has been designed to be insensitive of output
capacitor size or ESR (Equivalent Series Resistance). This
allows the flexibility to use any capacitor desired. The choice
for output capacitor will be determined solely on the application and the requirements for load transient response of V
.
TT
As a general recommendation the output capacitor should
be sized above 100 µF with a low ESR for SSTL applications
with DDR-SDRAM. The value of ESR should be determined
by the maximum current spikes expected and the extent at
which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these
are highlighted below:
AL - It should be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher
frequency (100 kHz) should be used for the LP2997. To
improve the ESR several AL electrolytics can be combined in
parallel for an overall reduction. An important note to be
aware of is the extent at which the ESR will change over
temperature. Aluminum electrolytic capacitors can have their
ESR rapidly increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 µF range, but they have
excellent AC performance for bypassing noise because of
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20109407
FIGURE 1. θJAvs Airflow (SO-8)
Additional improvements can be made by the judicious use
of vias to connect the part and dissipate heat to an internal
ground plane. Using larger traces and more copper on the
Thermal Dissipation (Continued)
top side of the board can also help. With careful layout it is
possible to reduce the θ
shown in Figure 1
Optimizing the θ
and placing the LP2997 in a section of a
JA
board exposed to lower ambient temperature allows the part
to operate with higher power dissipation. The internal power
dissipation can be calculated by summing the three main
sources of loss: output current at V
sourcing, and quiescent current at AVIN and VDDQ. During
the active state (when shutdown is not held low) the total
internal power dissipation can be calculated from the following equations:
P
D=PAVIN+PVDDQ+PVTT
Where,
P
P
VDDQ=VVDDQ*IVDDQ=VVDDQ
further than the nominal values
JA
, either sinking or
TT
AVIN=IAVIN*VAVIN
2
xR
VDDQ
To calculate the maximum power dissipation at VTTboth
conditions at V
need to be examined, sinking and sourcing
TT
current. Although only one equation will add into the total,
cannot source and sink current simultaneously.
V
TT
P
VTT=VVTTxILOAD
=(V
P
VTT
PVIN-VVTT
(Sinking) or
)xI
LOAD
(Sourcing)
The power dissipation of the LP2997 can also be calculated
during the shutdown state. During this condition the output
will tri-state, therefore that term in the power equation
V
TT
will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be
the reduced quiescent current at AVIN and the constant
impedance that is seen at the VDDQ pin.
P
D=PAVIN+PVDDQ
P
AVIN=IAVINxVAVIN
P
VDDQ=VVDDQ*IVDDQ=VVDDQ
2
xR
VDDQ
LP2997
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Typical Application Circuits
LP2997
Several different application circuits have been shown to
illustrate some of the options that are possible in configuring
the LP2997. Graphs of the individual circuit performance can
be found in the Typical Performance Characteristics section
in the beginning of the datasheet. These curves illustrate
how the maximum output current is affected by changes in
AVIN and PVIN.
FIGURE 2. Recommended DDR-II Termination
Figure 2 shows the recommended circuit configuration for
DDR-II applications. The output stage is connected to the
1.8V rail and the AVIN pin can be connected to either a 2.5V,
3.3V or 5V rail.
20109413
This circuit permits termination in a minimum amount of
board space and component count. Capacitor selection can
be varied depending on the number of lines terminated and
the maximum load transient. However, with motherboards
and other applications where V
is distributed across a long
TT
plane it is advisable to use multiple bulk capacitors and
addition to high frequency decoupling. The bulk output capacitors should be situated at both ends of the V
plane for
TT
optimal placement. Large aluminum electrolytic capacitors
are used for their low ESR and low cost.
PCB Layout Considerations
1. The input capacitor for the power rail should be placed
as close as possible to the PVIN pin.
2. V
should be connected to the VTTtermination bus
SENSE
at the point where regulation is required. For motherboard applications an ideal location would be at the
center of the termination bus.
3. V
can be connected remotely to the V
DDQ
DDQ
rail input
at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side
copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the
internal ground plane will help. Additionally these can be
located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the V
SENSE
trace to
avoid noise pickup from switching I/O signals. A 0.1uF
ceramic capacitor located close to the
SENSE
can also be
used to filter any unwanted high frequency signal. This
can be an issue especially if long
6. V
should be bypassed with a 0.01 µF or 0.1 µF
REF
traces are used.
SENSE
ceramic capacitor for improved performance. This capacitor should be located as close as possible to the
pin.
V
REF
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Physical Dimensions inches (millimeters) unless otherwise noted
LP2997
8-Lead Small Outline Package (M8)
NS Package Number M08A
8-Lead PSOP Package (PSOP-8)
NS Package Number MRA08A
www.national.com11
LP2997 DDR-II Termination Regulator
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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