National Semiconductor LP2997 Technical data

LP2997 DDR-II Termination Regulator

June 2005

General Description

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a V load regulation and a V chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTToutput will tri-state providing a high impedance output, but, V remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

REF

pin to provide superior

SENSE

output as a reference for the

will

REF

Typical Application Circuit

Features

n Source and sink current n Low output voltage offset n No external resistors required n Linear topology n Suspend to Ram (STR) functionality n Low external component count n Thermal Shutdown n Available in SO-8, PSOP-8 packages

Applications

n DDR-II Termination Voltage n SSTL-18 Termination

20109418

Connection Diagrams

LP2997

Pin Descriptions

SO-8 Pin or PSOP-8 Pin

1 GND Ground

2SD

3 VSENSE Feedback pin for regulating V

4 VREF Buffered internal reference voltage of V

5 VDDQ Input for internal reference equal to V

6 AVIN Analog input pin

7 PVIN Power input pin

8 VTT Output voltage for connection to termination

PSOP-8 Layout

20109403

20109404

SO-8 Layout

Name Function

Shutdown

resistors

DDQ

Ordering Information

Order Number Package Type

LP2997M SO-8 M08A 95 Units per Rail

LP2997MX SO-8 M08A 2500 Units Tape and Reel

LP2997MR PSOP-8 MRA08A 95 Units Tape and Reel

LP2997MRX PSOP-8 MRA08A 2500 Units Tape and Reel

NSC Package

Drawing

Supplied As

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LP2997

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

PVIN, AVIN, VDDQ to GND No pin should exceed AVIN −0.3V to +6V

Storage Temp. Range −65˚C to +150˚C

Junction Temperature 150˚C

SO-8 Thermal Resistance (θJA) 151˚C/W

PSOP-8 Thermal Resistance (θ

) 43˚C/W

Minimum ESD Rating (Note 2) 1kV

Operating Range

Junction Temp. Range (Note 3) 0˚C to +125˚C

AVIN to GND 2.2V to 5.5V

Lead Temperature (Soldering, 10 sec) 260˚C

Electrical Characteristics Specifications with standard typeface are for T

type apply over the full Operating Temperature Range (T

= 0˚C to +125˚C) (Note 4). Unless otherwise specified,

= 25˚C and limits in boldface

AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V.

Symbol Parameter Conditions Min Typ Max Units

REF

VREF

Voltage PVIN = VDDQ = 1.7V

REF

PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V

REF

Output

= -30 to +30 µA 2.5 kΩ

REF

0.837

0.887

0.936

0.860

0.910

0.959

0.887

0.937

0.986

Impedance

Vos

TT/VTT

VTTOutput Voltage I

VTTOutput Voltage Offset (V

REF-VTT

)

Quiescent Current

=0A

OUT

PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V

=±0.5A (Note 7)

OUT

PVIN = VDDQ = 1.7V PVIN = VDDQ = 1.8V PVIN = VDDQ = 1.9V

=0A

OUT

= -0.5A

OUT

= +0.5A

OUT

= 0A (Note 5) 320 500

OUT

0.822

0.874

0.923

0.828

0.878

0.928

-25

0.856

0.908

0.957

0.856

0.908

0.957

0 0 0

0.887

0.939

0.988

0.890

0.940

0.990

25 25 25

(Note 5)

VDDQ

VDDQ Input Impedance 100 kΩ

Quiescent Current in

SD = 0V 115 150 µA

Shutdown (Note 5)

Q_SD

Shutdown Leakage

SD=0V 2 5 µA

Current

Minimum Shutdown

1.9 V

High Level

Maximum Shutdown

0.8 V

Low Level

SENSE

_HYS Thermal Shutdown

Input Current 13 nA

SENSE

Thermal Shutdown (Note 6) 165 Celsius

10 Celsius

Hysteresis

µA

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Electrical Characteristics Specifications with standard typeface are for T

apply over the full Operating Temperature Range (T

LP2997

AVIN = 2.5V, PVIN = 1.8V, VDDQ = 1.8V. (Continued)

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θ

junction to ambient with no heat sink.

Note 4: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 5: Quiescent current defined as the current flow into AVIN.

Note 6: The maximum allowable power dissipation is a function of the maximum junction temperature, T

the ambient temperature, T shutdown.

Note 7: V

load regulation is tested by using a 10 ms current pulse and measuring VTT.

. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal

= 0˚C to +125˚C) (Note 4). Unless otherwise specified,

J(MAX)

= 25˚C and limits in boldface type

, the junction to ambient thermal resistance, θJA, and

= 151.2˚ C/W

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