National Semiconductor LMX2525 Technical data

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LMX2525

LMX2525 PLLatinum Dual Frequency Synthesizer System with Integrated VCOs

April 2004

PLLatinum

™

Dual Frequency Synthesizer System

with Integrated VCOs

General Description

LMX2525 is a highly integrated, high performance, low power frequency synthesizer system optimized for dualband Japan PDC mobile handsets. Using a proprietary digital phase locked loop technique, LMX2525 generates very stable, low noise local oscillator signals for up and down conversion in wireless communications devices.

LMX2525 includes dual voltage controlled oscillators (VCOs) for the upper and lower Japan PDC frequency bands, a loop filter, and a fractional-N RF PLL based on a delta sigma modulator. In concert, these blocks form a closed loop RF synthesizer system. The RF synthesizer system supports two frequency bands: PDC1500 and PDC800.

Serial data is transferred to the device via a three-wire MICROWIRE interface (DATA, LE, CLK).

Operating supply voltage ranges from 2.5 V to 3.3 V. LMX2525 features low current consumption: 10 mA at 2.8 V when operating in the PDC800 mode.

LMX2525 is available in a 24-pin leadless leadframe package (LLP).

Features

n Small Size

5.0 mm X 4.0 mm X 0.75 mm 24-Pin LLP Package

n RF Synthesizer System

Two Integrated VCOs Integrated Loop Filter Low Spurious, Low Phase Noise Fractional-N RF PLL Based on 10-Bit Delta Sigma Modulator Frequency Resolution Down to 20 kHz

n Supports Various Reference Frequencies

12.6 MHz, 14.4 MHz, 25.2MHz, and 26.0 MHz

n Fast Lock Time: 300 µs n Low Current Consumption

10 mA at 2.8 V in PDC800 Mode

n 2.5 V to 3.3 V Operation n Digital Filtered Lock Detect Output n Hardware and Software Power Down Control

Applications

n Japan PDC Systems at 800 MHz and 1500 MHz

Frequency Bands.

Functional Block Diagram

20068907

FastLock™is a trademark of National Semiconductor Corporation.

TRI-STATE PLLatinum

is a registered trademark of National Semiconductor Corporation.

™

is a trademark of National Semiconductor Corporation.

Connection Diagram

LMX2525

Note: Analog ground connected through exposed die attached pad.

Pin Descriptions

Pin Number Name I/O Description

1 L1 — RF2 VCO tank pin. An external inductor is required between pins

2 L2 — RF2 VCO tank pin. An external inductor is required between pins

3 NC — Do not connect to any node on the printed circuit board.

4 NC — Do not connect to any node on the printed circuit board.

6 RF1out O RF output of RF1 VCO for PDC1500

8 RF2out O RF output of RF2 VCO for PDC800

10 V

11 GND — Ground for digital circuitry

12 V

13 LE I MICROWIRE Latch Enable

14 DATA I MICROWIRE Data

15 CLK I MICROWIRE Clock

16 CE I Chip enable control pin

17 BS I Band select control pin

18 LD O Lock detect pin

19 V

20 OSCin I Reference frequency input

21 GND — Ground for digital circuitry

22 V

23 GND — Ground for analog circuitry

24 V

24-Pin 5x4 LLP (LQ) Package

20068902

L1 and L2 to set the resonant frequency of RF2 VCO (PDC800).

— Supply voltage for RF analog circuitry

— Supply voltage for analog circuitry

— Supply voltage for digital circuitry

— Supply voltage for analog circuitry

— Supply voltage for RF analog circuitry

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Ordering Information

Part Number RF1 Min.

(MHz)

LMX2525LQX1321 1270.22 1394.95~1321 633.15 768.00 25251321 4500 units on

LMX2525LQ1321 1270.22 1394.95~1321 633.15 768.00 25251321 1000 units on

RF1 Max. (MHz)

RF1 Center (MHz)

RF2 Min. (MHz)

RF2 Max. (MHz)

Package Marking

Part Number Description

20068903

Typical Application Circuit (Note 1)

LMX2525

Supplied As

tape and reel

20068904

Note 1: Refer to RF2 VCO Tuning Range vs. External Inductance plot to aid in selecting the appropriate external inductance, PCB trace and L1, for the desired frequency range.

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Absolute Maximum Ratings (Notes 2, 3,

LMX2525

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Parameter Symbol Ratings Units

Supply Voltage V

Voltage on any pin to GND

Storage Temperature Range T

CC,VDD

STG

-0.5 to 3.6 V

-0.3 to VCC+ 0.3 V

-0.3 to V

-65 to 150 ˚C

+ 0.3 V

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Ambient Temperature T

Supply Voltage (to GND) V

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed.

Note 3: This device is a high performance RF integrated circuit with an ESD

rating

2 kV and is ESD sensitive. Handling and assembly of this device

should be done at ESD protected workstations.

Note 4: GND=0V.

CC,VDD

-30 25 85 ˚C

2.5 3.3 V

Electrical Characteristics (V

= 25 ˚C; Limits in boldface type apply over the operating temperature range from -20 ˚C ≤ TA≤ 75 ˚C unless other-

for T

= 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are

wise noted.)

Symbol Parameter Condition Min Typ Max Units

PARAMETERS

CC+IDD

Supply Current (Note 5) OB_CRL [1:0] = 10 10.6 12.0

12.3

OB_CRL [1:0] = 00 10.0 11.5

11.8

CC+IDD

Supply Current (Note 6) OB_CRL [1:0] = 10 15.0 16.5

16.8

OB_CRL [1:0] = 00 14.2 15.6

15.9

Power Down Current CE = LOW or

20 µA

RF_PD = 1

REFERENCE OSCILLATOR PARAMETERS

OSCin

Reference Oscillator Input Frequency (Note 7)

Supports 12.6, 14.4, 25.2 and 26.0 MHz.

12.6 14.4 26.0 MHz

Reference Oscillator Input Sensitivity 0.5 V

Vp-p

RF1 VCO FOR PDC1500

RF1out

Frequency Range (Note 8) RF1 VCO for PDC1500 1270.22 1394.95 MHz

Output Power OB_CRL [1:0] = 11 -5 -2 1 dBm

OB_CRL [1:0] = 10 -7 -4 -1 dBm

OB_CRL [1:0] = 01 -10 -7 -4 dBm

OB_CRL [1:0] = 00 -13 -10 -7 dBm

Lock Time Full frequency span within

each band in High Speed

300

(Note 9)

µs

Mode (HS = 1).

Between bands High Speed Mode (HS = 1).

Full frequency span within each band in Normal Mode (HS = 0). (Note 11)

Between bands in Normal Mode (HS = 0).

300

(Note 9)

500

(Note 9)

375

(Note 10)

500

(Note 9)

400

µs

(Note 10)

RMS Phase Error 1.3 degrees

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LMX2525

Electrical Characteristics (V

= 25 ˚C; Limits in boldface type apply over the operating temperature range from -20 ˚C ≤ TA≤ 75 ˚C unless otherwise

= 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for

noted.) (Continued)

Symbol Parameter Condition Min Typ Max Units

RF1 VCO FOR PDC1500

L(f)

RF1out

Phase Noise when RF1 VCO for PDC1500 is activated in Normal Mode (HS = 0).

25 kHz offset -95 -93

50 kHz offset -106 -103

dBc/Hz

-91

dBc/Hz

-101

100 kHz offset -115 -113

dBc/Hz

-111

1 MHz offset -135

dBc/Hz

-133

2ndHarmonic Suppression -25 dBc

Harmonic Suppression OB_CRL [1:0] = 11, 10, 01 -20 dBc

OB_CRL [1:0] = 00 -14

dBc

-11

Spurious Tones

≤ 25 kHz offset -45 dBc

25 kHz<offset ≤ 50 kHz -60 dBc

50 kHz<offset ≤ 100 kHz -69 dBc

offset>100 kHz -75 dBc

RF2 VCO FOR PDC800

RF2out

Frequency Range (Note 8) RF2 VCO for PDC800 633.15 768.00 MHz

Output Power OB_CRL [1:0] = 11 -6 -3 0 dBm

OB_CRL [1:0] = 10 -9 -6 -3 dBm

OB_CRL [1:0] = 01 -11 -8 -5 dBm

OB_CRL [1:0] = 00 -15 -12 -9 dBm

Lock Time Full frequency span within

each band in High Speed

300

(Note 9)

µs

Mode (HS = 1).

Between bands High Speed Mode (HS = 1).

Full frequency span within each band in Normal Mode (HS = 0). (Note 11)

Between bands in Normal Mode (HS = 0).

300

(Note 9)

500

(Note 9)

375

(Note 10)

500

(Note 9)

400

µs

(Note 10)

RMS Phase Error 1.3 degrees

L(f)

RF2out

Phase Noise when RF2 VCO for PDC800 is activated in Normal Mode (HS = 0).

25 kHz offset -95 -93

50 kHz offset -106 -103

dBc/Hz

-91

dBc/Hz

-101

100 kHz offset -115 -113

dBc/Hz

-111

1 MHz offset -135

dBc/Hz

-133

Harmonic Suppression -25 dBc

Harmonic Suppression OB_CRL[1:0] = 11, 10, 01 -20 dBc

OB_CRL[1:0] = 00 -14

dBc

-11

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Electrical Characteristics (V

= 25 ˚C; Limits in boldface type apply over the operating temperature range from -20 ˚C ≤ TA≤ 75 ˚C unless otherwise

noted.) (Continued)

LMX2525

= 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for

Symbol Parameter Condition Min Typ Max Units

RF2 VCO FOR PDC800

Spurious Tones

≤ 25 kHz offset -45 dBc

25 kHz<offset ≤ 50 kHz -60 dBc

50 kHz<offset ≤ 100 kHz -69 dBc

offset>100 kHz -75 dBc

DIGITAL INTERFACE (DATA, CLK, LE, LD, CE, BS)

High-Level Input Voltage 0.8 V

0.8 V

Low-Level Input Voltage -0.3 0.2 V

-0.3 0.2 V

High-Level Input Current -10 10 µA

Low-Level Input Current -10 10 µA

Input Capacitance 3 pF

Rise/Fall Time 30 ns

High-Level Output Voltage VCC- 0.4 V

- 0.4 V

Low-Level Output Voltage 0.4 V

Output Capacitance 5pF

MICROWIRE INTERFACE TIMING

CWH

CWL

Data to Clock Set Up Time 50 ns

Data to Clock Hold Time 10 ns

Clock Pulse Width HIGH 50 ns

Clock Pulse Width LOW 50 ns

Latch Enable LOW to Data Set Up

50 ns

Time

Note 5: RF PLL and VCO in PDC800 mode.

Note 6: RF PLL and VCO in PDC1500 mode.

Note 7: The reference frequency must be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National Semiconductor.

Note 8: For other frequency ranges, please contact National Semiconductor.

Note 9: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-1 kHz

of the final frequency.

Note 10: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-3 kHz of the final frequency.

Note 11: Lock time specification also applies to power up with MICROWIRE serial interface.

Note 12: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T

Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Clock to Latch Enable Set Up Time 50 ns

Latch Enable Pulse Width 50 ns

= 25 ˚C or correlated using

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