The LMX2470 is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. The device
is fabricated using National Semiconductor’s advanced BiCMOS process.
With delta-sigma architecture, fractional spur compensation
is achieved with noise shaping capability of the delta-sigma
modulator and the inherent low pass filtering of the PLL loop
filter. Fractional spurs at lower frequencies are pushed to
higher frequencies outside the loop bandwidth. Unlike analog compensation, the digital feedback techniques used in
the LMX2470 are highly resistant to changes in temperature
and variations in wafer processing. With delta-sigma architecture, the ability to push close in spur and phase noise
energy to higher frequencies is a direct function of the modulator order. The higher the order, the more this energy can be
spread to higher frequencies. The LMX2470 has a programmable modulator up to order four, which allows the designer
to select the optimum modulator order to fit the phase noise,
spur, and lock time requirements of the system.
Programming is fast and simple. Serial data is transferred
into the LMX2470 via a three line MICROWIRE interface
(Data, Clock, Load Enable). Nominal supply voltage is 2.5 V.
The LMX2470 features a typical current consumption of 4.1
mA at 2.5 V. The LMX2470 is available in a 24 lead 3.5 X 4.5
X 0.6 mm package.
Features
n Low in-band phase noise and low fractional spurs
n 12 bit or 22 bit selectable fractional modulus
n Up to 4th order programmable delta-sigma modulator
n Enhanced Anti-Cycle Slip Fastlock Circuitry
n Digital lock detect output
n Prescalers allow wide range of N values
RF PLL: 16/17/20/21
IF PLL: 8/9 or 16/17
n Crystal Reference Frequency up to 110 MHz
n On-chip crystal reference frequency doubler.
n Phase Comparison Frequency up to 30 MHz
n Hardware and software power-down control
n Ultra low consumption: I
= 4.1 mA (typical)
CC
Applications
n Cellular Phones and Base Stations
CDMA, WCDMA, GSM/GPRS, TDMA, EDGE, PDC
n Applications requiring fine frequency resolution
n Satellite and Cable TV Tuners
n WLAN Standards
5FinRFIRF prescaler input. Small signal input from the VCO.
6FinRF*IRF prescaler complimentary input. For single-ended operation, a bypass capacitor should
7VccRFRF PLL power supply voltage input. Must be equal to VccIF . May range from 2.25V to
8ENIChip enable input. High impedance CMOS input. When EN is high, the chip is powered
9ENOSCIThis pin should be grounded for normal operation.
10CLKIMICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is
11DATAIMICROWIRE Data. High impedance binary serial data input.
12LEMICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift
13Ftest/LDOTest frequency output / Lock Detect
14VddIF-Digital power supply for IF PLL
15VccIF-IF power supply voltage input. Must be equal to VccRF. Input may range from 2.25 V to
16GND-Ground for RF PLL digital circuitry.
17FinIFIIF prescaler input. Small signal input from the VCO.
18GND-Digital ground for IF PLL
19CPoutIFOIF PLL charge pump output
20FLoutIFOIF Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
21OSCout*I/OComplementary reference input or oscillator output.
22OSCinIReference input
23VddRF-Digital power supply for RF PLL
24FLoutRFORF Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
Pin
Name
24-Pin CSP (SLE) Package
20059322
I/OPin Description
be placed as close as possible to this pin and be connected directly to the ground plane.
2.75V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
up, otherwise it is powered down.
clocked into the 24 bit shift register on the rising edge.
registers is loaded into the internal latches when LE goes HIGH
2.75 V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
www.national.com2
Absolute Maximum Ratings (Notes 1, 2)
LMX2470
ParameterSymbol
Power Supply VoltageV
V
Voltage on any pin with GND =V
=0VV
SS
Storage Temperature RangeT
Lead Temperature (Solder 4 sec.)T
MinTypMax
CC
DD
i
s
L
-0.33.0V
V
CC
-0.3VCC+ 0.3V
-65+150˚C
Value
Units
V
CC
+260˚C
V
Recommended Operating Conditions
ParameterSymbol
Power Supply Voltage (Note 1)V
Operating TemperatureT
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions" indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Note also that these maximum ratings imply that the voltage at all the power
supply pins of VccRF, VccIF, VddRF, and VddIF are the same. V
Note 2: This Device is a high performance RF integrated circuit with an ESD rating
be done at ESD-free workstations.
Electrical Characteristics (V
CC
V
DD
A
will be used to refer to the voltage at these pins.
Applies to both low and high
current modes-209dBc/Hz
(Note 3)
Note 3: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(f
measured at an offset frequency, f, ina1HzBandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. The offset chosen was 4 KHz.
) where L(f) is defined as the single side band phase noise