National Semiconductor LMX2370, LMX2371, LMX2372 Technical data
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LMX2370/LMX2371/LMX2372 PLLatinum Dual Frequency Synthesizer for RF Personal
Communications
LMX2370/LMX2371/LMX2372
PLLatinum
™
Dual Frequency Synthesizer for RF
Personal Communications
LMX2370 2.5 GHz/1.2 GHz
LMX2371 2.0 GHz/1.2 GHz
LMX2372 1.2 GHz/1.2 GHz
General Description
The LMX237X family of monolithic, integrated dual frequency synthesizers, including prescalers, is designed to be
used as a first and second local oscillator for dual mode or
dual conversion transceivers. It is fabricated using National’s
0.5u ABiCV silicon BiCMOS process. The LMX237X contains two dual modulus prescalers. A 32/33 or a 16/17
prescaler can be selected for the 2.5 GHz and 2.0 GHz RF
synthesizers with the 16/17 prescaler rated for input frequencies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be selected for the 1.2 GHz RF synthesizers with the 8/9 prescaler
rated for input frequencies below 550 MHz. Using a digital
phase locked loop technique, the LMX237X can generate
very stable, low noise control signals for UHF and VHF voltage controlled oscillators (VCO’s). Serial data is transferred
into the LMX237X via a 1.8V three wire interface (Data, Enable, Clock) compatible with low voltage baseband processors. Supply voltage can range from 2.7V to 5.5V. The
LMX237X family features very low current consumption typically: LMX2370 - 6.0 mA
LMX2372 - 4.0 mA
@
3V, LMX2371 - 5.0 mA@3V,
@
3V.
PRELIMINARY
March 1999
The LMX237X are available in a 24-pad chip scale (CSP) or
a 20-pin TSSOP surface mount plastic package.
Features
n 2.7V–5.5V operation
n Ultra low current consumption
n Low phase detector noise floor
n Low voltage MICROWIRE
n Low prescaler values
n Selectable charge pump current levels
n Selectable FastLock
n Enhanced ESD protection
n Small 24 pad chip scale package (3.5 x 4.5 x 1.0 mm)
32/33
16/17
8/9
@
@
fIN≤ 2.5 GHz
@
fIN≤ 1.2 GHz
fIN≤ 550 MHz
™
interface (1.8V up to VCC)
™
mode
Applications
n Portable wireless communications (PCS/PCN, cordless)
n Dual mode cellular telephone systems
n Spread spectrum communication systems (CDMA)
n Cable TV tuners (CATV)
Functional Block Diagram
DS101026-1
FastLock™, PLLatinum™and MICROWIRE™are trademarks of National Semiconductor Corporation.
®
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS101026 www.national.com
Connection Diagrams
TSSOP 20-Pin Package
DS101026-2
CSP 24-Pin Package
Top View
Order Number LMX2370TM, LMX2370TMX,
LMX2371TM, LMX2371TMX,
LMX2372TM or LMX2372TMX
See NS Package Number MTC20
Top View
DS101026-3
Order Number LMX2370SLBX,
LMX2371SLBX or LMX2372SLBX
See NS Package Number SLB24A
Pin Descriptions
Pin No.
24-Pin
CSP
20-Pin
TSSOP
24 1 V
2 2 Vp1 — Power supply for Main charge pump. Must be ≥ V
33CP
4 4 GND — Ground for Main digital circuitry.
55f
66f
7 7 GND — Ground for Main analog circuitry.
8 8 OSC
10 9 GND — Ground for Aux digital, MICROWIRE, FoLD, and oscillator circuits.
11 10 Fo/LD O Multiplexed output of the Main/Aux programmable or reference dividers,
12 11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on
14 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control
15 13 LE I Load enable. High impedance CMOS input. When LE goes HIGH, data stored in
Pin
Name
CC
IN
IN
I/O Description
1 — Power supply voltage input for RF analog and RF digital circuits. Input may range
from 2.7V to 5.5V. V
close as possible to this pin and be connected directly to the ground plane.
1 O Internal Main charge pump output. For connection to a loop filter for driving the
o
input of an external VCO.
1 must equal VCC2. Bypass capacitors should be placed as
CC
.
CC
1 I Main prescaler input. Small signal input from the VCO.
1b I Main prescaler complementary input. For single ended operation, a bypass
capacitor should be placed as close as possible to this pin and be connected
directly to the ground plane.
I Oscillator input. The input has a VCC/2 input threshold and can be driven from an
in
external CMOS or TTL logic gate.
Main/Auxiliary lock detect signals and Fastlock mode. CMOS output
(see
Programmable Modes in the Datasheet).
the rising edge, into the 22-bit shift register.
bits. High impedance CMOS input.
the shift registers is loaded into one of the 4 appropriate latches (control bit
dependent).
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Pin Descriptions (Continued)
24-Pin
CSP
Pin No.
20-Pin
TSSOP
Pin
Name
I/O Description
16 14 Vµc — Power supply for MICROWIRE circuitry. Must be ≤ V
same supply level as µprocessor or baseband controller to enable programming at
low voltages.
17 15 GND — Ground for Aux analog circuitry.
18 16 f
2 I Auxiliary prescaler input. Small signal input from the VCO.
IN
19 17 GND — Ground for Aux digital, MICROWIRE, FoLD, and oscillator.
20 18 CP
22 19 Vp2 — Power supply for Aux charge pump. Must be ≥ V
23 20 V
2 O Aux internal charge pump output. For connection to a loop filter for driving the
o
2 — Power supply voltage input for Aux analog, Aux digital, FoLD, and oscillator
CC
input of an external VCO.
.
CC
circuits. Input may range from 2.7V to 5.5V. V
capacitors should be placed as close as possible to this pin and be connected
2 must equal VCC1. Bypass
CC
directly to the ground plane.
1, 9,
— NC — No Connect
13, 21
Block Diagram
. Typically connected to
CC
DS101026-4
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
1 −0.3V to 6.5V
V
CC
2 −0.3V to 6.5V
V
CC
Vp1 −0.3V to 6.5V
Vp2 −0.3V to 6.5V
Vµc −0.3V to 6.5V
Voltage on any pin with
GND=0V (V
Storage Temperature Range (T
Lead Temperature (solder, 4 sec.) (T
ESD - Human Body Model (Note 2) TBD
Electrical Characteristics (V
GENERAL Value
Symbol Parameter Conditions Min Typ Max
I
CC
) −0.3V to VCC+0.3V
I
Power Supply
Current
) −65˚C to +150˚C
S
) +260˚C
L
=Vp=
CC
LMX2370 Main=On, Aux=On 6 8.5 mA
LMX2371 Main=On, Aux=On 5 7.5 mA
Vµc=3.0V; −40˚C
Recommended Operating
Conditions
Power Supply Voltage
1 2.7V to 5.5V
V
CC
2 2.7V to 5.5V
V
CC
1–VCC2 −0.2V to 0.2V
V
CC
Vp1 V
Vp2 V
Vµc 1.72V to V
Operating Temperature (TA) −40˚C to +85˚C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance
limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should only be done at ESD
free workstations.
Note 3: V
CC
<
(Note 3)
is defined as V
<
T
A
=
V
CC
85˚C except as specified).
1=VCC2.
CC
CC
CC
to 5.5V
to 5.5V
Unit
LMX2372 Main=On, Aux=On 4 6.0 mA
I
CC-PWDN
f
1 Main PLL
IN
Power Down Current EN_Main, EN_Aux=01550µA
Operating
Frequency
LMX2370
/71/72
LMX2370 P=32/33 1.2 2.5 GHz
LMX2371 P = 32/33 1.2 2.0 GHz
Aux Only
2 3.25 mA
P = 16/17 45 1200 MHz
P = 16/17 45 1200 MHz
LMX2372 P = 16/17 45 1200 MHz
P = 8/9 45 550 MHz
f
2 Auxiliary PLL Operating
IN
Zf
Main Main PLL Input Impedance RF On, f
IN
Zf
Aux Aux Input Impedance f
IN
Frequency
P = 16/17 45 1200 MHz
P = 8/9 45 550 MHz
=
1800 MHz TBD Ω
IN
RF Off, f
IN
=
1800 MHz TBD Ω
IN
=
120 MHz TBD Ω
fφ Phase Detector Frequency 10 MHz
Pf
1, PfIN2 RF Input Sensitivity 2.7 ≤ VCC≤ 3.6V −15 0 dBm
IN
OSCILLATOR INPUT Value
Symbol Parameter Conditions Min Typ Max
OSC
in
OSC OSC Input Impedance OSC On, Freq = 10 MHz TBD kΩ
Z
IN
Reference Oscillator Input
Operating Frequency
3.6 ≤ V
≤ 5.5V −10 0 dBm
CC
2 50 MHz
Unit
OSC Off, Freq = 10 MHz TBD kΩ
V
OSC
I
IH
I
IL
Oscillator Input Sensitivity OSC
in
0.5 V
V
CC
OSCinInput Current VIH=VCC= 5.5V 100 µA
OSCinInput Current VIL=0,VCC= 5.5V −100 µA
PP
CC
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Electrical Characteristics (V
CC
=Vp=
Vµc=3.0V; −40˚C
<
<
T
85˚C except as specified). (Continued)
A
CHARGE PUMP Value
Symbol Parameter Conditions Min Typ Max
ICP
o-source
ICP
o-sink
ICP
o-source
ICP
o-sink
ICP
o-TRI
ICP
o-sink
ICP
o-source
vs
ICP
o
VCP
o
vs TACP Current vs Temperature VCP
ICP
o
Main and Auxiliary Charge
Pump Output Current (Note 4)
Charge Pump TRI-STATE
Current
vs
CP Sink vs Source Mismatch VCP
CP Current vs Voltage 0.5 ≤ VCPo≤ Vp − 0.5, T
®
=
VCP
o
=
VCP
o
=
VCP
o
=
VCP
o
0.5 ≤ VCP
<
−40˚C
=
o
=
o
Vp/2, ICP
Vp/2, ICP
Vp/2, ICP
Vp/2, ICP
≤ Vp − 0.5,
o
<
T
85˚C
A
=
Vp/2, T
A
Vp/2, −40˚C
_4X=0 1.0 mA
o
_4X=0 −1.0 mA
o
_4X=1 4.0 mA
o
_4X=1 −4.0 mA
o
−2.5 0.1 2.5 nA
25˚C
=
25˚C
A
<
<
T
85˚C 8
A
310
815
DIGITAL INTERFACE (DATA, CLOCK, LE) Value
Symbol Parameter Conditions Min Typ Max
V
IH
V
IL
I
IH
I
IL
V
OL
High-Level Input Voltage Vµc=1.72V to 5.5V 0.8 Vµc V
Low-Level Input Voltage Vµc=1.72V to 5.5V 0.2 Vµc V
High-Level Input Current V
Low-Level Input Current V
Low-Level Output Current I
=
Vµc=5.5V −1.0 1.0 µA
IH
=
0, Vµc=5.5V −1.0 1.0 µA
IL
OL
5)
=
1.0 mA, V
EXT
=
1.8V (Note
0.1 0.4 V
MICROWIRE TIMING Value
Symbol Parameter Conditions Min Typ Max
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Note 4: Main and Auxiliary Charge Pump magnitude are controlled by Main_ICPo_4X and Aux_ICPo_4X bits respectively.
Note 5: Lock Detect open drain output only pulled up to V
Data to Clock Setup Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 20 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Setup
Time
See Data Input Timing
50 ns
Load Enable Pulse Width See Data Input Timing 50 ns
. Typically V
EXT
EXT
=
.
V
CC
Unit
%
%
%
Unit
Unit
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer
such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter.The frequency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to
obtain a comparison reference frequency. This reference signal (
and compared with the feedback signal (
phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control
f
), which is obtained by dividing the VCO frequency down by way of the N-counter.The
N
voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback
signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency
will be N times that of the comparison frequency, where N is the integer divide ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSC
OSC
can operate up to 50 MHz with input sensitivity of 0.5 VPP. The OSCinpin drives both the Main R-counter and the Auxiliary
in
R-counter.The input has a V
is connected to the output of a crystal oscillator.
/2 input threshold that can be driven from an external CMOS or TTL logic gate. Typically, the OSC
CC
1.2 REFERENCE DIVIDERS (R-COUNTERS)
The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.
Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.
f
) is then presented to the input of a phase/frequency detector
R
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pin.
in
in
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