National Semiconductor LMX2354 Technical data

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LMX2354
PLLatinum Fractional N RF/ Integer N IF Dual Low Power
Frequency Synthesizer
LMX2354 2.5 GHz/550 MHz

LMX2354 PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer

August 2001

General Description

The LMX2354 is part of a family of monolithic integrated
fractional N/Integer N frequency synthesizers designed to be
used in a local oscillatorsubsystem for a radio transceiver. It
is fabricated using National’s 0.5 µ ABiC V silicon BiCMOS
process. The LMX2354 contains quadruple modulus pres­calers along with modulo 15 or 16 fractional compensation
circuitry in theRF divider. The LMX2354 provides a continu­ous divide ratio of 80 to 32767 in 16/17/20/21
(1.2 GHz–2.5 GHz) fractional mode and 40 to 16383 in
8/9/12/13 (550 MHz–1.2 GHz) fractional mode. The IF cir­cuitry for the LMX2354 contains an 8/9prescaler, and is fully
programmable. Using a fractional N phase locked loop tech­nique, the LMX2354 can generate very stable low noise
control signals for UHF and VHF voltage controlled oscilla­tors (VCOs).

For the RF PLL, a highly flexible 16 level programmable
charge pump supplies output current magnitudes from 100
µA to 1.6 mA. Two uncommitted CMOS outputs can be used
to provide external control signals, or configured to FastLock
mode. Serial dataistransferredintotheLMX2354 via a three
wire interface (Data, LE, Clock). Supply voltage can range
from 2.7V to 5.5V. The LMX2354 family features very low
current consumption; typically LMX2354 (2.5 GHz) — 7.0
mA. The LMX2354 are available in a 24-pin TSSOP surface
mount plastic package and 24-pin CSP.

Features

n Pin compatible/functional equivalent to the LMX2350
n Enhanced Low Noise Fractional Engine
n 2.7V to 5.5V operation
n Low current consumption

LMX2354: I

n Programmable or logical power down mode:

I

= 5 µA typical at 3V

CC

n Modulo 15 or 16 fractional RF N divider supports ratios

of 1, 2, 3, 4, 5, 8, 15, or 16

n Programmable charge pump current levels

RF 100 µA to 1.6 mA in 100 µA steps
IF 100 µA or 800 µA

n Digital filtered lock detect
n Available in 24-pin TSSOP and 24-pin CSP

= 7 mA typical at 3V

CC

Applications

n Portable wireless communications (PCS/PCN, cordless)
n Dual mode cellular telephone systems
n Zero blind slot TDMA systems
n Spread spectrum communication systems (CDMA)
n Cable TV Tuners (CATV)

Functional Block Diagram

20004801

© 2001 National Semiconductor Corporation DS200048 www.national.com

Connection Diagrams

LMX2354

Order Number LMX2354TM or LMX2355TM

20004802

See NS Package Number MTC24

Order Number LMX2354SLB or LMX2355SLB

20004822

See NS Package Number SLB

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Pin Descriptions

LMX2354

Pin No. for

TSSOP

Package

Pin No. for

CSP

Package

Pin

Name I/O Description

1 24 OUT0 O Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
21V

CC

RF

— RF PLL power supply voltage input. Must be equal to VccIF. May range from

2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this

pin and be connected directly to the ground plane.
32V
43CP

P

RF

o

RF

— Power supply for RF charge pump. Must be ≥ V

O RF charge pump output. Connected to a loop filter for driving the control input

and V

CC

RF

.

CC

IF

of an external VCO.
5 4 GND — Ground for RF PLL digital circuitry.
6 5 fin RF I RF prescaler input. Small signal input from the VCO.
7 6 fin RF

I RF prescaler complimentary input. A bypass capacitor should be placed as

close as possible to this pin and be connected directly to the ground plane.
8 7 GND — Ground for RF PLL analog circuitry.
9 8 OSC

RF

I Dual mode oscillator output or RF R counter input. Has a VCC/2 input threshold

when configured as an input and can be driven from an external CMOS or TTL

logic gate.

10 9 OSC

IF

I Oscillator input which can be configured to drive both the IF and RF R counter

inputs or only the IF R counter depending on the state of the OSC

programming bit. (See functional description 1.1 and programming description

3.1.)

11 10 Fo/LD O Multiplexed output of N or R divider and RF/IF lock detect. CMOS output. (See

programming description 3.1.5.)

12 11 RF_EN I RF PLL Enable. Powers down RF N and R counters, prescaler, and

®

TRI-STATE

charge pump output when LOW. Bringing RF_EN high powers up

RF PLL depending on the state of RF_CTL_WORD. (See functional description

1.9.)

13 12 IF_EN I IF PLL Enable. Powers down IF N and R counters, prescaler, and TRI-STATE

charge pump output when LOW. Bringing IF_EN high powers up IF PLL

depending on the state of IF_CTL_WORD. (See functional description 1.9.)

14 13 CLOCK I High impedance CMOS Clock input. Data for the various counters is clocked

into the 24-bit shift register on the rising edge.

15 14 DATA I Binary serial data input. Data entered MSB first. The last two bits are the

control bits. High impedance CMOS input.

16 15 LE I Load Enable high impedance CMOS input. Data stored in the shift registers is

loaded into one of the 4 internal latches when LE goes HIGH. (See functional

description 1.7.)

17 16 GND — Ground for IF analog circuitry.
18 17 fin IF

I IF prescaler complimentary input. A bypass capacitor should be placed as

close as possible to this pin and be connected directly to the ground plane.

19 18 fin IF I IF prescaler input. Small signal input from the VCO.
20 19 GND — Ground for IF digital circuitry.
21 20 CPo

IF

O IF charge pump output. For connection to a loop filter for driving the input of an

external VCO.

22 21 V
23 22 V

PIF
CC

IF

— Power supply for IF charge pump. Must be ≥ V

CC

— IF power supply voltage input. Must be equal to V

RF

CC

and V

RF

.

CC

IF

. Input may range from

2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this

pin and be connected directly to the ground plane.

24 23 OUT1 O Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.

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Absolute Maximum Ratings (Notes 1, 2)

LMX2354

Power Supply Voltage V

Parameter Symbol

CC

RF

V

CC

IF

Vp

RF

Vp

IF

Min Typ Max

−0.3 6.5 V

−0.3 6.5 V

−0.3 6.5 V

−0.3 6.5 V

Voltage on any pin with GND = 0V Vi −0.3 V

Value

+ 0.3 V

CC

Storage Temperature Range Ts −65 +150 C˚
Lead Temperature (Solder 4 sec.) T

L

+260 C˚

Recommended Operating Conditions

Parameter Symbol

Power Supply Voltage V

Operating Temperature T

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended tobe functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.

Note 2: This Device is a high performance RF integrated circuit with an ESD rating
be done at ESD-free workstations.

CC

RF

V

CC

IF

V

pRF

V

pIF

A

Min Typ Max

2.7 5.5 V

V

CC

RF

V

CC

V

CC

−40 +85 ˚C

<

2kV and is ESD sensitive. Handling and assembly of this device should only

Value

V

CC

RF

5.5 V

5.5 V

Units

Units

V

Electrical Characteristics (V

All min/max specifications are guaranteed by design, or test, or statistical methods.

=V

=V

=V

cc

cc

RF

P

IF

RF

= 3.0V; −40˚C<T

P

IF

Symbol Parameter Conditions

<

+85˚C except as specified)

A

Value

Min Typ Max

Units

GENERAL

I

CC

Power Supply Current RF and IF 6.0 8.5 mA

IF Only 1.1 2.0 mA

I

CC-PWDN

f

RF RF Operating Frequency 0.5 2.5 GHz

in

f

IF IF Operating Frequency 10 550 MHz

in

f

OSC

Power Down Current RF_EN = IF_EN = LOW 20 50 µA

Oscillator Frequency No load on OSC

RF

2 50 MHz
fφ Phase Detector Frequency RF and IF 10 MHz
Pf

in RF

Pf

in IF

V

OSC

RF Input Sensitivity VCC= 3.0V −15 0 dBm

V

= 5.0V −10 0 dBm

CC

IF Input Sensitivity 2.7V ≤ VCC≤ 5.5V −10 0 dBm
Oscillator Sensitivity OSCIF, OSC

RF

0.5 V

CC

V

PP

CHARGE PUMP

ICPo-

ICPo-

ICPo-

ICPo-

source RF

sink RF

source RF

sink RF

RF Charge Pump Output
Current (see Programming
Description 3.2.2)

VCPo Vp/2, RF_CP_WORD =
0000

VCPo = Vp/2, RF_CP_WORD =
0000

VCPo = Vp/2, RF_CP_WORD =
1111

VCPo = Vp/2, RF_CP_WORD =
1111

−100 µA

100 µA

−1.6 mA

1.6 mA

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LMX2354

Electrical Characteristics (V

=V

=V

=V

cc

cc

RF

P

IF

RF

= 3.0V; −40˚C<T

P

IF

<

A

All min/max specifications are guaranteed by design, or test, or statistical methods. (Continued)

Symbol Parameter Conditions

ICPo-

source IF

ICPo-

sink IF

ICPo-

source IF

ICPo-

sink IF

ICPo-

Tri

RF ICPo­vs. ICPo-

sink
source

ICPo vs. VCPo CP Current vs. Voltage

ICPo vs. T CP Current vs

V

CP

IF Charge Pump Output
Current (see Programming
Description 3.1.4)

Charge Pump TRI-STATE
Current

RF CP Sink vs. Source
Mismatch

Variation

Temperature
Charge Pump Output

Voltage (RF only)

VCPo = Vp/2, CP_GAIN_8 = 0 −100 µA
VCPo = Vp/2, CP_GAIN_8 = 0 100 µA
VCPo = Vp/2, CP_GAIN_8 = 1 −800 µA
VCPo = Vp/2, CP_GAIN_8 = 1 800 µA

0.5 ≤ VCPo ≤ Vp −0.5

<

−40˚C

T

A

VCPo = Vp/2 TA= 25˚C
RF ICPo=900µA − 1.6mA

0.5 ≤ VCPo ≤ Vp −0.5
= 25˚C RF ICPo

T

A

VCPo = Vp/2

<

−40˚C

T

A

2.7V ≤ VCC≤ 3.3V, Doubler

Enabled

<

+85˚C

<

+85˚C RF ICPo

Min Typ Max

−2.5 2.5 nA

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

V

IH

V

IL

I

IL

I

IH

I

IH

I

IL

V

OH

High-level Input Voltage (Note 3) 0.8 V

CC

Low-level Input Voltage (Note 3) 0.2 V
Low-level Input Current VIL=0,VCC= 5.5V, (Note 3) −1.0 1.0 µA
High-level Input Current VIH=VCC= 5.5V, (Note 3) −1.0 1.0 µA
Oscillator Input Current VIH=VCC= 5.5V 100 µA
Oscillator Input Current VIL=0,VCC= 5.5V −100 µA
High-level Output Voltage IOH= −500 µA V

CC

−0.4

V

OL

High-level Output Voltage IOL= 500 µA 0.4 V

MICROWIRE TIMING

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

EW

Note 3: except fIN, OSCIFand OSC

Data to Clock Setup Time See Data Input Timing 50 ns
Data to Clock Hold Time See Data Input Timing 10 ns
Clock Pulse Width High See Data Input Timing 50 ns
Clock Pulse Width Low See Data Input Timing 50 ns
Clock to Load Enable Set

Up Time

See Data Input Timing

50 ns

Load Enable Pulse Width See Data Input Timing 50 ns

RF

+85˚C except as specified)

Value

Units

3.5 10 %

510%

8%

2*V

CC

−0.5

V

V

CC

V

V

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Charge Pump Current Specification Definitions

LMX2354

I1 = CP sink current at VDo=Vp−∆V
I2 = CP sink current at V
I3 = CP sink current at V
I4 = CP source current at V
I5 = CP source current at V
I6 = CP source current at V

Do
Do

= Vp/2
= ∆V

=Vp−∆V

Do

= Vp/2

Do

= ∆V

Do

∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
Note 4: I

||6|}]

Note 5: I
Note 6: I

25˚C|]/||5@25˚C|*100%

vs VDo= Charge Pump Output Current magnitude variation vs Voltage = [1⁄

Do

*

100%

vs I

Do-sink
Do

Do-source

vs TA= Charge Pump Output Current magnitude variation vs Temperature = [||2@temp| − ||2@25˚C|]/||2@25˚C|*100% and [||5@temp| − ||5

= Charge Pump Output Current Sink vs Source Mismatch = [||2| − ||5|]/[1⁄

*

2

{||1| − ||3|}]/[1⁄

20004823

and ground. Typical values are between 0.5V and 1.0V.

CC

*

2

{||1| + ||3|}]*100% and [1⁄

*

2

{||2| + ||5|}]*100%

*

2

{||4| − ||6|}]/[1⁄

*

2

{||4| +

@

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RF Sensitivity Test Block Diagram

LMX2354

Note: N = 10,000 R = 50 P = 16
Note: Sensitivity limit is reached when the error of the divided RF output, F

Typical Performance Characteristics

ICCvs V

LMX2354

Charge Pump Current vs CPOVoltage

RF_CP_WORD = 0000 and 0111

IF CP_GAIN_8 = 0 and 1

CC

20004825 20004827

LD, is ≥ 1 Hz.

o

TRI-STATE vs

I

CPO

CP

Voltage

O

Charge Pump Current vs CP

RF_CP_WORD = 0011 and 1111

Voltage

O

20004824

20004828

20004829

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