National Semiconductor LMX2353 Technical data

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LMX2353 PLLatinum Fractional N Single 2.5 GHz Frequency Synthesizer

LMX2353 PLLatinum

™

Fractional N Single 2.5 GHz Frequency

Synthesizer

General Description

The LMX2353 is a monolithic integrated fractional N frequency synthesizer, designed to be used in a local oscillator subsystem for a radio transceiver. It is fabricated using National’s 0.5µABiCVsiliconBiCMOS process. The LMX2353 contains dual modulus prescalers along with modulo 15 or 16 fractional compensation circuitry in the N divider. A 16/17 or 32/33 prescale ratio can be selected for the LMX2353. Using a fractional N phase locked loop technique, the LMX2353 can generate very stable low noise control signals for UHF and VHF voltage controlled oscillators (VCO’s).

The LMX2353 has a highly flexible 16 level programmable charge pump supplies output current magnitudes from 100 µAto 1.6 mA. Serial data is transferred into the LMX2353 via a three wire interface (Data, LE, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2353 features very low current consumption; typically 4.5 mAat 3.0V. The LMX2353 is available in a 16-pin TSSOP or a 16-pad CSP surface mount plastic package.

Functional Block Diagram

PRELIMINARY

June 1999

Features

n 2.7V – 5.5V operation n Low Current Consumption

= 4.5 mA typ@VCC= 3.0V

n Programmable or Logical Power Down Mode

=5µAtyp@VCC= 3.0V

n Modulo 15 or 16 fractional N divider

Supports ratios of 1, 2, 3, 4, 5, 8, 15, or 16

n Programmable charge pump current levels

100 µA to 1.6 mA in 100 µA steps

n Digital Filtered Lock Detect

Applications

n Portable wireless communications (PCS/PCN, cordless) n Zero blind slot TDMA systems n Cellular and Cordless telephone systems n Spread spectrum communication systems (CDMA)

DS101124-1

MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

Connection Diagrams

DS101124-2

TOP VIEW

Order Number LMX2353TM or

LMX2353TMX

Order Number LMX2353SLBX

TOP VIEW

See NS Package Number SLB16A

DS101124-3

See NS Package Number MTC16

Pin Description

Pin No.

CSP TSSOP

16 1 V

12CP

2 3 GND — Ground for PLL digital circuitry. 34f 45f

5 6 GND — Ground for PLL analog circuitry. 6 7 OSC

78F 8 9 CE I PLL Enable. Powers down N and R counters, prescalers, and TRI-STATE

9 10 CLK I High impedance CMOS Clock input. Data for the various counters is clocked into

10 11 DATA I Binary serial data input. Data entered MSB first. The last two bits are the control

11 12 LE I Load enable high impedance CMOS input. Data stored in the shift registers is

12 13 GND — Ground. 13 14 V

14 15 OUT1 — Programmable CMOS output. Level of the output is controlled by F2[18] bit. 15 16 OUT0 — Programmable CMOS output. Level of the output is controlled by F2[17] bit.

Name

INB

I/O Description

— Power supply for charge pump. Must be ≥ VCC.

O Charge pump output. Connected to a loop filter for driving the control input of an

external VCO.

I RF prescaler input. Small signal input from the VCO. I RF prescaler complimentary input. A bypass capacitor should be placed as close

as possible to this pin and be connected directly to the ground plane.

I Oscillator input. A CMOS inverting gate input. The input has a VCC/2 input

threshold and can be driven from an external CMOS or TTL logic gate.

LD O Multiplexed output of N or R divider and lock detect. CMOS output.

pump output when LOW. Bringing CE high powers up PLL depending on the state of CTL_WORD.

the 24-bit shift register on the rising edge.

bits. High impedance CMOS input.

loaded into one of the 4 internal latches when LE goes HIGH.

— PLL power supply voltage input. May range from 2.7V to 5.5V. Bypass capacitors

should be placed as close as possible to this pin and be connected directly to the ground plane.

charge

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Power Supply Voltage

Vp −0.3V to 6.5V

Voltage on any pin with

GND=0V (V Storage Temperature Range (T Lead Temperature (solder, 4 sec.) (T

) −0.3V to VCC+0.3V

) −65˚C to +150˚C

ESD - Human Body Model (Note 2) 2 kV

Electrical Characteristics (V

Symbol Parameter Conditions

−0.3V to 6.5V

) +260˚C

=Vp=

3.0V; −40˚C

Recommended Operating Conditions

Power Supply Voltage

Vp V

Operating Temperature (T

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.

Note 2: This device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done at ESD free workstations.

85˚C except as specified).

) −40˚C to +85˚C

Value

Min Typ Max

2.7V to 5.5V to 5.5V

Unit

GENERAL

CC-PWDN

OSC

Power Supply Current 4.5 mA Power Down Current CE = LOW 5 µA RF Operating Frequency (Note 3) 0.5 2.5 GHz

Oscillator Frequency (Note 3) 2 50 MHz fφ Phase Detector Frequency 10 MHz Pf

OSC

RF Input Sensitivity VCC= 3.0V −15 0 dBm

= 5.0V −10 0 dBm

Oscillator Sensitivity OSC

0.5 V

CHARGE PUMP

ICP

o-source

ICP

o-sink

ICP

o-source

ICP

o-sink

ICP

o-TRI

ICP

o-sink

ICP

o-source

ICP

VCP

vs T CP Current vs Temperature VCP

ICP

Charge Pump Output Current VCP

Charge Pump TRI-STATE

Current

CP Sink vs Source Mismatch VCP

CP Current vs Voltage 0.5 ≤ VCPo≤ Vp − 0.5, T

Vp/2,

CP_WORD = 0000

VCP

Vp/2,

CP_WORD = 0000

VCP

Vp/2,

CP_WORD = 1111

VCP

Vp/2,

CP_WORD = 1111

0.5 ≤ VCPo≤ Vp − 0.5,

−40˚C

Vp/2, T

Vp/2, −40˚C

85˚C

25˚C

85˚C 8

−100 µA

100 µA

−1.6 mA

1.6 mA

500 pA

% %

VOLTAGE DOUBLER

D-ON

CPO

P DOUBLER

DIGITAL INTERFACE (DATA, CLK, LE, EN, F

Voltage Doubler Turn on Time OSCIN= 10 MHz, C

Settled to within±10

Charge Pump Output Voltage 2.7V ≤ VCC≤ 3.3V,

Doubler Enabled

Doubler Voltage at VPPin 2.7V ≤ VCC≤ 3.3V,

Doubler Enabled

LD)

ext

= 0.1 µF

TBD µs

2xV

− 1.0

2xV

− 0.5

High-Level Input Voltage (Note 4) 0.8 x

Low-Level Input Voltage (Note 4) 0.2 x

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Electrical Characteristics (V

=Vp=

3.0V; −40˚C

Symbol Parameter Conditions

DIGITAL INTERFACE (DATA, CLK, LE, EN, F

High-Level Input Current V Low-Level Input Current V Oscillator Input Current VIH=VCC= 5.5V 100 µA Oscillator Input Current VIL=0,VCC= 5.5V −100 µA High-Level Output Voltage IOH= −500 µA VCC−

Low-Level Output Voltage IOL= 500 µA 0.4 V

LD)

0, V

85˚C except as specified). (Continued)

Value

Min Typ Max

5.5V, (Note 4) −1.0 1.0 µA =

5.5V, (Note 4) −1.0 1.0 µA

0.4

MICROWIRE TIMING

CWH

CWL

Note 3: Minimum operating frequencies are not production tested — only characterized. Note 4: Except f

Data to Clock Setup Time See Data Input Timing 50 ns Data to Clock Hold Time See Data Input Timing 10 ns Clock Pulse Width High See Data Input Timing 50 ns Clock Pulse Width Low See Data Input Timing 50 ns Clock to Load Enable Setup

Time

See Data Input Timing

50 ns

Load Enable Pulse Width See Data Input Timing 50 ns

and OSCIN.

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2353, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison frequency. This reference signal, fr, is then presented to the input of a phase/frequency detector and compared with another signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of the N counter and fractional circuitry. The phase/frequency detector’s current source outputs pump charge into the loop filter, which then converts the charge into the VCO’s control voltage. The phase/frequency comparator’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency (and phase) match that of the reference signal. When this “phaselocked” condition exists, the RF VCO’s frequency will be N+F times that of the comparison frequency, where N is the integer divide ratio and F is the fractional component. The fractional synthesis allows the phase detector frequency to be increased while maintaining the same frequency step size for channel selection. The division value N is thereby reduced giving a lower phase noise referred to the phase detector input, and the comparison frequency is increased allowing faster switching times.

1.1 REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSC operate to 50 MHz with a minimum input sensitivity of 0.5 V an external CMOS or TTL logic gate.

. The inputs have a VCC/2 input threshold and can be driven from

1.2 REFERENCE DIVIDER (R-COUNTER)

The R-counter is clocked through the oscillator block. The maximum frequency is 50 MHz. The R-counter is CMOS design and 15-bit in length with programmable divider ratio from 3 to 32,767.

1.3 FEEDBACK DIVIDER (N-COUNTER)

The N counter is clocked by the small signal f The integer part is configured as a 5-bit A counter and a 10-bit B counter. The LMX2353 is capable of operating from 500 MHz

input pin. The N counter is 19 bits with 15 bits integer divide and 4 bits fractional.

to 1.2 GHz with the 16/17 prescaler offering a continuous integer divide range from 272 to 16399, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler offering a continuous integer divide range from 1056 to 32767. The fractional compensation is programmable in either 1/15 or 1/16 modes.

1.3.1 Prescaler

The RF input to the prescaler consist of f mentary input is internally coupled to ground with a 10 pF capacitor. This input is typically AC coupled to ground through external

and f

; which are complimentary inputs to a differential pair amplifier. The compli-

INB

capacitors as well. A 16/17 or 32/33 prescaler ratio can be selected.

pin. OSCinblock can

Unit

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1.0 Functional Description (Continued)

1.3.2 Fractional Compensation

The fractional compensation circuitry in the N divider allows the user to adjust the VCO’s tuning resolution in 1/16 or 1/15 increments of the phase detector comparison frequency.A4-bit register is programmed with the fractions desired numerator, while another bit selects between fractional 15 and 16 modulo base denominator.An integer average is accomplished by using a 4-bit accumulator.Avariable phase delay stage compensates for the accumulated integer phase error, minimizing the charge pump duty cycle, and reducing spurious levels. This technique eliminates the need for compensation current injection in to the loop filter. Overflow signals generated by the accumulator are equivalent to 1 full VCO cycle, and result in a pulse swallow.

1.4 PHASE/FREQUENCY DETECTOR

The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the phase detector input is about 2 MHz for some high frequency VCO due to the minimum continuous divide ratio of the dual modulus prescaler. For example, if the VCO output frequency is 1.984 GHz, the maximum phase detector input frequency is 2 MHz because the minimum continuous divide ratio with 32/33 prescaler is 1056. The phase detector outputs control the charge pumps. The polarity of the pump-up or pump-down control is programmed using PD_POL depending on whether the VCO characteristics are positive or negative. The phase detector also receives a feedback signal from the charge pump, in order to eliminate dead zone.

1.5 CHARGE PUMPS

The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control voltage. The charge pump steers the charge pump output CP primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected from 100 µA to 1.6 mA by programming the CP_WORD bits.

1.6 VOLTAGE DOUBLER

The V

pin is normally driven from an external power supply over a range of VCCto 5.5V to provide current for the RF charge

pump circuit. An internal voltage doubler circuit connected between the V

(

10%) users to run the RF charge pump circuit at close to twice the VCCpower supply voltage. The Voltage doubler mode is enabled by setting the V2_EN bit (R[20]) to a HIGH level. The average delivery current of the doubler is less than the instantaneous current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out of lock condition. A large external capacitor connected to V

1.7 MICROWIRE

™

SERIAL INTERFACE

(≈ 0.1 µF) is therefore needed to control power supply droop when changing frequencies.

The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of three functions: clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the rising edge of clock, into the 24-bit shift register. Data is entered MSB first. The last two bits decode the internal register address. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by address bits). A complete programming description is included in the following sections.

1.8 Lock Detect Output

A digital filtered lock detect function is included with each phase detector through an internal digital filter to produce a logic level output available on the FoLD output pin if selected. The lock detect output is high when the error between the phase detector inputs is less than 15 ns for 5 consecutive comparison cycles. The lock detect output is low when the error between the phase detector inputs is more than 30 ns for one comparison cycle. An analog lock detect status generated from the phase detector is also available on the FoLD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when the charge pump is active during a comparison cycle. When a PLL is in power down mode, the respective lock detect output is always low.

1.9 OUT0/OUT1 Output Modes (Fastlock & CMOS Output Modes)

The OUT_0 and OUT_1 pins are normally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also a production test mode that overrides the other two normal modes when activated. The selection of these modes is determined by the 4 bit CMOS register (F2_15–18) described in Table 2.5.3.

The fastlock mode allows the user to open up the loop bandwidth momentarily while acquiring lock by increasing the charge pump output current magnitude while simultaneously switching in a second resistor element to ground via the OUT0 output pin. The loop will lock faster without any additional stability considerations as the phase margin remains constant.

The loop bandwidth during fastlock can be opened up by as much as a factor of 4. The amount of bandwidth increase is a function of the square root of the charge pump current increase. The maximum charge pump current ratio results from switching the charge pump current between 100 µA and 1.6 mA. The damping resistor ratio for these two charge pump current setting changes by the reciprocal of the bandwidth change. In the 4 to 1 bandwidth scenerio, the resulting damping resistor value would be 1/4th of the steady state value. This would be achieved by switching 3 more identical resistors in parallel with the first to ground through the OUT_0 pin.

to VCC(pump-up) or Ground (pump-down). When locked, CPois

and Vpsupply pins alternately allows VCC=3V

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