National Semiconductor LMX2346, LMX2347 Technical data
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LMX2346/LMX2347
LMX2346/LMX2347 PLLatinum Frequency Synthesizer for RF Personal Communications
June 2004
PLLatinum
™
Frequency Synthesizer for RF Personal
Communications
LMX2346 2.0 GHz
LMX2347 2.5 GHz
General Description
The LMX2346/7 are high performance frequency synthesizers with an integrated 32/33 dual modulus prescaler. The
LMX2346 is designed for RF operation up to 2.0 GHz. The
LMX2347 is designed for RF operation up to 2.5 GHz. Using
a proprietary digital phase locked loop technique, the
LMX2346/7 generates very stable, low noise control signals
for UHF and VHF voltage controlled oscillators.
Serial data is transferred into the LMX2346/7 via a three-line
MICROWIRE interface (DATA, LE, CLOCK). Supply voltage
range is from 2.7V to 5.5V. The charge pump provides 4 mA
output current.
The LMX2346/7 are manufactured using National’s 0.5µ
ABiC V silicon BiCMOS process and is available in 16-pin
TSSOP and 16-pin CSP packages.
Functional Block Diagram
Features
n RF operation up to 2.5 GHz
n 2.7V to 5.5V operation
n Digital & Analog Lock Detect
n 32/33 Dual modulus prescaler
n Excellent Phase Noise
n Internal balanced, low leakage charge pump
n Pin Compatible to LMX2323
Applications
n Cellular DCS/PCS/3G infrastructure equipment
n Wireless Local Area Networks (WLANs)
n Other wireless communication systems
20038406
PLLatinum™is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200384 www.national.com
Connection Diagrams
LMX2346/LMX2347
16-Pin Chip Scale Package
NS Package Number SLB16A
Pin Descriptions
Pin Number
Pin Name
OSC
IN
V
P
V
CC
CP
o
16-Pin
CSP
15 1 I Reference oscillator input. A CMOS
1 3 — Charge Pump Power Supply. Must be ≥
2 4 — Main Power Supply. VCCmay range from
3 5 O Charge Pump output. For connection to a
16-Pin
TSSOP
16-Pin TSSOP Package
20038401
NS Package Number MTC16
20038407
I/O Description I/O Circuit Configuration
inverting gate input. The input has a
/2 input threshold and can be driven
V
CC
from an external CMOS or TTL logic
gate.
.
V
CC
2.7V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin
and be connected directly to the ground
plane.
loop filter for driving the voltage control
input of an external VCO.
GND 4 6 — Ground.
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Pin Descriptions (Continued)
Pin Number
Pin Name
F
INB
16-Pin
CSP
16-Pin
TSSOP
5 7 I RF prescaler complementary input. For
I/O Description I/O Circuit Configuration
LMX2346/LMX2347
single ended operation, this pin should be
AC grounded. The LMX2346/7 can be
driven differentially when a bypass
capacitor is omitted.
F
IN
6 8 I RF PLL prescaler input. Small signal
input from the VCO.
CLOCK 8 9 I High impedance CMOS Clock input. Data
is clocked in on the rising edge, into the
18-bit shift register.
DATA 9 10 I Binary serial data input. Data entered
MSB first. LSB is control bit. High
impedance CMOS input.
LE 10 11 I Latch Enable input. When Latch Enable
transitions HIGH, data stored in the 18-bit
shift register is loaded into one of the 2
control registers, based on the address
bit. High impendance CMOS input.
CE 11 12 I Chip Enable input. Provides logical
power-down control of the device. Pull-up
if unused. High impedance CMOS
to V
CC
input.
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Pin Descriptions (Continued)
Pin Number
Pin Name
LD 13 14 O Locked Detect output. Multi-function
LMX2346/LMX2347
16-Pin
CSP
16-Pin
TSSOP
I/O Description I/O Circuit Configuration
CMOS output pin that provides
multiplexed access to digital lock detect,
open-drain analog lock detect, as well as
the outputs of the R and N counters.
NC 7, 12, 14,162, 13, 15,
16
No Connect.
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LMX2346/LMX2347
Absolute Maximum Ratings (Notes 1,
2)
Lead Temp. (solder 4 sec.),
(T
) +260˚C
L
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
(Note 1)
Power Supply Voltage,
) −0.3V to +6.5V
(V
CC
Power Supply for Charge
Pump, (V
) −0.3V to +6.5V
P
Voltage on any pin with
GND=0V, except V
) −0.3V to VCC+0.3V
P(Vi
Power Supply Voltage, (V
) 2.7 5.5 V
CC
Power Supply for Charge Pump, (V
Operating Temperature, (T
) −40 +85 ˚C
A
Min Max Unit
)VCC6.0 V
P
Storage Temperature
Range, (TS) −65˚C to +150˚C
Electrical Characteristics
The following conditions apply; VCC= 3.0V, VP= 3.0V; −40˚C ≤ TA≤ 85˚C, unless specified differently.
Symbol Parameter Conditions Min Typ Max Units
I
CC
I
CC
I
-pwdn Power Down Current CLOCK, DATA, LE = GND
CC
RF PRESCALER
F
IN
PF
IN
PHASE DETECTOR
F
φ
REFERENCE OSCILLATOR
F
OSC
V
OSC
I
IH
I
IL
CHARGE PUMP
ICPo-
source
ICPo-
sink
ICPo-
tri
ICPo-
sink
vs.
ICPo-
source
ICPo vs
VCPo
ICPo vs T
Power Supply Current, LMX2346 3.5 4.5 mA
V
= 5.5V 7.0 mA
CC
Power Supply Current, LMX2347 4.5 5.5 mA
V
= 5.5V 8.0 mA
CC
110µA
Operating Frequency, RF
Prescaler, LMX2346
Operating Frequency, RF
Prescaler, LMX2347
CE = GND
0.2 2.0 GHz
0.2 2.5 GHz
Input Sensitivity, RF Prescaler 2.7V ≤ VCC≤ 3.0V (Note 6) −15 +0 dBm
<
3.0V
VCC≤ 5.5V (Note 6) −10 +0 dBm
Phase Detector Frequency 10 MHz
Operating Frequency, Reference
Oscillator Input
Input Sensitivity, Reference
Oscillator Input
(Note 10)
(Note 7)
5 104 MHz
0.4 V
− 0.3 V
CC
OSCinHigh-Level Input Current VIH=VCC= 5.5V 100 µA
OSCinLow-Level Input Current VIL= 0V, VCC= 5.5V −100 µA
Charge Pump Source Current VCPo = Vp/2V −4.0 mA
Charge Pump Sink Current VCPo = Vp/2V 4.0 mA
Charge Pump TRI-STATE Current 0.5V ≤ VCPo ≤ VP− 0.5V −2.5 2.5 nA
CP Sink vs. Source Mismatch VCPo = Vp/2
= 25˚
T
A
310%
(Note 4)
CP Current vs. Voltage 0.5V ≤ VCPo ≤ VP− 0.5V
= 25˚ (Note 4)
T
A
CP Current vs. Temperature VCPo = Vp/2V (Note 4) 10 %
A
10 15 %
PP
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Electrical Characteristics (Continued)
The following conditions apply; VCC= 3.0V, VP= 3.0V; −40˚C ≤ TA≤ 85˚C, unless specified differently.
Symbol Parameter Conditions Min Typ Max Units
LOGICAL INTERFACE (CE, CLOCK, LE, DATA, LD)
V
IH
V
IL
LMX2346/LMX2347
I
IH
I
IL
V
OH
V
OL
MICROWIRE INTERFACE (CLOCK, LE, DATA)
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
PHASE NOISE
L(f) Single Side-Band Phase Noise F
(f) Normalized Single Side-Band
L
N
High-level Input Voltage 0.8 V
CC
Low-level Input Voltage 0.2 V
High-level Input Current VIH=VCC= 5.5V −1.0 1.0 µA
Low-level Input Current VIL= 0V, VCC= 5.5V −1.0 1.0 µA
High-level Output Voltage IOH= −500 µA VCC− 0.4 V
Low-level Output Voltage IOL= 500 µA 0.4 V
Data to Clock Set Up Time (Note 5) 50 ns
Data to Clock Hold Time (Note 5) 10 ns
Clock Pulse Width High (Note 5) 50 ns
Clock Pulse Width Low (Note 5) 50 ns
Clock to Latch Enable Set Up
Time
(Note 5)
50 ns
Latch Enable Pulse Width (Note 5) 50 ns
= 900 MHz
IN
= 200 kHz
F
φ
= 10 MHz
F
OSC
= 1.0 V
V
OSC
PP
−91 dBc/Hz
TA= 25˚C (Note 3)
= 1750 MHz
F
IN
= 200 kHz
F
φ
= 10 MHz
F
OSC
= 1.0 V
V
OSC
PP
−86 dBc/Hz
TA= 25˚C (Notes 3, 9)
= 1960 MHz
F
IN
= 200 kHz
F
φ
= 10 MHz
F
OSC
= 1.0 V
V
OSC
PP
−85 dBc/Hz
TA= 25˚C (Note 3)
= 2450 MHz
F
IN
= 200 kHz
F
φ
= 10 MHz
F
OSC
= 1.0 V
V
OSC
PP
−83 dBc/Hz
TA= 25˚C (Note 3)
Fφ= 200 kHz
Phase Noise
F
OSC
V
OSC
= 10 MHz
= 1.0 V
PP
−164.5 dBc/Hz
TA= 25˚C (Note 8)
V
CC
V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional. For guaranteed specifications and test conditions see the Electrical Characteristics.
Note 2: This device is a high performance RF integrated circuit with an ESD rating
protected workstations.
Note 3: Phase Noise is measured using a reference evaluation board with a loop bandwidth of approximately 12 kHz. The phase noise specification is the
composite average of 3 measurements made at frequency offsets of 2.0, 2.5 and 3.0 kHz.
Note 4: See Charge Pump Measurement Definitions for detail on how these measurements are made.
Note 5: See Serial Input Data Timing.
Note 6: See F
Note 7: See OSC
Note 8: Normalized Single-Side Band Phase Noise is defined as: L
Note 9: This parameter is derived from Normalized Single Side-Phase Noise, L
Note 10: For F
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Sensitivity Test Setup.
IN
Sensitivity Test Setup.
in
frequencies below 10 MHz, it is recommended that the rise time of the signal does not exceed 25ns.
OSC
(f) = L(f) − 20 log (FIN/Fφ), where L(f) is defined as the Single Side-Band Phase Noise.
N
<
2 kV. Handling and assembly of this device should only be done at ESD
(f).
n
Typical Performance
Characteristics
LMX2346/LMX2347
ICCvs VCCLMX2346/7
CPOTRI-STATE vs CPOVoltage at 85˚C
20038422
20038423
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Typical Performance Characteristics (Continued)
LMX2346/7 Charge Pump Sweeps
LMX2346/LMX2347
20038424
Sink vs Source Mismatch
(See forumla under Charge Pump Current Specifications Definitions)
20038425
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Typical Performance Characteristics (Continued)
Charge Pump Current Variation
(See forumla under Charge Pump Current Specifications Definitions)
LMX2346/LMX2347
LMX2346 FINSensitivity vs Frequency at 3.0V
20038426
20038427
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