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LMX2335U
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National Semiconductor LMX2335U, LMX2336U Technical data

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LMX2335U/LMX2336U
November 2002
LMX2335U/LMX2336U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal
Communications
PLLatinum
™
Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2335U 1.2 GHz/1.2 GHz LMX2336U 2.0 GHz/1.2 GHz
General Description
The LMX2335U and LMX2336U devices are high perfor­mance frequency synthesizers with integrated dual modulus prescalers. The LMX2335U and LMX2336U devices are designed for use in applications requiring two RF phase-locked loops.
A 64/65 or a 128/129 prescale ratio can be selected for each RF synthesizer. Using a proprietary digital phase locked loop technique, the LMX2335U and LMX2336U devices generate very stable, low noise control signals for the RF voltage controlled oscillators. Both RF synthesizers include a two-level programmable charge pump. The RF1 synthesizer has dedicated Fastlock circuitry.
Serial data is transferred to the devices via a three wire interface (Data, LE, Clock). Supply voltages from 2.7V to
5.5V are supported. The LMX2335U and the LMX2336U feature very low current consumption:
LMX2335U (1.2 GHz)– 3.0 mA, LMX2336U (2.0 GHz)–
3.5 mA at 3.0V. The LMX2335U device is available in 16-pin TSSOP, and
16-pin Chip Scale Package (CSP) surface mount plastic packages. The LMX2336U device is available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin UTCSP surface mount plastic packages.
Features
n Ultra Low Current Consumption n Upgrade and Compatible to the LMX2335L and
LMX2336L devices
n 2.7V to 5.5V operation n Selectable Synchronous or Asynchronous Powerdown
Mode: I
CC-PWDN
n Selectable Dual Modulus Prescaler
RF1: 64/65 or 128/129 RF2: 64/65 or 128/129
n Selectable Charge Pump TRI-STATE n Programmable Charge Pump Current Levels
RF1 and RF2: 0.95 or 3.8 mA
n Selectable Fastlock n Push-Pull Analog Lock Detect Mode n LMX2335U is available in 16-Pin TSSOP and 16-Pin
CSP
n LMX2336U is available in 20-Pin TSSOP, 24-Pin CSP,
and 20-Pin UTCSP
= 1 µA typical at 3.0V
™
Mode for the RF1 Synthesizer
Applications
n Mobile Handsets
(GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS)
n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners
®
Mode
Thin Shrink Small Outline Package (MTC16) Thin Shrink Small Outline Package (MTC20)
10136787
Ultra Thin Chip Scale Package
Chip Scale Package (SLB16A) Chip Scale Package (SLB24A)
10136788
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
Fastlock
, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation DS101367 www.national.com
10136781
10136780
(SLE20A)
10136795
LMX2335U Functional Block Diagram
LMX2335U/LMX2336U
LMX2336U Functional Block Diagram
10136789
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10136701
Connection Diagrams
LMX2335U/LMX2336U
LMX2335U Thin Shrink Small Outline Package (TM)
(Top View)
10136702
LMX2336U Thin Shrink Small Outline Package (TM)
(Top View)
LMX2335U Chip Scale Package (SLB)
(Top View)
10136738
LMX2336U Chip Scale Package (SLB)
(Top View)
10136703
LMX2336U Ultra Thin Chip Scale Package (SLE)
(Top View)
10136796
10136736
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Pin Descriptions
Pin No.
Pin
LMX2336U
Name
20-Pin
UTCSP
V
CC
20 1 24 1 16 – Power supply bias for the RF1 PLL analog and
LMX2335U/LMX2336U
Pin No.
LMX2336U
20-Pin
TSSOP
Pin No.
LMX2336U
24-Pin
CSP
Pin No.
LMX2335U
16-Pin
TSSOP
Pin No.
LMX2335U
16-Pin
CSP
I/O Description
digital circuits. V
may range from 2.7V to
CC
5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane.
V
P
RF1
D
RF1
o
1 2 2 2 1 – RF1 PLL charge pump power supply. Must be ≥
VCC.
2 3 3 3 2 O RF1 PLL charge pump output. The output is
connected to the external loop filter, which drives the input of the VCO.
GND 3 4 4 4 3 – LMX2335U: Ground for the RF1 PLL analog and
digital circuits. LMX2336U: Ground for the RF1 PLL digital circuitry.
RF1 4 5 5 5 4 I RF1 PLL prescaler input. Small signal input from
f
IN
the VCO.
fINRF1 5 6 6 X X I LMX2335U: Don’t care.
LMX2336U: RF1 PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2336U RF1 PLL can be driven differentially when the bypass capacitor is omitted.
GND 6 7 7 X X – LMX2335U: Don’t care.
LMX2336U: Ground for the RF1 PLL analog circuitry.
OSC
in
7 8 8 6 5 I Oscillator input. It has an approximate VCC/2
input threshold and can be driven from an external CMOS or TTL logic gate.
OSC
out
8 9 10 7 6 O Oscillator output. This output is connected
directly to a crystal. If a TCXO is used, it is left open.
LD 9 10 11 8 7 O Programmable multiplexed output pin. Functions
F
o
as a general purpose CMOS TRI-STATE output, RF1/RF2 PLL push-pull analog lock detect output, N and R divider output, or Fastlock output, which connects a parallel resistor to the external loop filter.
Clock 10 11 12 9 8 I MICROWIRE Clock input. High impedance
CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock.
Data 11 12 14 10 9 I MICROWIRE Data input. High impedance
CMOS input. Binary serial data. The MSB of Data is entered first. The last two bits are the control bits.
LE 12 13 15 11 10 I MICROWIRE Latch Enable input. High
impedance CMOS input. When LE transitions HIGH, Data stored in the shift registers is loaded into one of 4 internal control registers.
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Pin Descriptions (Continued)
LMX2335U/LMX2336U
Pin
Name
Pin No.
LMX2336U
20-Pin
UTCSP
Pin No.
LMX2336U
20-Pin
TSSOP
Pin No.
LMX2336U
24-Pin
CSP
Pin No.
LMX2335U
16-Pin
TSSOP
Pin No.
LMX2335U
16-Pin
CSP
I/O Description
GND 13 14 16 X X – LMX2335U: Don’t care.
LMX2336U: Ground for the RF2 PLL analog circuitry.
RF2 14 15 17 X X I LMX2335U: Don’t care.
f
IN
LMX2336U: RF2 PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2336U RF2 PLL can be driven differentially when the bypass capacitor is omitted.
RF2 15 16 18 12 11 I RF2 PLL prescaler input. Small signal input from
f
IN
the VCO.
GND 16 17 19 13 12 − LMX2335U: Ground for the RF2 PLL analog and
digital circuits, MICROWIRE, F
LD and oscillator
o
circuits. LMX2336U: Ground for the RF2 PLL digital circuitry, MICROWIRE, F
LD and
o
oscillator circuits.
D
RF2
o
17 18 20 14 13 O RF2 PLL charge pump output. The output is
connected to the external loop filter, which drives the input of the VCO.
V
RF2
V
CC
P
18 19 22 15 14 – RF2 PLL charge pump power supply. Must be ≥
VCC.
19 20 23 16 15 – Power supply bias for the RF2 PLL analog and
digital circuits, MICROWIRE, F circuits. V
may range from 2.7V to 5.5V.
CC
LD and oscillator
o
Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane.
NC X X 1, 9, 13,
21
X X – LMX2335U: Don’t Care.
LMX2336U: No connect.
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Ordering Information
Model Temperature Range Package Description Packing NS Package Number
LMX2335USLBX −40˚C to +85˚C Chip Scale Package
LMX2335UTM −40˚C to +85˚C Thin Shrink Small
LMX2335U/LMX2336U
LMX2335UTMX −40˚C to +85˚C Thin Shrink Small
LMX2336USLEX −40˚C to +85˚C Ultra Thin Chip Scale
LMX2336USLBX −40˚C to +85˚C Chip Scale Package
LMX2336UTM −40˚C to +85˚C Thin Shrink Small
LMX2336UTMX −40˚C to +85˚C Thin Shrink Small
2500 Units Per Reel SLB16A
(CSP) Tape and Reel
96 Units Per Rail MTC16
Outline Package
(TSSOP)
2500 Units Per Reel MTC16
Outline Package
(TSSOP) Tape and
Reel
2500 Units Per Reel SLE20A
Package (UTCSP)
Tape and Reel
2500 Units Per Reel SLB24A
(CSP) Tape and Reel
73 Units Per Rail MTC20
Outline Package
(TSSOP)
2500 Units Per Reel MTC20
Outline Package
(TSSOP) Tape and
Reel
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Detailed Block Diagram
LMX2335U/LMX2336U
Notes:
supplies power to the RF1 and RF2 prescalers, RF1 and RF2 feedback dividers, RF1 and RF2 reference dividers, RF1 and RF2 phase detectors, the
1. V
CC
OSC
buffer, MICROWIRE, and FoLD circuits.
in
RF1 and VPRF2 supply power to the charge pumps. They can be run separately as long as VPRF1 ≥ VCCand VPRF2 ≥ VCC.
2. V
P
3. X signifies a pin that is NOT available on the LMX2335U PLL.
10136704
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Absolute Maximum Ratings (Notes 1,
2, 3)
16-Pin CSP θ
24-Pin CSP θ
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Recommended Operating Conditions
Power Supply Voltage
V
to GND −0.3V to +6.5V
LMX2335U/LMX2336U
CC
V
RF1 to GND −0.3V to +6.5V
P
V
RF2 to GND −0.3V to +6.5V
P
Voltage on any pin to GND (V
V
must be<+6.5V −0.3V to VCC+0.3V
I
Storage Temperature Range (T
Lead Temperature (solder 4 s) (T
16-Pin TSSOP θ
Thermal
JA
)
I
) −65˚C to +150˚C
S
) +260˚C
L
Impedance 137.1˚C/W
20-Pin TSSOP θJAThermal Impedance 114.5˚C/W
Power Supply Voltage
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate condi­tions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test condi­tions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD rating should only be done at ESD protected work stations.
Note 3: GND=0V
Electrical Characteristics
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
I
PARAMETERS
CC
I
CC
RF1 + RF2
I
CC
RF1
I
CC
RF2
I
CC-PWDN
RF1 SYNTHESIZER PARAMETERS
RF1 RF1 Operating
f
IN
N
RF1
R
RF1
F
φRF1
Pf
RF1 RF1 Input Sensitivity 2.7V ≤ VCC≤ 3.0V
IN
Power Supply Current, RF1 + RF2 Synthesizers
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 3.5 4.5 mA
PWDN RF1 Bit = 0 PWDN RF2 Bit = 0
Power Supply Current, RF1 Synthesizer Only
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 2.0 2.5 mA
PWDN RF1 Bit = 0 PWDN RF2 Bit = 1
Power Supply Current, RF2 Synthesizer Only
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 1.5 2.0
PWDN RF1 Bit = 1 PWDN RF2 Bit = 0
Powerdown Current LMX2335U/ Clock, Data and LE = GND
= GND
OSC
in
LMX2336U
PWDN RF1 Bit = 1 PWDN RF2 Bit = 1
LMX2335U 100 1200 MHz
Frequency
LMX2336U 200 2000 MHz
RF1 N Divider Range Prescaler = 64/65
(Note 4)
Prescaler = 128/129 (Note 4)
RF1 R Divider Range 3 32767
RF1 Phase Detector Frequency 10 MHz
(Note 5)
<
VCC≤ 5.5V
3.0V (Note 5)
Thermal Impedance 130˚C/W
JA
Thermal Impedance 112˚C/W
JA
(Note 1)
V
to GND +2.7V to +5.5V
CC
V
RF1 to GND VCCto +5.5V
P
V
RF2 to GND VCCto +5.5V
P
) −40˚C to +85˚C
A
<
2 kV and is ESD sensitive. Handling and assembly of this device
Value
Min Typ Max
3.0 4.0 mA
1.5 2.0 mA
1.5 2.0 mA
1.0 10.0 µA
192 131135
384 262143
−15 0 dBm
−10 0 dBm
Units
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
RF1 SYNTHESIZER PARAMETERS
ID
RF1
o
SOURCE
RF1
ID
o
SINK
RF1
ID
o
TRI-STATE
IDoRF1 SINK Vs
RF1
ID
o
SOURCE
RF1
ID
o
Vs
RF1
VD
o
RF1
ID
o
Vs T
A
RF2 SYNTHESIZER PARAMETERS
RF2 RF2 Operating
f
IN
N
RF2
R
RF2
F
φRF2
Pf
RF2 RF2 Input Sensitivity 2.7V ≤ VCC≤ 3.0V
IN
RF1 Charge Pump Output Source Current
VDoRF1=VPRF1/2
RF1 Bit = 0
ID
o
(Note 6)
RF1=VPRF1/2
VD
o
RF1 Bit = 1
ID
o
(Note 6)
RF1 Charge Pump Output Sink Current
VDoRF1=VPRF1/2
RF1 Bit = 0
ID
o
(Note 6)
RF1=VPRF1/2
VD
o
RF1 Bit = 1
ID
o
(Note 6)
RF1 Charge Pump Output TRI-STATE Current
RF1 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch
RF1 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage
RF1 Charge Pump Output Current Magnitude Variation Vs Temperature
0.5V ≤ VDoRF1 ≤ VPRF1 - 0.5V (Note 6)
RF1=VPRF1/2
VD
o
= +25˚C
T
A
(Note 7)
0.5V ≤ VD = +25˚C
T
A
RF1 ≤ VPRF1 - 0.5V
o
(Note 7)
VDoRF1=VPRF1/2 (Note 7)
LMX2335U 100 1200 MHz
Frequency
LMX2336U 100 1200 MHz
RF2 N Divider Range Prescaler = 64/65
(Note 4)
Prescaler = 128/129 (Note 4)
RF2 R Divider Range 3 32767
RF2 Phase Detector Frequency 10 MHz
(Note 5)
3.0V<VCC≤ 5.5V
(Note 5)
Value
Min Typ Max
Units
-0.95 mA
-3.80 mA
0.95 mA
3.80 mA
-2.5 2.5 nA
310%
10 15 %
10 %
192 131135
384 262143
-15 0 dBm
-10 0 dBm
LMX2335U/LMX2336U
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
RF2 SYNTHESIZER PARAMETERS
ID
RF2
o
SOURCE
LMX2335U/LMX2336U
RF2
ID
o
SINK
RF2
ID
o
TRI-STATE
IDoRF2 SINK Vs
RF2
ID
o
SOURCE
RF2
ID
o
Vs
RF2
VD
o
RF2
ID
o
Vs T
A
OSCILLATOR PARAMETERS
F
OSC
V
OSC
I
OSC
DIGITAL INTERFACE (Data, LE, Clock, F
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
MICROWIRE INTERFACE
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
RF2 Charge Pump Output Source Current
VDoRF2=VPRF2/2
RF2 Bit = 0
ID
o
(Note 6)
RF2=VPRF2/2
VD
o
RF2 Bit = 1
ID
o
(Note 6)
RF2 Charge Pump Output Sink Current
VDoRF2=VPRF2/2
RF2 Bit = 0
ID
o
(Note 6)
RF2= VPRF2/2
VD
o
RF2 Bit = 1
ID
o
(Note 6)
RF2 Charge Pump Output TRI-STATE Current
RF2 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch
RF2 Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage
RF2 Charge Pump Output Current Magnitude Variation Vs Temperature
0.5V ≤ VDoRF2 ≤ VPRF2 - 0.5V (Note 6)
RF2=VPRF2/2
VD
o
= +25˚C
T
A
(Note 7)
0.5V ≤ VD = +25˚C
T
A
RF2 ≤ VPRF2 - 0.5V
o
(Note 7)
VDoRF2=VPRF2/2 (Note 7)
Oscillator Operating Frequency 2 40 MHz
Oscillator Sensitivity (Note 8) 0.5 V
Oscillator Input Current V
LD)
o
OSC=VCC
V
OSC
= 5.5V 100 µA
= 0V, VCC= 5.5V -100 µA
High-Level Input Voltage 0.8 V
Low-Level Input Voltage 0.2 V
High-Level Input Current VIH=VCC= 5.5V −1.0 1.0 µA
Low-Level Input Current VIL= 0V, VCC= 5.5V −1.0 1.0 µA
High-Level Output Voltage IOH= −500 µA VCC−
Low-Level Output Voltage IOL= 500 µA 0.4 V
Data to Clock Set Up Time (Note 9) 50 ns
Data to Clock Hold Time (Note 9) 10 ns
Clock Pulse Width HIGH (Note 9) 50 ns
Clock Pulse Width LOW (Note 9) 50 ns
Clock to Load Enable Set Up Time (Note 9) 50 ns
Latch Enable Pulse Width (Note 9) 50 ns
Value
Min Typ Max
Units
-0.95 mA
-3.80 mA
0.95 mA
3.80 mA
-2.5 2.5 nA
310%
10 15 %
10 %
V
CC
CC
CC
0.4
PP
V
V
V
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
PHASE NOISE CHARACTERISTICS
L
(f) RF1 RF1 Synthesizer Normalized Phase
N
Noise Contribution (Note 10)
L(f) RF1 RF1 Synthesizer
LMX2335U f Single Side Band Phase Noise Measured
LMX2336U f
TCXO Reference Source
RF1 Bit = 1
ID
o
RF1 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF1
Loop Bandwidth = 12 kHz N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
PP
IDoRF1 Bit = 1 PWDN RF2 Bit = 1
= +25˚C
T
A
(Note 11)
RF1 = 1960 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF1
Loop Bandwidth = 15 kHz N = 9800
=10MHz
F
OSC
= 0.632 V
V
OSC
PP
IDoRF1 Bit = 1 PWDN RF2 Bit = 1
= +25˚C
T
A
(Note 11)
Value
Min Typ Max
-212.0 dBc/
-85.94 dBc/
-79.18 dBc/
LMX2335U/LMX2336U
Units
Hz
Hz
Hz
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
PHASE NOISE CHARACTERISTICS
L
(f) RF2 RF2 Synthesizer Normalized Phase
N
Noise Contribution
LMX2335U/LMX2336U
(Note 10)
L(f) RF2 RF2 Synthesizer
Single Side Band Phase Noise Measured
LMX2335U f
LMX2336U f
TCXO Reference Source
RF2 Bit = 1
ID
o
RF2 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF2
Loop Bandwidth = 12 kHz N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
IDoRF2 Bit = 1 PWDN RF1 Bit = 1
= +25˚C
T
A
(Note 11)
RF2 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF2
Loop Bandwidth = 12 kHz N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
IDoRF2 Bit = 1 PWDN RF1 Bit = 1
= +25˚C
T
A
(Note 11)
Value
Min Typ Max
Units
-212.0 dBc/ Hz
-85.94 dBc/ Hz
PP
-85.94 dBc/ Hz
PP
Note 4: Some of the values in this range are illegal divide ratios (B<A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N
*
≥ P
(P−1), where P is the value selected for the prescaler.
Note 5: Refer to the LMX2335U and LMX2336U f
Note 6: Refer to the LMX2335U and LMX2336U Charge Pump Test Setup section
Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made.
Note 8: Refer to the LMX2335U and LMX2336U OSC
Note 9: Refer to the LMX2335U and LMX2336U Serial Data Input Timing section
Note 10: Normalized Phase Noise Contribution is defined as : L
measured at an offset frequency, f, ina1Hzbandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and F comparison frequency..
Note 11: The synthesizer phase noise is measured with the LMX2335TMEB/LMX2335SLBEB or LMX2336TMEB/LMX2336SLBEB/LMX2336SLEEB Evaluation boards and the HP8566B Spectrum Analyzer.
Sensitivity Test Setup section
IN
Sensitivity Test Setup section
in
(f) = L(f) − 20 log (N) − 10 log (Fφ), where L(f) is defined as the single side band phase noise
N
is the RF1/RF2 phase detector
φ
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Typical Performance Characteristics Sensitivity
LMX2335U fINRF1 Input Power Vs Frequency
V
CC=VP
LMX2335U/LMX2336U
RF1 = 3.0V
LMX2335U fINRF1 Input Power Vs Frequency
V
CC=VP
RF1 = 5.5V
10136746
10136747
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Typical Performance Characteristics Sensitivity
(Continued)
LMX2335U/LMX2336U
LMX2336U f
RF1 Input Power Vs Frequency
IN
V
CC=VP
RF1 = 3.0V
LMX2336U fINRF1 Input Power Vs Frequency
V
CC=VP
RF1 = 5.5V
10136744
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10136745
Typical Performance Characteristics Sensitivity
(Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U f
V
CC=VP
RF2 Input Power Vs Frequency
IN
RF2 = 3.0V
LMX2335U and LMX2336U fINRF2 Input Power Vs Frequency
V
CC=VP
RF2 = 5.5V
10136792
10136793
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Typical Performance Characteristics Sensitivity
(Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U OSC
V
Input Voltage Vs Frequency
in
= 3.0V
CC
LMX2335U and LMX2336U OSCinInput Voltage Vs Frequency
= 5.5V
V
CC
10136752
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10136753
Typical Performance Characteristics Charge Pump
LMX2335U and LMX2336U RF1 Charge Pump Sweeps
−40˚C ≤ T
≤ +85˚C
A
LMX2335U/LMX2336U
10136760
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Typical Performance Characteristics Charge Pump
LMX2335U/LMX2336U
(Continued)
LMX2335U and LMX2336U RF2 Charge Pump Sweeps
−40˚C ≤ T
≤ +85˚C
A
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10136761
Typical Performance Characteristics Input Impedance
LMX2335U/LMX2336U
LMX2335U TSSOP and LMX2336U TSSOP
RF1 and fINRF2 Input Impedance
f
IN
= 3.0V, TA= +25˚C
V
CC
LMX2335U TSSOP and LMX2336U TSSOP
f
RF1 and fINRF2 Input Impedance
IN
= 5.5V, TA= +25˚C
V
CC
LMX2335U CSP and LMX2336U CSP
RF1 and fINRF2 Input Impedance
f
IN
= 3.0V, TA= +25˚C
V
CC
10136766 10136767
LMX2335U CSP and LMX2336U CSP f
RF1 and fINRF2 Input Impedance
IN
= 5.5V, TA= +25˚C
V
CC
10136768 10136769
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LMX2335U/LMX2336U
RF2 Input Impedance Table
IN
RF1 and f
IN
10136770
LMX2335U/LMX2336U TSSOP and LMX2335U/LMX2336U CSP f
(Continued)
Typical Performance Characteristics
Input Impedance
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Typical Performance Characteristics Input Impedance
(Continued)
LMX2335U/LMX2336U
LMX2336U UTCSP
RF1 and fINRF2 Input Impedance
f
IN
= 3.0V, TA= +25˚C
V
CC
LMX2336U UTCSP
f
RF1 and fINRF2 Input Impedance
IN
= 5.5V, TA= +25˚C
V
CC
10136797 10136797
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LMX2335U/LMX2336U
RF2 Input Impedance Table
IN
RF1 and f
IN
10136798
LMX2336U UTCSP f
(Continued)
Typical Performance Characteristics
Input Impedance
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Typical Performance Characteristics Input Impedance
(Continued)
LMX2335U TSSOP and LMX2336U TSSOP
Input Impedance Vs Frequency
OSC
in
T
A
LMX2335U/LMX2336U
= +25˚C
LMX2335U CSP and LMX2336U CSP
Input Impedance Vs Frequency
OSC
in
T
A
= +25˚C
10136776
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10136777
LMX2335U/LMX2336U
Input Impedance Table
in
10136778
LMX2335U/LMX2336U TSSOP and LMX2335U/LMX2336U CSP OSC
(Continued)
Typical Performance Characteristics
Input Impedance
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Typical Performance Characteristics Input Impedance
(Continued)
LMX2336U UTCSP
Input Impedance Vs Frequency
OSC
in
T
A
LMX2335U/LMX2336U
= +25˚C
101367A1
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LMX2335U/LMX2336U
Input Impedance Table
in
101367A2
LMX2336U UTCSP OSC
(Continued)
Typical Performance Characteristics
Input Impedance
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Charge Pump Current Specification Definitions
LMX2335U/LMX2336U
I1 = Charge Pump Sink Current at VDo=VP− ∆V
I2 = Charge Pump Sink Current at VD
I3 = Charge Pump Sink Current at VD
I4 = Charge Pump Source Current at VD
I5 = Charge Pump Source Current at VD
I6 = Charge Pump Source Current at VD
o=VP
= ∆V
o
o=VP
o=VP
o
/2
− ∆V
/2
= ∆V
∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to V
1.0V.
V
refers to either VPRF1 or VPRF2
P
refers to either VDoRF1 or VDoRF2
VD
o
refers to either IDoRF1 or IDoRF2
ID
o
Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage
10136763
Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch
10136764
10136783
and GND. Typical values are between 0.5V and
CC
Charge Pump Output Current Magnitude Variation Vs Temperature
10136765
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Test Setups
LMX2335U/LMX2336U
LMX2335U and LMX2336U Charge Pump Test Setup
The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 charge pump sink current. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. The RF2 charge pump measurement setup is similar to the RF1 charge pump mea­surement setup. The purpose of this test is to assess the functionality of the RF1 charge pump.
This setup uses an open loop configuration. A power supply is connected to V
and swept from 2.7V to 5.5V. By means
cc
of a signal generator, a 10 MHz signal is typically applied to
RF1 pin. The signal is one of two inputs to the phase
the f
IN
detector. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSC
pin is tied to Vcc.
in
This establishes the other input to the phase detector. Alter­natively, this input can be tied directly to the ground plane. With the D
RF1 pin connected to a Semiconductor Param-
o
eter Analyzer in this way, the sink, source, and TRI-STATE currents can be measured by simply toggling the Phase Detector Polarity and Charge Pump State states in Code Loader. Similarly, the LOW and HIGH currents can be mea­sured by switching the Charge Pump Gain’s state between 1X and 4X in Code Loader.
10136750
represent the frequency of the signal applied to the
Let F
r
pin, which is simply zero in this case (DC), and let F
OSC
in
represent the frequency of the signal applied to the fINRF1 pin. The phase detector is sensitive to the rising edges of F and Fp. Assuming positive VCO characteristics; the charge pump turns ON and sinks current when the first rising edge
is detected. Since Frhas no rising edge, the charge
of F
p
pump continues to sink current indefinitely. Toggling the Phase Detector Polarity state to negative
VCO characteristics allows the measurement of the RF1 charge pump source current. Likewise, selecting TRI-STATE (TRI-STATE ID
RF1 Bit = 1) for Charge Pump State in
o
Code Loader facilitates the measurement of the TRI-STATE current.
The measurements are repeated at different temperatures, namely T
= -40˚C, +25˚C, and +85˚C.
A
The LMX2335U charge pump test setup is very much similar to the above test setup.
p
r
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Test Setups (Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U f
Sensitivity Test Setup
IN
The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 input sensitivity level. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. The RF2 input sensitiv­ity test setup is similar to the RF1 sensitivity test setup. The purpose of this test is to measure the acceptable signal level to the f
RF1 input of the PLL chip. Outside the acceptable
IN
signal range, the feedback divider begins to divide incor­rectly and miscount the frequency.
The setup uses an open loop configuration. A power supply is connected to V
and the bias voltage is swept from 2.7V
cc
to 5.5V. The RF2 PLL is powered down (PWDN RF2 Bit = 1). By means of a signal generator, an RF signal is applied to
RF1 pin. The 3 dB pad provides a 50 Ω match
the f
IN
between the PLL and the signal generator. The OSC tied to V
. The N value is typically set to 10000 in Code
cc
in
pin is
Loader, i.e. RF1 N_CNTRB Word = 156 and RF1 N_CNTRA Word = 16 for PRE RF1 Bit = 0. The feedback divider output is routed to the F Output word (F Universal Counter is connected to the F
LD pin by selecting the RF1 PLL N Divider
o
LD Word = 6 or 14) in Code Loader. A
o
LD pin and tied to
o
10136740
the 10 MHz reference output of the signal generator. The output of the feedback divider is thus monitored and should be equal to f
The f
IN
RF1/N.
IN
RF1 input frequency and power level are then swept with the signal generator. The measurements are repeated at different temperatures, namely T
= -40˚C, +25˚C, and
A
+85˚C. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3 dB pad must be ac­counted for. The feedback divider will actually miscount if too much or too little power is applied to the f
RF1 input.
IN
Therefore, the allowed input power level will be bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the f
RF1 input approaches the sen-
IN
sitivity limits, this can introduce spurs and degradation in phase noise. When the power level gets even closer to these limits, or exceeds it, then the RF1 PLL loses lock.
The LMX2335U f
sensitivity test setup is very much similar
IN
to the above test setup.
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Test Setups (Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U OSC
Sensitivity Test Setup
in
The block diagram above illustrates the setup required to measure the LMX2336U device’s OSC
buffer sensitivity
in
level. The same setup is used for the LMX2336TMEB/ LMX2336SLEEB Evaluation Boards. This setup is similar to
sensitivity setup except that the signal generator is
the f
IN
now connected to the OSC
. The 51 Ω shunt resistor matches the OSCininput to the
V
CC
pin and both fINpins are tied to
in
signal generator. The R counter is typically set to 1000, i.e. RF1 R_CNTR Word = 1000 or RF2 R_CNTR Word = 1000. The reference divider output is routed to the F selecting the RF1 PLL R Divider Output word (F = 2 or 10) or the RF2 PLL R Divider Output word (F
LD pin by
o
LD Word
o
LD
o
Word = 1 or 9) in Code Loader. Similarly, a Universal
10136741
Counter is connected to the F
LD pin and is tied to the 10
o
MHz reference output from the signal generator. The output of the reference divider is monitored and should be equal to
/ RF1 R_CNTR or OSCin/ RF2 R_CNTR.
OSC
in
Again, V
is swept from 2.7V to 5.5V. The OSCininput
CC
frequency and voltage level are then swept with the signal generator. The measurements are repeated at different tem­peratures, namely T
= -40˚C, +25˚C, and +85˚C. Sensitivity
A
is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz.
The LMX2335U OSC
sensitivity test setup is very much
in
similar to the above test setup.
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Test Setups (Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U f
Impedance Test Setup
IN
The block diagram above illustrates the setup required to measure the LMX2336U device’s RF1 input impedance. The RF2 input impedance and reference oscillator impedance setups are very much similar. The same setup is used for a LMX2336TMEB Evaluation Board. Measuring the device’s input impedance facilitates the design of appropriate match­ing networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired transmission line effects.
Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error coefficients need to be calculated. Therefore, three standards will be used to calculate these coefficients: an open, short and a matched load. A 1-port calibration is implemented here.
To calculate the coefficients, the PLL chip is first removed from the PCB. The Network Analyzer port is then connected to the RF1 OUT connector of the evaluation board and the desired operating frequency is set. The typical frequency range selected for the LMX2336U device’s RF1 synthesizer is from 100 MHz to 2000 MHz. The standards will be located down the length of the RF1 OUT transmission line. The transmission line adds electrical length and acts as an offset from the reference plane of the Network Analyzer; therefore, it must be included in the calibration. Although not shown, 0 Ω resistors are used to complete the RF1 OUT transmission line (trace).
10136779
To implement an open standard, the end of the RF1 OUT trace is simply left open. To implement a short standard, a 0 Ω resistor is placed at the end of the RF1 OUT transmission line. Last of all, to implement a matched load standard, two 100 Ω resistors in parallel are placed at the end of the RF1 OUT transmission line. The Network Analyzer calculates the calibration coefficients based on the measured S
11
param-
eters. With this all done, calibration is now complete. The PLL chip is then placed on the PCB. A power supply is
connected to V
5.5V. The OSC the OSC
in
mentary input (f
and the bias voltage is swept from 2.7V to
CC
pin is tied to the ground plane. Alternatively,
in
pin can be tied to VCC. In this setup, the comple-
RF1) is AC coupled to ground. With the
IN
Network Analyzer still connected to RF1 OUT, the measured
RF1 impedance is displayed.
f
IN
Note: The impedance of the reference oscillator is measured when the oscillator buffer is powered up (PWDN RF1 Bit = 0 or PWDN RF2 Bit = 0), and when the oscillator buffer is powered down (PWDN RF1 Bit = 1 and PWDN RF2 Bit = 1).
The LMX2335U f
impedance test setup is very much simi-
IN
lar to the above test setup. Note that there are no comple­mentary inputs in the LMX2335U device.
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LMX2335U and LMX2336U Serial Data Input Timing
LMX2335U/LMX2336U
Notes:
1. Data is clocked into the 22-bit shift register on the rising edge of Clock
2. The MSB of Data is shifted in first.
10136784
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1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe­sizer such as the National Semiconductor LMX2335U or LMX2336U, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, programmable reference R and feedback N frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the reference divider to obtain a comparison reference frequency. This reference signal, F sented to the input of a phase/frequency detector and com­pared with the feedback signal, F
, which was obtained by
p
dividing the VCO frequency down by way of the feedback divider. The phase/frequency detector measures the phase error between the F
and Fpsignals and outputs control
r
signals that are directly proportional to the phase error. The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error. The loop filter converts the charge into a stable control voltage for the VCO. The phase/frequency detector’s func­tion is to adjust the voltage presented to the VCO until the feedback signal’s frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency will be N times that of the comparison frequency, where N is the feedback divider ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for both the RF1 and RF2 PLLs is provided from an external reference via the OSC pin. The reference buffer circuit supports input frequencies from 5 to 40 MHz with a minimum input sensitivity of 0.5 V The reference buffer circuit has an approximate V threshold and can be driven from an external CMOS or TTL logic gate. Typically, the OSC
pin is connected to the output
in
of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R COUNTERS)
The reference dividers divide the reference input signal,
, by a factor of R. The output of the reference divider
OSC
in
circuits feeds the reference input of the phase detector. This reference input to the phase detector is often referred to as the comparison frequency. The divide ratio should be chosen such that the maximum phase comparison frequency (F or F
) of 10 MHz is not exceeded.
φRF2
The RF1 and RF2 reference dividers are each comprised of 15-bit CMOS binary counters that support a continuous in­teger divide ratio from 3 to 32767. The RF1 and RF2 refer­ence divider circuits are clocked by the output of the refer­ence buffer circuit which is common to both.
1.3 PRESCALERS
RF1 (fINRF2) and fINRF1 (fINRF2) input pins of the
The f
IN
LMX2336U device drives the input of a bipolar, differential­pair amplifier. The output of the bipolar, differential-pair am­plifier drives a chain of ECL D-type flip-flops in a dual modu-
, is then pre-
r
/2 input
CC
φRF1
PP
LMX2335U/LMX2336U
lus configuration. The output of the prescaler is used to clock the subsequent feedback dividers. The complementary in­puts of both the RF1 and RF2 synthesizers can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended con­figuration. A 64/65 or a 128/129 prescale ratio can be se­lected for the both the RF1 and RF2 synthesizers. On the other hand, the LMX2335U PLL is only intended for single ended operation. Similarly, a 64/65 or a 128/129 prescale ratio can be selected for both the RF1 and RF2 synthesizers.
1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N COUNTERS)
The programmable feedback dividers operate in concert with the prescalers to divide the input signal f The output of the programmable reference divider is pro­vided to the feedback input of the phase detector circuit. The divide ratio should be chosen such that the maximum phase comparison frequency (F
φRF1
or F
exceeded. The programmable feedback divider circuit is comprised of
an A counter (swallow counter) and a B counter (program­mble binary counter). The RF1 N_CNTRA counter and RF2 N_CNTRA counter are both 7-bit CMOS swallow counters, programmable from 0 to 127. The RF1 N_CNTRB and RF2 N_CNTRB counters are both 11-bit CMOS binary counters, programmable from 3 to 2047. A continuous integer divide
*
in
.
prescaler selected. Divide ratios less than the minimum con­tinuous divide ratio are achievable as long as the binary programmable counter value is greater than the swallow
ratio is achieved if N ≥ P
(P−1), where P is the value of the
counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections
2.5.1, 2.5.2, 2.7.1 and 2.7.2 for details on how to program the N_CNTRA and N_CNTRB counters. The following equa­tions are useful in determining and programming a particular value of N:
N = (P x N_CNTRB) + N_CNTRA
=NxF
f
IN
φ
Definitions:
F
: RF1 or RF2 phase detector comparison
φ
frequency
: RF1 or RF2 input frequency
f
IN
N_CNTRA: RF1 or RF2 A counter value N_CNTRB: RF1 or RF2 B counter value P: Preset modulus of the dual moduIus
prescaler LMX2335U RF1 synthesizer: P = 64 or 128 LMX2336U RF1 synthesizer: P = 64 or 128 LMX2335U RF2 synthesizer: P = 64 or 128 LMX2336U RF2 synthesizer: P = 64 or 128
by a factor of N.
IN
) of 10 MHz is not
φRF2
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1.0 Functional Description (Continued)
1.5 PHASE/FREQUENCY DETECTORS
The RF1 and RF2 phase/frequency detectors are driven from their respective N and R counter outputs. The maxi­mum frequency for both the RF1 and RF2 phase detector inputs is 10 MHz. The phase/frequency detector outputs control the respective charge pumps. The polarity of the pump-up or pump-down control signals are programmed
LMX2335U/LMX2336U
using the PD_POL RF1 or PD_POL RF2 control bits, de-
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
pending on whether the RF1 or RF2 VCO characteristics are positive or negative. Refer to Sections 2.4.2 and 2.6.2 for more details. The phase/frequency detectors have a detec­tion range of −2π to +2π. The phase/frequency detectors also receive a feedback signal from the charge pump in order to eliminate dead zone.
Notes:
1. The minimum width of the pump-up and pump-down current pulses occur at the D
2. The diagram assumes positive VCO characteristics, i.e. PD_POL RF1 or PD_POL RF2 = 1.
is the phase detector input from the reference divider (R counter).
3. F
r
is the phase detector input from the programmable feedback divder (N counter).
4. F
p
refers to either the RF1 or RF2 charge pump output.
5. D
o
1.6 CHARGE PUMPS
The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards V
RF1 or VPRF2 during pump-up events and
P
towards GND during pump-down events. When locked, D RF1 or DoRF2 are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling the ID
RF1 or IDoRF2 control bits.
o
1.7 MICROWIRE SERIAL INTERFACE
The programmable register set is accessed via the MI­CROWIRE serial interface. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control regis­ter address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description.
o
1.8 MULTI-FUNCTION OUTPUTS
The F configured as the RF1 FastLock output, a push-pull analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feed­back divider (N counter) circuits. The F used to select the desired output function. When the PLL is in powerdown mode, the F state. A complete programming description of the multi-function output is provided in Section 2.8 F
1.8.1 Push-Pull Analog Lock Detect Output
An analog lock detect status generated from the phase detector is available on the F lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is a push-pull con­figuration.
Three separate lock detect signals are routed to the multi­plexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the RF1 and RF2 synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to
Section 2.8 F
lock detect options.
10136785
RF1 or DoRF2 pins when the loop is phase locked.
o
LD output pin is a multi-function output that can be
o
LD control word is
o
LD output is pulled to a LOW
o
LD.
o
LD output pin if selected. The
o
LD for details on how to program the different
o
www.national.com 34
1.0 Functional Description (Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response time during lock aquisition. The loop response time (lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain/ phase relationship at twice the loop bandwidth must be maintained. This can be achieved by increasing the charge pump current from 0.95 mA (ID
3.8 mA (ID
o
is configured as a FastLock output, an open drain device is enabled. The open drain device switches in a parallel resis­tor R2’ to ground, of equal value to resistor R2 of the external loop filter. The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the PLL will return to a steady state condition. Refer to
Section 2.8 F
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When the F
LD is programmed to Reset RF2 Counters, both the
o
RF2 feedback divider and the RF2 reference divider are held at their load point. When the Reset RF1 Counters is pro­grammed, both the RF1 feedback divider and the RF1 ref­erence divider are held at their load point. When the Reset All Counters mode is enabled, all feedback dividers and reference dividers are held at their load point. When the device is programmed to normal operation, both the feed­back divider and reference divider are enabled and resume counting in ‘close’ alignment to each other. Refer to Section
LD for more details.
2.8 F
o
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R dividers can be moni­tored by selecting the appropriate F tial when performing OSC Refer to the Test Setups section for more details. Refer to
Section 2.8 F
appropriate divider output to the F
RF1 Bit = 0) in the steady state mode, to
o
RF1 Bit = 1) in Fastlock. When the FoLD output
LD for details on how to configure the FoLD
o
LD word. This is essen-
o
or fINsensitivity measurements.
in
LD for more details on how to route the
o
LD pin.
o
1.9 POWER CONTROL
Each synthesizer in the LMX2335U or LMX2336U is indi­vidually power controlled by device powerdown bits. The powerdown word is comprised of the PWDN RF1 (PWDN RF2) bit, in conjuction with the TRI-STATE ID (TRI-STATE ID
RF2) bit. The powerdown control word is
o
RF1
o
used to set the operating mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4, and 2.7.4 for details on how to program the RF1 or RF2 powerdown bits.
When either the RF1 synthesizer or the RF2 synthesizer enters the powerdown mode, the respective prescaler, phase detector, and charge pump circuit are disabled. The
RF1 (DoRF2), fINRF1 (fINRF2), and fINRF1 (fINRF2)
D
o
pins are all forced to a high impedance state. The reference divider and feedback divider circuits are held at the load point during powerdown. The oscillator buffer is disabled when both the RF1 and RF2 synthesizers are powered down. The OSC
pin is forced to a HIGH state through an
in
approximate 100 kΩ resistance when this condition exists. When either synthesizer is activated, the respective pres­caler, phase detector, charge pump circuit, and the oscillator buffer are all powered up. The feedback divider, and the reference divider are held at load point. This allows the reference oscillator, feedback divider, reference divider and prescaler circuitry to reach proper bias levels. After a finite delay, the feedback and reference dividers are enabled and they resume counting in ‘close’ alignment (the maximum error is one prescaler cycle). The MICROWIRE control reg­ister remains active and capable of loading and latching data while in the powerdown mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge pump. When the device is configured for synchronous pow­erdown, the device will enter the powerdown mode upon completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the completion of a charge pump pulse event. When the device is configured for asynchronous powerdown, the part will go into powerdown mode immediately.
LMX2335U/LMX2336U
TRI-STATE ID
o
PWDN Operating Mode
0 0 PLL Active, Normal Operation
1 0 PLL Active, Charge Pump Output in High Impedance State
0 1 Synchronous Powerdown
1 1 Asynchronous Powerdown
Notes:
1. TRI-STATE ID
refers to either the TRI-STATE IDoRF1 or TRI-STATE IDoRF2 bit .
o
2. PWDN refers to either the PWDN RF1 or PWDN RF2 bit.
www.national.com35
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bit Data[19:0] Field and a 2-bit Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE
transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address bits. The MSB of Data is loaded in first. The Data Field assignments are shown in Section 2.3 CONTROL REGISTER CONTENT
MAP.
LMX2335U/LMX2336U
2.2 CONTROL REGISTER LOCATION
The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into the target control register.
2.3 CONTROL REGISTER CONTENT MAP
The control register content map describes how the bits within each control register are allocated to specific control functions.
MSB LSB
Data[19:0] Address[1:0]
21 2 1 0
Address[1:0] Target
Field Register
0 0 RF2 R
0 1 RF2 N
1 0 RF1 R
1 1 RF1 N
www.national.com 36
Field
LMX2335U/LMX2336U
Data Field Address
PD_
ID
RF2 R_CNTR[14:0] 0 0
RF2
POL
o
RF2
o
ID
RF2
STAT E
PD_
o
ID
RF1 R_CNTR[14:0] 1 0
POL
RF1
STAT E
RF1
o
ID
RF1
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit
2.0 Programming Description (Continued)
LD2 TRI-
o
LD0 F
o
F
RF2
LD3 TRI-
o
RF2 RF2 N_CNTRB[10:0] RF2 N_CNTRA[6:0] 0 1
PRE
LD1 F
o
RF2
PWDN
R
RF2
F
N
RF1
R
RF1 RF1 N_CNTRB[10:0] RF1 N_CNTRA[6:0] 1 1
PRE
RF1
PWDN
N
RF1
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2.0 Programming Description (Continued)
2.4 RF2 R REGISTER
The RF2 R register contains the RF2 R_CNTR, PD_POL RF2, ID bits that compose the F
LD control word. The detailed description and programming information for each control word is
o
discussed in the following sections. RF2 R_CNTR[14:0]
Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit
LMX2335U/LMX2336U
2120191817161514131211109876543210
Data Field
RF2
R
FoLD0 FoLD2
TRI-
STAT E
ID
RF2
o
ID
RF2
PD_
o
POL
RF2
2.4.1 RF2 R_CNTR[14:0] RF2 SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF2 R[2:16]
The RF2 reference divider (RF2 R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited.
Divide Ratio RF2 R_CNTR[14:0]
14131211109876543210
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 111111111111111
RF2, and TRI-STATE IDoRF2 control words, in addition to two
o
Address
RF2 R_CNTR[14:0] 0 0
Field
2.4.2 PD_POL RF2 RF2 SYNTHESIZER PHASE DETECTOR POLARITY RF2 R[17]
The PD_POL RF2 bit is used to control the RF2 synthesizer’s phase detector polarity based on the VCO tuning characteristics.
Control Bit Register Location Description Function
01
PD_POL RF2 RF2 R[17] RF2 Phase Detector
Polarity
RF2 VCO Negative Tuning Characteristics
RF2 VCO Positive Tuning Characteristics
RF2 VCO Characteristics
10136786
2.4.3 IDoRF2 RF2 SYNTHESIZER CHARGE PUMP CURRENT GAIN RF2 R[18]
The ID
RF2 bit controls the RF2 synthesizer’s charge pump gain. Two current levels are available.
o
Control Bit Register Location Description Function
01
ID
RF2 RF2 R[18] RF2 Charge Pump
o
Current Gain
LOW
0.95 mA
HIGH
3.80 mA
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2.0 Programming Description (Continued)
LMX2335U/LMX2336U
2.4.4 TRI-STATE ID
The TRI-STATE ID output state. This happens asynchronously with the change in the TRI-STATE ID
Furthermore, the TRI-STATE ID
RF2 RF2 SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF2 R[19]
o
RF2 bit allows the charge pump to be switched between a normal operating mode and a high impedance
o
RF2 bit operates in conjuction with the PWDN RF2 bit to set a synchronous or an asynchronous
o
RF2 bit.
o
powerdown mode.
Control Bit Register Location Description Function
01
TRI-STATE ID
RF2 RF2 R[19] RF2 Charge Pump
o
TRI-STATE Current
RF2 Charge Pump Normal Operation
RF2 Charge Pump Output in High Impedance State
2.5 RF2 N REGISTER
The RF2 N register contains the RF2 N_CNTRA, RF2 N_CNTRB, PRE RF2, and PWDN RF2 control words. The RF2 N_CNTRA and RF2 N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections.
Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit
2120191817161514131211109876543210
Address
Field
RF2
N
PWDN
RF2
PRE
RF2
Data Field
RF2 N_CNTRB[10:0] RF2 N_CNTRA[6:0] 0 1
2.5.1 RF2 N_CNTRA[6:0] RF2 SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF2 N[2:8]
The RF2 N_CNTRA control word is used to setup the RF2 synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF2 N_CNTRA control word can be programmed to values ranging from 0 to 127.
Divide Ratio RF2 N_CNTRA[6:0]
6543210
00000000
10000001
••••••••
1271111111
2.5.2 RF2 N_CNTRB[10:0] RF2 SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF2 N[9:19]
The RF2 N_CNTRB control word is used to setup the RF2 synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF2 N_CNTRB control word can be programmed to values ranging from 3 to 2047.
Divide
Ratio
109876543210
RF2 N_CNTRB[10:0]
300000000011
400000000100
••••••••••••
2047 11111111111
2.5.3 PRE RF2 RF2 SYNTHESIZER PRESCALER SELECT RF2 N[20]
The RF2 synthesizer utilizes a selectable dual modulus prescaler.
Control Bit Register Location Description Function
01
PRE RF2 RF2 N[20] RF2 Prescaler Select 64/65 Prescaler
Selected
128/129 Prescaler Selected
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2.0 Programming Description (Continued)
2.5.4 PWDN RF2 RF2 SYNTHESIZER POWERDOWN RF2 N[21]
The PWDN RF2 bit is used to switch the RF2 PLL between a powered up and powered down mode. Furthermore, the PWDN RF2 bit operates in conjuction with the TRI-STATE ID
powerdown mode.
Control Bit Register Location Description Function
LMX2335U/LMX2336U
PWDN RF2 RF2 N[21] RF2 Powerdown RF2 PLL Active RF2 PLL Powerdown
2.6 RF1 R REGISTER
The RF1 R register contains the RF1 R_CNTR, PD_POL RF1, ID bits that compose the F
LD control word. The detailed description and programming information for each control word is
o
discussed in the following sections.
Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit
2120191817161514131211109876543210
Data Field
RF1
R
FoLD1 FoLD3
TRI-
STAT E
ID
RF1
PD_
ID
o
POL
RF1
o
RF1
2.6.1 RF1 R_CNTR[14:0] RF1 SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF1 R[2:16]
The RF1 reference divider (RF1 R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited.
RF1, and TRI-STATE IDoRF1 control words, in addition to two
o
RF1 R_CNTR[14:0] 1 0
RF2 bit to set a synchronous or an asynchronous
o
01
Address
Field
Divide Ratio RF1 R_CNTR[14:0]
14131211109876543210
3 000000000000011
4 000000000000100
• •••••••••••••••
32767 111111111111111
2.6.2 PD_POL RF1 RF1 SYNTHESIZER PHASE DETECTOR POLARITY RF1 R[17]
The PD_POL RF1 bit is used to control the RF1 synthesizer’s phase detector polarity based on the VCO tuning characteristics.
Control Bit Register Location Description Function
01
PD_POL RF1 RF1 R[17] RF1 Phase Detector
Polarity
RF1 VCO Negative Tuning Characteristics
RF1 VCO Positive Tuning Characteristics
RF1 VCO Characteristics
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10136782
2.0 Programming Description (Continued)
LMX2335U/LMX2336U
2.6.3 ID
The ID
RF1 RF1 SYNTHESIZER CHARGE PUMP CURRENT GAIN RF1 R[18]
o
RF1 bit controls the RF1 synthesizer’s charge pump gain. Two current levels are available.
o
Control Bit Register Location Description Function
01
ID
RF1 RF1 R[18] RF1 Charge Pump
o
Current Gain
2.6.4 TRI-STATE ID
The TRI-STATE ID
RF1 RF1 SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF1 R[19]
o
RF1 bit allows the charge pump to be switched between a normal operating mode and a high impedance
o
output state. This happens asynchronously with the change in the TRI-STATE ID Furthermore, the TRI-STATE ID
RF1 bit operates in conjuction with the PWDN RF1 bit to set a synchronous or an asynchronous
o
RF1 bit.
o
LOW
0.95 mA
HIGH
3.80 mA
powerdown mode.
Control Bit Register Location Description Function
01
TRI-STATE ID
RF1 RF1 R[19] RF1 Charge Pump
o
TRI-STATE Current
RF1 Charge Pump Normal Operation
RF1 Charge Pump Output in High Impedance State
2.7 RF1 N REGISTER
The RF1 N register contains the RF1 N_CNTRA, RF1 N_CNTRB, PRE RF1, and PWDN RF1 control words. The RF1 N_CNTRA and RF1 N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections.
Reg. Most Significant Bit SHIFT REGISTER BIT LOCATION Least Significant Bit
2120191817161514131211109876543210
Address
Field
RF1
N
PWDN
RF1
PRE
RF1
Data Field
RF1 N_CNTRB[10:0] RF1 N_CNTRA[6:0] 1 1
2.7.1 RF1 N_CNTRA[6:0] RF1 SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF1 N[2:8]
The RF1 N_CNTRA control word is used to setup the RF1 synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF1 N_CNTRA control word can be programmed to values ranging from 0 to 127.
Divide Ratio RF1 N_CNTRA[6:0]
6543210
00000000
10000001
••••••••
1271111111
2.7.2 RF1 N_CNTRB[10:0] RF1 SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF1 N[9:19]
The RF1 N_CNTRB control word is used to setup the RF1 synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF1 N_CNTRB control word can be programmed to values ranging from 3 to 2047.
Divide
Ratio
109876543210
RF1 N_CNTRB[10:0]
300000000011
400000000100
••••••••••••
2047 11111111111
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2.0 Programming Description (Continued)
2.7.3 PRE RF1 RF1 SYNTHESIZER PRESCALER SELECT RF1 N[20]
The RF1 synthesizer utilizes a selectable dual modulus prescaler.
Control Bit Register Location Description Function
01
PRE RF1 RF1 N[20] RF1 Prescaler Select 64/65 Prescaler
LMX2335U/LMX2336U
2.7.4 PWDN RF1 RF1 SYNTHESIZER POWERDOWN RF1 N[21]
The PWDN RF1 bit is used to switch the RF1 PLL between a powered up and powered down mode. Furthermore, the PWDN RF1 bit operates in conjuction with the TRI-STATE ID
powerdown mode.
Control Bit Register Location Description Function
PWDN RF1 RF1 N[21] RF1 Powerdown RF1 PLL Active RF1 PLL Powerdown
Selected
RF1 bit to set a synchronous or an asynchronous
o
01
128/129 Prescaler Selected
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2.0 Programming Description (Continued)
2.8 F
LD[3:0] MULTI-FUNCTION OUTPUT SELECT [RF1 R[20], RF2 R[20], RF1 R [21], RF2 R[21]]
o
LD control word is used to select which signal is routed to the FoLD pin.
The F
o
FoLD3 FoLD2 FoLD1 FoLD0 FoLD Output State
0 0 0 0 LOW Logic State Output
0 0 0 1 RF2 PLL R Divider Output, Push-Pull Output
0 0 1 0 RF1 PLL R Divider Output, Push-Pull Output
0 0 1 1 Open Drain Fastlock Output
0 1 0 0 RF2 PLL Analog Lock Detect, Push-Pull Output
0 1 0 1 RF2 PLL N Divider Output, Push-Pull Output
0 1 1 0 RF1 PLL N Divider Output, Push-Pull Output
0 1 1 1 Reset RF2 Counters, LOW Logic State Output
1 0 0 0 RF1 Analog Lock Detect, Push-Pull Output
1 0 0 1 RF2 PLL R Divider Output, Push-Pull Output
1 0 1 0 RF1 PLL R Divider Output, Push-Pull Output
1 0 1 1 Reset RF1 Counters, LOW Logic State Output
1 1 0 0 RF1 and RF2 Analog Lock Detect, Push-Pull Output
1 1 0 1 RF2 PLL N Divider Output, Push-Pull Output
1 1 1 0 RF1 PLL N Divider Output, Push-Pull Output
1 1 1 1 Reset All Counters, LOW Logic State Output
LMX2335U/LMX2336U
www.national.com43
Physical Dimensions inches (millimeters)
unless otherwise noted
LMX2335U/LMX2336U
16-Pin Thin Shrink Small Outline Package (TM)
NS Package Number MTC16
www.national.com 44
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LMX2335U/LMX2336U
20-Pin Thin Shrink Small Outline Package (TM)
NS Package Number MTC20
www.national.com45
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LMX2335U/LMX2336U
16-Pin Chip Scale Package (SLB)
NS Package Number SLB16A
www.national.com 46
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LMX2335U/LMX2336U
24-Pin Chip Scale Package (SLB)
NS Package Number SLB24A
www.national.com47
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Communications
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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LMX2335U/LMX2336U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal
www.national.com
National Semiconductor Corporation
Americas Email: support@nsc.com
20-Pin Ultra Thin Chip Scale Package (SLE)
NS Package Number SLE20A
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790
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