National Semiconductor LMX2335U, LMX2336U Technical data
查询LMX2335U供应商
LMX2335U/LMX2336U
November 2002
LMX2335U/LMX2336U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal
Communications
PLLatinum
™
Ultra Low Power Dual Frequency
Synthesizer for RF Personal Communications
LMX2335U 1.2 GHz/1.2 GHz
LMX2336U 2.0 GHz/1.2 GHz
General Description
The LMX2335U and LMX2336U devices are high performance frequency synthesizers with integrated dual modulus
prescalers. The LMX2335U and LMX2336U devices are
designed for use in applications requiring two RF
phase-locked loops.
A 64/65 or a 128/129 prescale ratio can be selected for each
RF synthesizer. Using a proprietary digital phase locked loop
technique, the LMX2335U and LMX2336U devices generate
very stable, low noise control signals for the RF voltage
controlled oscillators. Both RF synthesizers include a
two-level programmable charge pump. The RF1 synthesizer
has dedicated Fastlock circuitry.
Serial data is transferred to the devices via a three wire
interface (Data, LE, Clock). Supply voltages from 2.7V to
5.5V are supported. The LMX2335U and the LMX2336U
feature very low current consumption:
LMX2335U (1.2 GHz)– 3.0 mA, LMX2336U (2.0 GHz)–
3.5 mA at 3.0V.
The LMX2335U device is available in 16-pin TSSOP, and
16-pin Chip Scale Package (CSP) surface mount plastic
packages. The LMX2336U device is available in 20-Pin
TSSOP, 24-Pin CSP, and 20-Pin UTCSP surface mount
plastic packages.
Features
n Ultra Low Current Consumption
n Upgrade and Compatible to the LMX2335L and
LMX2336L devices
n 2.7V to 5.5V operation
n Selectable Synchronous or Asynchronous Powerdown
Mode:
I
CC-PWDN
n Selectable Dual Modulus Prescaler
RF1: 64/65 or 128/129
RF2: 64/65 or 128/129
n Selectable Charge Pump TRI-STATE
n Programmable Charge Pump Current Levels
RF1 and RF2: 0.95 or 3.8 mA
n Selectable Fastlock
n Push-Pull Analog Lock Detect Mode
n LMX2335U is available in 16-Pin TSSOP and 16-Pin
CSP
n LMX2336U is available in 20-Pin TSSOP, 24-Pin CSP,
and 20-Pin UTCSP
= 1 µA typical at 3.0V
™
Mode for the RF1 Synthesizer
Applications
n Mobile Handsets
(GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC,
DCS)
n Cordless Handsets (DECT, DCT)
n Wireless Data
n Cable TV Tuners
®
Mode
Thin Shrink Small Outline Package (MTC16) Thin Shrink Small Outline Package (MTC20)
10136787
Ultra Thin Chip Scale Package
Chip Scale Package (SLB16A) Chip Scale Package (SLB24A)
10136788
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
Fastlock
, MICROWIRE™and PLLatinum™are trademarks of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation DS101367 www.national.com
10136781
10136780
(SLE20A)
10136795
LMX2335U Functional Block Diagram
LMX2335U/LMX2336U
LMX2336U Functional Block Diagram
10136789
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10136701
Connection Diagrams
LMX2335U/LMX2336U
LMX2335U Thin Shrink Small Outline Package (TM)
(Top View)
10136702
LMX2336U Thin Shrink Small Outline Package (TM)
(Top View)
LMX2335U Chip Scale Package (SLB)
(Top View)
10136738
LMX2336U Chip Scale Package (SLB)
(Top View)
10136703
LMX2336U Ultra Thin Chip Scale Package (SLE)
(Top View)
10136796
10136736
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Pin Descriptions
Pin No.
Pin
LMX2336U
Name
20-Pin
UTCSP
V
CC
20 1 24 1 16 – Power supply bias for the RF1 PLL analog and
LMX2335U/LMX2336U
Pin No.
LMX2336U
20-Pin
TSSOP
Pin No.
LMX2336U
24-Pin
CSP
Pin No.
LMX2335U
16-Pin
TSSOP
Pin No.
LMX2335U
16-Pin
CSP
I/O Description
digital circuits. V
may range from 2.7V to
CC
5.5V. Bypass capacitors should be placed as
close as possible to this pin and be connected
directly to the ground plane.
V
P
RF1
D
RF1
o
1 2 2 2 1 – RF1 PLL charge pump power supply. Must be ≥
VCC.
2 3 3 3 2 O RF1 PLL charge pump output. The output is
connected to the external loop filter, which drives
the input of the VCO.
GND 3 4 4 4 3 – LMX2335U: Ground for the RF1 PLL analog and
digital circuits.
LMX2336U: Ground for the RF1 PLL digital
circuitry.
RF1 4 5 5 5 4 I RF1 PLL prescaler input. Small signal input from
f
IN
the VCO.
fINRF1 5 6 6 X X I LMX2335U: Don’t care.
LMX2336U: RF1 PLL prescaler complementary
input. For single ended operation, this pin should
be AC grounded. The LMX2336U RF1 PLL can
be driven differentially when the bypass
capacitor is omitted.
GND 6 7 7 X X – LMX2335U: Don’t care.
LMX2336U: Ground for the RF1 PLL analog
circuitry.
OSC
in
7 8 8 6 5 I Oscillator input. It has an approximate VCC/2
input threshold and can be driven from an
external CMOS or TTL logic gate.
OSC
out
8 9 10 7 6 O Oscillator output. This output is connected
directly to a crystal. If a TCXO is used, it is left
open.
LD 9 10 11 8 7 O Programmable multiplexed output pin. Functions
F
o
as a general purpose CMOS TRI-STATE output,
RF1/RF2 PLL push-pull analog lock detect
output, N and R divider output, or Fastlock
output, which connects a parallel resistor to the
external loop filter.
Clock 10 11 12 9 8 I MICROWIRE Clock input. High impedance
CMOS input. Data is clocked into the 22-bit shift
register on the rising edge of Clock.
Data 11 12 14 10 9 I MICROWIRE Data input. High impedance
CMOS input. Binary serial data. The MSB of
Data is entered first. The last two bits are the
control bits.
LE 12 13 15 11 10 I MICROWIRE Latch Enable input. High
impedance CMOS input. When LE transitions
HIGH, Data stored in the shift registers is loaded
into one of 4 internal control registers.
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Pin Descriptions (Continued)
LMX2335U/LMX2336U
Pin
Name
Pin No.
LMX2336U
20-Pin
UTCSP
Pin No.
LMX2336U
20-Pin
TSSOP
Pin No.
LMX2336U
24-Pin
CSP
Pin No.
LMX2335U
16-Pin
TSSOP
Pin No.
LMX2335U
16-Pin
CSP
I/O Description
GND 13 14 16 X X – LMX2335U: Don’t care.
LMX2336U: Ground for the RF2 PLL analog
circuitry.
RF2 14 15 17 X X I LMX2335U: Don’t care.
f
IN
LMX2336U: RF2 PLL prescaler complementary
input. For single ended operation, this pin should
be AC grounded. The LMX2336U RF2 PLL can
be driven differentially when the bypass
capacitor is omitted.
RF2 15 16 18 12 11 I RF2 PLL prescaler input. Small signal input from
f
IN
the VCO.
GND 16 17 19 13 12 − LMX2335U: Ground for the RF2 PLL analog and
digital circuits, MICROWIRE, F
LD and oscillator
o
circuits. LMX2336U: Ground for the RF2 PLL
digital circuitry, MICROWIRE, F
LD and
o
oscillator circuits.
D
RF2
o
17 18 20 14 13 O RF2 PLL charge pump output. The output is
connected to the external loop filter, which drives
the input of the VCO.
V
RF2
V
CC
P
18 19 22 15 14 – RF2 PLL charge pump power supply. Must be ≥
VCC.
19 20 23 16 15 – Power supply bias for the RF2 PLL analog and
digital circuits, MICROWIRE, F
circuits. V
may range from 2.7V to 5.5V.
CC
LD and oscillator
o
Bypass capacitors should be placed as close as
possible to this pin and be connected directly to
the ground plane.
NC X X 1, 9, 13,
21
X X – LMX2335U: Don’t Care.
LMX2336U: No connect.
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Ordering Information
Model Temperature Range Package Description Packing NS Package Number
LMX2335USLBX −40˚C to +85˚C Chip Scale Package
LMX2335UTM −40˚C to +85˚C Thin Shrink Small
LMX2335U/LMX2336U
LMX2335UTMX −40˚C to +85˚C Thin Shrink Small
LMX2336USLEX −40˚C to +85˚C Ultra Thin Chip Scale
LMX2336USLBX −40˚C to +85˚C Chip Scale Package
LMX2336UTM −40˚C to +85˚C Thin Shrink Small
LMX2336UTMX −40˚C to +85˚C Thin Shrink Small
2500 Units Per Reel SLB16A
(CSP) Tape and Reel
96 Units Per Rail MTC16
Outline Package
(TSSOP)
2500 Units Per Reel MTC16
Outline Package
(TSSOP) Tape and
Reel
2500 Units Per Reel SLE20A
Package (UTCSP)
Tape and Reel
2500 Units Per Reel SLB24A
(CSP) Tape and Reel
73 Units Per Rail MTC20
Outline Package
(TSSOP)
2500 Units Per Reel MTC20
Outline Package
(TSSOP) Tape and
Reel
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Detailed Block Diagram
LMX2335U/LMX2336U
Notes:
supplies power to the RF1 and RF2 prescalers, RF1 and RF2 feedback dividers, RF1 and RF2 reference dividers, RF1 and RF2 phase detectors, the
1. V
CC
OSC
buffer, MICROWIRE, and FoLD circuits.
in
RF1 and VPRF2 supply power to the charge pumps. They can be run separately as long as VPRF1 ≥ VCCand VPRF2 ≥ VCC.
2. V
P
3. X signifies a pin that is NOT available on the LMX2335U PLL.
10136704
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Absolute Maximum Ratings (Notes 1,
2, 3)
16-Pin CSP θ
24-Pin CSP θ
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Power Supply Voltage
V
to GND −0.3V to +6.5V
LMX2335U/LMX2336U
CC
V
RF1 to GND −0.3V to +6.5V
P
V
RF2 to GND −0.3V to +6.5V
P
Voltage on any pin to GND (V
V
must be<+6.5V −0.3V to VCC+0.3V
I
Storage Temperature Range (T
Lead Temperature (solder 4 s) (T
16-Pin TSSOP θ
Thermal
JA
)
I
) −65˚C to +150˚C
S
) +260˚C
L
Impedance 137.1˚C/W
20-Pin TSSOP θJAThermal
Impedance 114.5˚C/W
Power Supply Voltage
Operating Temperature (T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
rating
should only be done at ESD protected work stations.
Note 3: GND=0V
Electrical Characteristics
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
I
PARAMETERS
CC
I
CC
RF1 + RF2
I
CC
RF1
I
CC
RF2
I
CC-PWDN
RF1 SYNTHESIZER PARAMETERS
RF1 RF1 Operating
f
IN
N
RF1
R
RF1
F
φRF1
Pf
RF1 RF1 Input Sensitivity 2.7V ≤ VCC≤ 3.0V
IN
Power Supply
Current, RF1 + RF2
Synthesizers
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 3.5 4.5 mA
PWDN RF1 Bit = 0
PWDN RF2 Bit = 0
Power Supply
Current, RF1
Synthesizer Only
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 2.0 2.5 mA
PWDN RF1 Bit = 0
PWDN RF2 Bit = 1
Power Supply
Current, RF2
Synthesizer Only
LMX2335U Clock, Data and LE = GND
= GND
OSC
in
LMX2336U 1.5 2.0
PWDN RF1 Bit = 1
PWDN RF2 Bit = 0
Powerdown Current LMX2335U/ Clock, Data and LE = GND
= GND
OSC
in
LMX2336U
PWDN RF1 Bit = 1
PWDN RF2 Bit = 1
LMX2335U 100 1200 MHz
Frequency
LMX2336U 200 2000 MHz
RF1 N Divider Range Prescaler = 64/65
(Note 4)
Prescaler = 128/129
(Note 4)
RF1 R Divider Range 3 32767
RF1 Phase Detector Frequency 10 MHz
(Note 5)
<
VCC≤ 5.5V
3.0V
(Note 5)
Thermal Impedance 130˚C/W
JA
Thermal Impedance 112˚C/W
JA
(Note 1)
V
to GND +2.7V to +5.5V
CC
V
RF1 to GND VCCto +5.5V
P
V
RF2 to GND VCCto +5.5V
P
) −40˚C to +85˚C
A
<
2 kV and is ESD sensitive. Handling and assembly of this device
Value
Min Typ Max
3.0 4.0 mA
1.5 2.0 mA
1.5 2.0 mA
1.0 10.0 µA
192 131135
384 262143
−15 0 dBm
−10 0 dBm
Units
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
RF1 SYNTHESIZER PARAMETERS
ID
RF1
o
SOURCE
RF1
ID
o
SINK
RF1
ID
o
TRI-STATE
IDoRF1
SINK
Vs
RF1
ID
o
SOURCE
RF1
ID
o
Vs
RF1
VD
o
RF1
ID
o
Vs
T
A
RF2 SYNTHESIZER PARAMETERS
RF2 RF2 Operating
f
IN
N
RF2
R
RF2
F
φRF2
Pf
RF2 RF2 Input Sensitivity 2.7V ≤ VCC≤ 3.0V
IN
RF1 Charge Pump Output Source
Current
VDoRF1=VPRF1/2
RF1 Bit = 0
ID
o
(Note 6)
RF1=VPRF1/2
VD
o
RF1 Bit = 1
ID
o
(Note 6)
RF1 Charge Pump Output Sink
Current
VDoRF1=VPRF1/2
RF1 Bit = 0
ID
o
(Note 6)
RF1=VPRF1/2
VD
o
RF1 Bit = 1
ID
o
(Note 6)
RF1 Charge Pump Output TRI-STATE
Current
RF1 Charge Pump Output Sink
Current Vs Charge Pump Output
Source Current Mismatch
RF1 Charge Pump Output Current
Magnitude Variation Vs Charge Pump
Output Voltage
RF1 Charge Pump Output Current
Magnitude Variation Vs Temperature
0.5V ≤ VDoRF1 ≤ VPRF1 - 0.5V
(Note 6)
RF1=VPRF1/2
VD
o
= +25˚C
T
A
(Note 7)
0.5V ≤ VD
= +25˚C
T
A
RF1 ≤ VPRF1 - 0.5V
o
(Note 7)
VDoRF1=VPRF1/2
(Note 7)
LMX2335U 100 1200 MHz
Frequency
LMX2336U 100 1200 MHz
RF2 N Divider Range Prescaler = 64/65
(Note 4)
Prescaler = 128/129
(Note 4)
RF2 R Divider Range 3 32767
RF2 Phase Detector Frequency 10 MHz
(Note 5)
3.0V<VCC≤ 5.5V
(Note 5)
Value
Min Typ Max
Units
-0.95 mA
-3.80 mA
0.95 mA
3.80 mA
-2.5 2.5 nA
310%
10 15 %
10 %
192 131135
384 262143
-15 0 dBm
-10 0 dBm
LMX2335U/LMX2336U
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
RF2 SYNTHESIZER PARAMETERS
ID
RF2
o
SOURCE
LMX2335U/LMX2336U
RF2
ID
o
SINK
RF2
ID
o
TRI-STATE
IDoRF2
SINK
Vs
RF2
ID
o
SOURCE
RF2
ID
o
Vs
RF2
VD
o
RF2
ID
o
Vs
T
A
OSCILLATOR PARAMETERS
F
OSC
V
OSC
I
OSC
DIGITAL INTERFACE (Data, LE, Clock, F
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
MICROWIRE INTERFACE
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
RF2 Charge Pump Output Source
Current
VDoRF2=VPRF2/2
RF2 Bit = 0
ID
o
(Note 6)
RF2=VPRF2/2
VD
o
RF2 Bit = 1
ID
o
(Note 6)
RF2 Charge Pump Output Sink
Current
VDoRF2=VPRF2/2
RF2 Bit = 0
ID
o
(Note 6)
RF2= VPRF2/2
VD
o
RF2 Bit = 1
ID
o
(Note 6)
RF2 Charge Pump Output TRI-STATE
Current
RF2 Charge Pump Output Sink
Current Vs Charge Pump Output
Source Current Mismatch
RF2 Charge Pump Output Current
Magnitude Variation Vs Charge Pump
Output Voltage
RF2 Charge Pump Output Current
Magnitude Variation Vs Temperature
0.5V ≤ VDoRF2 ≤ VPRF2 - 0.5V
(Note 6)
RF2=VPRF2/2
VD
o
= +25˚C
T
A
(Note 7)
0.5V ≤ VD
= +25˚C
T
A
RF2 ≤ VPRF2 - 0.5V
o
(Note 7)
VDoRF2=VPRF2/2
(Note 7)
Oscillator Operating Frequency 2 40 MHz
Oscillator Sensitivity (Note 8) 0.5 V
Oscillator Input Current V
LD)
o
OSC=VCC
V
OSC
= 5.5V 100 µA
= 0V, VCC= 5.5V -100 µA
High-Level Input Voltage 0.8 V
Low-Level Input Voltage 0.2 V
High-Level Input Current VIH=VCC= 5.5V −1.0 1.0 µA
Low-Level Input Current VIL= 0V, VCC= 5.5V −1.0 1.0 µA
High-Level Output Voltage IOH= −500 µA VCC−
Low-Level Output Voltage IOL= 500 µA 0.4 V
Data to Clock Set Up Time (Note 9) 50 ns
Data to Clock Hold Time (Note 9) 10 ns
Clock Pulse Width HIGH (Note 9) 50 ns
Clock Pulse Width LOW (Note 9) 50 ns
Clock to Load Enable Set Up Time (Note 9) 50 ns
Latch Enable Pulse Width (Note 9) 50 ns
Value
Min Typ Max
Units
-0.95 mA
-3.80 mA
0.95 mA
3.80 mA
-2.5 2.5 nA
310%
10 15 %
10 %
V
CC
CC
CC
0.4
PP
V
V
V
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
PHASE NOISE CHARACTERISTICS
L
(f) RF1 RF1 Synthesizer Normalized Phase
N
Noise Contribution
(Note 10)
L(f) RF1 RF1 Synthesizer
LMX2335U f
Single Side Band
Phase Noise
Measured
LMX2336U f
TCXO Reference Source
RF1 Bit = 1
ID
o
RF1 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF1
Loop Bandwidth = 12 kHz
N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
PP
IDoRF1 Bit = 1
PWDN RF2 Bit = 1
= +25˚C
T
A
(Note 11)
RF1 = 1960 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF1
Loop Bandwidth = 15 kHz
N = 9800
=10MHz
F
OSC
= 0.632 V
V
OSC
PP
IDoRF1 Bit = 1
PWDN RF2 Bit = 1
= +25˚C
T
A
(Note 11)
Value
Min Typ Max
-212.0 dBc/
-85.94 dBc/
-79.18 dBc/
LMX2335U/LMX2336U
Units
Hz
Hz
Hz
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Electrical Characteristics (Continued)
VCC=VPRF1=VPRF2 = 3.0V, −40˚C ≤ TA≤ +85˚C, unless otherwise specified
Symbol Parameter Conditions
PHASE NOISE CHARACTERISTICS
L
(f) RF2 RF2 Synthesizer Normalized Phase
N
Noise Contribution
LMX2335U/LMX2336U
(Note 10)
L(f) RF2 RF2 Synthesizer
Single Side Band
Phase Noise
Measured
LMX2335U f
LMX2336U f
TCXO Reference Source
RF2 Bit = 1
ID
o
RF2 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF2
Loop Bandwidth = 12 kHz
N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
IDoRF2 Bit = 1
PWDN RF1 Bit = 1
= +25˚C
T
A
(Note 11)
RF2 = 900 MHz
IN
f = 1 kHz Offset
= 200 kHz
F
φRF2
Loop Bandwidth = 12 kHz
N = 4500
=10MHz
F
OSC
= 0.632 V
V
OSC
IDoRF2 Bit = 1
PWDN RF1 Bit = 1
= +25˚C
T
A
(Note 11)
Value
Min Typ Max
Units
-212.0 dBc/
Hz
-85.94 dBc/
Hz
PP
-85.94 dBc/
Hz
PP
Note 4: Some of the values in this range are illegal divide ratios (B<A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N
*
≥ P
(P−1), where P is the value selected for the prescaler.
Note 5: Refer to the LMX2335U and LMX2336U f
Note 6: Refer to the LMX2335U and LMX2336U Charge Pump Test Setup section
Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made.
Note 8: Refer to the LMX2335U and LMX2336U OSC
Note 9: Refer to the LMX2335U and LMX2336U Serial Data Input Timing section
Note 10: Normalized Phase Noise Contribution is defined as : L
measured at an offset frequency, f, ina1Hzbandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough
to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and F
comparison frequency..
Note 11: The synthesizer phase noise is measured with the LMX2335TMEB/LMX2335SLBEB or LMX2336TMEB/LMX2336SLBEB/LMX2336SLEEB Evaluation
boards and the HP8566B Spectrum Analyzer.
Sensitivity Test Setup section
IN
Sensitivity Test Setup section
in
(f) = L(f) − 20 log (N) − 10 log (Fφ), where L(f) is defined as the single side band phase noise
N
is the RF1/RF2 phase detector
φ
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Typical Performance Characteristics
Sensitivity
LMX2335U fINRF1 Input Power Vs Frequency
V
CC=VP
LMX2335U/LMX2336U
RF1 = 3.0V
LMX2335U fINRF1 Input Power Vs Frequency
V
CC=VP
RF1 = 5.5V
10136746
10136747
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Typical Performance Characteristics
Sensitivity
(Continued)
LMX2335U/LMX2336U
LMX2336U f
RF1 Input Power Vs Frequency
IN
V
CC=VP
RF1 = 3.0V
LMX2336U fINRF1 Input Power Vs Frequency
V
CC=VP
RF1 = 5.5V
10136744
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10136745
Typical Performance Characteristics
Sensitivity
(Continued)
LMX2335U/LMX2336U
LMX2335U and LMX2336U f
V
CC=VP
RF2 Input Power Vs Frequency
IN
RF2 = 3.0V
LMX2335U and LMX2336U fINRF2 Input Power Vs Frequency
V
CC=VP
RF2 = 5.5V
10136792
10136793
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