National Semiconductor LMK03000 Technical data

LMK03000 Family Precision Clock Conditioner with Integrated VCO

September 4, 2008

General Description

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family.

Target Applications

Data Converter Clocking

■

Networking, SONET/SDH, DSLAM

■

Wireless Infrastructure

■

Medical

■

Test and Measurement

■

Military / Aerospace

■

Features

Integrated VCO with very low phase noise floor

■

Integrated Integer-N PLL with outstanding normalized

■

phase noise contribution of -224 dBc/Hz VCO divider values of 2 to 8 (all divides)

■

Channel divider values of 1, 2 to 510 (even divides)

■

LVDS and LVPECL clock outputs

■

Partially integrated loop filter

■

Dedicated divider and delay blocks on each clock output

■

Pin compatible family of clocking devices

■

3.15 to 3.45 V operation

■

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

■

200 fs RMS Clock generator performance (10 Hz to 20

■

MHz) with a clean input clock

VCO

Device Outputs

LMK03000C

LMK03000 800

LMK03000D 1200

LMK03001C

LMK03001 800

LMK03001D 1200

LMK03033C

LMK03033 800

3 LVDS

5 LVPECL

4 LVDS

4 LVPECL

Tuning Range

(MHz)

1185 - 1296

1470 - 1570

1843 - 2160

RMS Jitter

(fs)

400

500

System Diagram

20211440

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

Functional Block Diagram

LMK03000 Family

20211401

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Connection Diagram

LMK03000 Family

48-Pin LLP Package

20211402

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Pin Descriptions

Pin # Pin Name I/O Description

1, 25 GND - Ground

2 Fout O Internal VCO Frequency Output

3, 8, 13, 16, 19, 22,

LMK03000 Family

26, 30, 31, 33, 37,

40, 43, 46

4 CLKuWire I MICROWIRE Clock Input

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE Latch Enable Input

7, 34, 35 NC - No Connection to these pins

9, 10 LDObyp1, LDObyp2 - LDO Bypass

11 GOE I Global Output Enable

12 LD O Lock Detect and Test Output

14, 15 CLKout0, CLKout0* O LVDS Clock Output 0

17, 18 CLKout1, CLKout1* O LVDS Clock Output 1

20, 21 CLKout2, CLKout2* O LVDS Clock Output 2

23, 24 CLKout3, CLKout3* O

27 SYNC* I Global Clock Output Synchronization

28, 29 OSCin, OSCin* I

32 CPout O Charge Pump Output

36 Bias I Bias Bypass

38, 39 CLKout4, CLKout4* O LVPECL Clock Output 4

41, 42 CLKout5, CLKout5* O LVPECL Clock Output 5

44, 45 CLKout6, CLKout6* O LVPECL Clock Output 6

47, 48 CLKout7, CLKout7* O LVPECLClock Output 7

DAP DAP - Die Attach Pad is Ground

Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, Vcc8, Vcc9, Vcc10,

Vcc11, Vcc12, Vcc13, Vcc14

- Power Supply

Clock Output 3 (LVDS for LMK03033C/LMK03033 LVPECL for all other parts)

Oscillator Clock Input; Should be AC coupled

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Parameter Symbol Ratings Units

Power Supply Voltage

Input Voltage

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

STG

-0.3 to 3.6 V

-0.3 to (VCC + 0.3)

-65 to 150 °C

+260 °C

125 °C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Ambient Temperature

Power Supply Voltage

Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.

-40 25 85 °C

3.15 3.3 3.45 V

LMK03000 Family

Package Thermal Resistance

Package

48-Lead LLP (Note 3) 27.4° C/W 5.8° C/W

Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.

J-PAD (Thermal Pad)

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Electrical Characteristics (Note 4)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; Vboost=0; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed).

Symbol Parameter Conditions Min Typ Max Units

LMK03000 Family

ICCPD

square

OSCin

square

OSCin

CPout

SRCE

CPout

SINK

TRI Charge Pump TRI-STATE® Current 0.5 V < V

CPout

%MIS

CPout

VTUNE

CPout

TEMP

CPout

PN10kHz

PN1Hz

Power Supply Current (Note 5)

Power Down Current POWERDOWN = 1 1 mA

Reference Oscillator Input Frequency Range for Square Wave

Square Wave Input Voltage for OSCin and OSCin*

Phase Detector Frequency 40 MHz

Charge Pump Source Current

Charge Pump Sink Current

Magnitude of Charge Pump Sink vs. Source Current Mismatch

Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation

Magnitude of Charge Pump Current vs. Temperature Variation

PLL 1/f Noise at 10 kHz Offset (Note 6) Normalized to 1 GHz Output Frequency

Normalized Phase Noise Contribution (Note 7)

Current Consumption

Entire device; one LVDS and one LVPECL clock enabled; no divide; no

161.8

delay.

Entire device; All Outputs Off (no emitter resistors placed)

Reference Oscillator

1 200 MHz

AC coupled; Differential (VOD)

0.2 1.6 Vpp

PLL

= Vcc/2, PLL_CP_GAIN = 1x

CPout

= Vcc/2, PLL_CP_GAIN = 4x

CPout

= Vcc/2, PLL_CP_GAIN = 16x

CPout

= Vcc/2, PLL_CP_GAIN = 32x

CPout

100

400

1600

3200

PLL (Continued)

= Vcc/2, PLL_CP_GAIN = 1x

CPout

= Vcc/2, PLL_CP_GAIN = 4x

CPout

= Vcc/2, PLL_CP_GAIN = 16x

CPout

= Vcc/2, PLL_CP_GAIN = 32x

CPout

< Vcc - 0.5 V

CPout

= Vcc / 2

CPout

TA = 25°C

0.5 V < V

< Vcc - 0.5 V

CPout

TA = 25°C

-100

-400

-1600

-3200

2 10 nA

3 %

4 %

PLL_CP_GAIN = 1x -117

PLL_CP_GAIN = 32x -122

PLL_CP_GAIN = 1x -219

PLL_CP_GAIN = 32x -224

µA

μA

dBc/Hz

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Symbol Parameter Conditions Min Typ Max Units

VCO

LMK03000C/LMK03000/LMK03000D 1185 1296

Fout

VCO Tuning Range

LMK03033C/LMK03033 1843 2160

After programming R15 for lock, no

|ΔTCL|

Allowable Temperature Drift for Continuous Lock

changes to output configuration are permitted to guarantee continuous

125 °C

lock. (Note 8)

LMK03000C/LMK03000/LMK03000D; TA = 25 °C

Fout

Output Power to a 50 Ω load driven by Fout (Note 10)

LMK03001C/LMK03001/LMK03001D; TA = 25 °C

LMK03033C/LMK03033;TA = 25 °C

3.3

2.7

-5 to 0

LMK03000C/LMK03000/LMK03000D 7 to 9

VCO

Fine Tuning Sensitivity (Note 9)

LMK03033C/LMK03033 14 to 26

LMK03000C/LMK03001C 400

LMK03000/LMK03001 800

LMK03000D/LMK03001D 1200

LMK03033C 500

RMS

Fout

Fout RMS Period Jitter (12 kHz to 20 MHz bandwidth)

LMK03033 800

10 kHz Offset -91.4

100 kHz Offset -116.8

1 MHz Offset -137.8

10 MHz Offset -156.9

10 kHz Offset -93.5

100 kHz Offset -118.5

1 MHz Offset -139.4

10 MHz Offset -158.4

10 kHz Offset -89.6

100 kHz Offset -115.2

1 MHz Offset -136.5

10 MHz Offset -156.0

10 kHz Offset -91.6

100 kHz Offset -116.0

1 MHz Offset -137.9

10 MHz Offset -156.2

10 kHz Offset -83

100 kHz Offset -109

1 MHz Offset -131

10 MHz Offset -152

10 kHz Offset -86

100 kHz Offset -111

1 MHz Offset -134

10 MHz Offset -153

L(f)

Fout

Fout Single Side Band Phase Noise

LMK03000C f

= 1296 MHz

Fout

(Note 11)

LMK03000C f

= 1185 MHz

Fout

(Note 11)

LMK03001C f

= 1570 MHz

Fout

(Note 11)

LMK03001C f

= 1470 MHz

Fout

(Note 11)

LMK03033C f

= 2160 MHz

Fout

(Note 11)

LMK03033C f

= 1843 MHz

Fout

(Note 11)

LMK03000 Family

MHzLMK03001C/LMK03001/LMK03001D 1470 1570

dBm

MHz/VLMK03001C/LMK03001/LMK03001D 9 to 11

dBc/Hz

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Symbol Parameter Conditions Min Typ Max Units

Clock Distribution Section (Notes 12, 13) - LVDS Clock Outputs

CLKoutX_MUX

Jitter

LMK03000 Family

ADD

Additive RMS Jitter (Note 12)

RL = 100 Ω Distribution Path = 765 MHz Bandwidth = 12 kHz to 20 MHz

= Bypass (no divide or delay)

CLKoutX_MUX = Divided (no delay) CLKoutX_DIV =

Equal loading and identical clock

SKEW

CLKoutX to CLKoutY (Note 14)

configuration

-30 ±4 30 ps

RL = 100 Ω

ΔV

SAB

Differential Output Voltage

Change in magnitude of VOD for complementary output states

Output Offset Voltage

Change in magnitude of VOS for complementary output states

Clock Output Short Circuit Current single-ended

Clock Output Short Circuit Current differential

RL = 100 Ω

250 350 450 mV

-50 50 mV

1.070 1.25 1.370 V

-35 35 mV

Single-ended outputs shorted to GND -24 24 mA

Complementary outputs tied together -12 12 mA

Clock Distribution Section (Notes 12, 13) - LVPECL Clock Outputs

CLKoutX_MUX

Jitter

ADD

Additive RMS Jitter (Note 12)

RL = 100 Ω Distribution Path = 765 MHz Bandwidth = 12 kHz to 20 MHz

= Bypass (no divide or delay)

CLKoutX_MUX = Divided (no delay) CLKoutX_DIV =

Equal loading and identical clock

SKEW

CLKoutX to CLKoutY (Note 14)

configuration

-30 ±3 30 ps

Termination = 50 Ω to Vcc - 2 V

Output High Voltage

Termination = 50 Ω to Vcc - 2 V

Output Low Voltage

Differential Output Voltage

RL = 100 Ω

660 810 965 mV

Vcc -

0.98

Vcc -

1.8

Digital LVTTL Interfaces (Note 15)

High-Level Input Voltage 2.0 Vcc V

Low-Level Input Voltage 0.8 V

High-Level Input Current

Low-Level Input Current

High-Level Output Voltage

Low-Level Output Voltage

VIH = Vcc

VIL = 0

IOH = +500 µA

IOL = -500 µA

-5.0 5.0 µA

-40.0 5.0 µA

Vcc -

0.4

0.4 V

Digital MICROWIRE Interfaces (Note 16)

High-Level Input Voltage 1.6 Vcc V

Low-Level Input Voltage 0.4 V

High-Level Input Current

Low-Level Input Current

VIH = Vcc

VIL = 0

-5.0 5.0 µA

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Symbol Parameter Conditions Min Typ Max Units

MICROWIRE Timing

CWH

CWL

CES

EWH

Note 4: The Electrical Characteristics table lists guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 5: See 3.5 for more current consumption / power dissipation calculation information.

Note 6: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L

dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of L

PLL_flicker

Note 7: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L L

PLL_flat

detector frequency of the synthesizer. L smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. L masked by the reference oscillator performance if a low power or noisy source is used.

Note 8: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reprogram the R15 register to ensure that the device stays in lock. Regardless of what temperature the device was initially programmed at, the ambient temperature can never drift outside the range of -40 °C ≤ TA ≤ 85 °C without violating specifications. For this specification to be valid, the programmed state of the device must not change after R15 is programmed.

Note 9: The lower sensitivity indicates the typical sensitivity at the lower end of the tuning range, the higher sensitivity at the higher end of the tuning range

Note 10: Output power varies as a function of frequency. When a range is shown, the higher output power applies to the lower frequency and the lower output

power applies to the higher frequency.

Note 11: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB, assuming the device is not reprogrammed. Reprogramming R15 will run the frequency calibration routine for optimum phase noise.

Note 12: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock distribution section only and this adds in an RMS fashion to the shaped jitter of the PLL and the VCO.

Note 13: For CLKout frequencies above 1 GHz, the delay should be limited to one half of a period. For 1 GHz and below, the maximum delay can be used.

Note 14: Specification is guaranteed by characterization and is not tested in production.

Note 15: Applies to GOE, LD, and SYNC*.

Note 16: Applies to CLKuWire, DATAuWire, and LEuWire.

Data to Clock Set Up Time See Data Input Timing 25 ns

Data to Clock Hold Time See Data Input Timing 8 ns

Clock Pulse Width High See Data Input Timing 25 ns

Clock Pulse Width Low See Data Input Timing 25 ns

Clock to Enable Set Up Time See Data Input Timing 25 ns

Enable to Clock Set Up Time See Data Input Timing 25 ns

Enable Pulse Width High See Data Input Timing 25 ns

(f), which is dominant close to the carrier. Flicker noise has a 10

(f) and L

(f) – 20log(N) – 10log(f

PLL_flat

(f).

COMP

PLL_flicker

). L

(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and f

PLL_flat

(f) contributes to the total noise, L(f). To measure L

PLL_flat

(10 kHz) - 20log(Fout / 1 GHz), where L

PLL_flicker

(f) the offset frequency, f, must be chosen sufficiently

(f) it is important to be on the 10 dB/decade

PLL_flicker

(f), of the PLL and is defined as PN1Hz =

PLL_flat

is the phase

COMP

PLL_flat

PLL_flicker

(f) can be

LMK03000 Family

(f)

Serial Data Timing Diagram

20211403

Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. It is recommended that the slew rate of CLKuWire, DATAuWire, and LEuWire should be at least 30 V/μs.

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