National Semiconductor LMK01000 Technical data

July 15, 2009

LMK01000 Family

LMK01000 Family 1.6 GHz High Performance Clock Buffer, Divider, and Distributor

General Description

The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

Target Applications

High performance Clock Distribution

■

Wireless Infrastructure

■

Medical Imaging

■

Wired Communications

■

Test and Measurement

■

Military / Aerospace

■

System Diagram

Features

30 fs additive jitter (100 Hz to 20 MHz)

■

Dual clock inputs

■

Programmable output channels (0 to 1600 MHz)

■

External synchronization

■

Pin compatible family of clocking devices

■

3.15 to 3.45 V operation

■

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

■

Device

LMK01000 3 5

LMK01010 8 0

LMK01020 0 8

LVDS

Outputs

LVPECL Outputs

30042806

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

Functional Block Diagram

LMK01000 Family

30042801

Connection Diagram

48-Pin LLP Package

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30042802

Pin Descriptions

Pin # Pin Name I/O Description

1, 25 GND - Ground

2, 7, 9,10, 32 NC - No Connect. Pin is not connected to the die.

3, 8, 13, 16, 19, 22, 26,

30, 31, 33, 37, 40, 43, 46

4 CLKuWire I MICROWIRE Clock Input

5 DATAuWire I MICROWIRE Data Input

6 LEuWire I MICROWIRE Latch Enable Input

11 GOE I Global Output Enable

12 Test O

14, 15 CLKout0, CLKout0* O Clock Output 0

17, 18 CLKout1, CLKout1* O Clock Output 1

20, 21 CLKout2, CLKout2* O Clock Output 2

23, 24 CLKout3, CLKout3* O Clock Output 3

27 SYNC* I Global Clock Output Synchronization

28, 29 CLKin0,CLKin0* I CLKin 0 Input; Must be AC coupled

34, 35 CLKin1, CLKin1* I CLKin 1 Input; Must be AC coupled

36 Bias I Bias Bypass

38, 39 CLKout4, CLKout4* O Clock Output 4

41, 42 CLKout5, CLKout5* O Clock Output 5

44, 45 CLKout6, CLKout6* O Clock Output 6

47, 48 CLKout7, CLKout7* O Clock Output 7

DAP DAP - Die Attach Pad should be connected to ground.

Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7,

Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14

- Power Supply

This is an output pin used strictly for test purposes and should be not connected for normal operation. However, any load of an impedance of more than 1 kΩ is acceptable.

LMK01000 Family

The LMK01000 family is footprint compatible with the LMK03000/02000 family of devices. All CLKout pins are pin-to-pin compatible, and CLKin0 and CLKin1 are equivalent to OSCin and Fin, respectively.

Device Configuration Information

Output LMK01000 LMK01010 LMK01020

CLKout0 LVDS LVDS LVPECL

CLKout1 LVDS LVDS LVPECL

CLKout2 LVDS LVDS LVPECL

CLKout3 LVPECL LVDS LVPECL

CLKout4 LVPECL LVDS LVPECL

CLKout5 LVPECL LVDS LVPECL

CLKout6 LVPECL LVDS LVPECL

CLKout7 LVPECL LVDS LVPECL

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Absolute Maximum Ratings (Note 1, Note 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Parameter Symbol Ratings Units

Power Supply Voltage

LMK01000 Family

Input Voltage

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

V

CC

V

IN

T

STG

T

L

T

J

-0.3 to 3.6 V

-0.3 to (VCC + 0.3)

-65 to 150 °C

+260 °C

125 °C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Ambient Temperature

Power Supply Voltage

Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV.

T

A

V

CC

-40 25 85 °C

3.15 3.3 3.45 V

Package Thermal Resistance

V

Package

θ

JA

θ

J-PAD (Thermal Pad)

48-Lead LLP (Note 3) 27.4° C/W 5.8° C/W

Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.

Electrical Characteristics (Note 4)

(3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed).

Symbol Parameter Conditions Min Typ Max Units

Current Consumption

I

CC

ICCPD

f

CLKin

SLEW

DUTY

P

CLKin

All outputs enabled, no divide or delay

Power Supply Current (Note 5)

( CLKoutX_MUX = Bypassed )

Per channel, no divide or delay (CLKoutX_MUX = Bypassed )

Power Down Current POWERDOWN = 1 1

CLKin0, CLKin0*, CLKin1, CLKin1*

CLKin Frequency Range 1 1600 MHz

CLKin Frequency Input Slew Rate (Note 6, Note 8) 0.5 V/ns

f

≤ 800 MHz

CLKin Frequency Input Duty Cycle

Input Power Range for CLKin or CLKin*

CLKin

f

> 800 MHz

CLKin

AC coupled -13 5 dBm

LMK01000 271

LMK01010 160

LMK01020 338

LVDS 17.8

LVPECL (Includes Emitter

40

Resistors)

30 70

40 60

mA

%

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Symbol Parameter Conditions Min Typ Max Units

Clock Distribution Section--Delays

f

≤ 1 GHz

Delay

CLKout

Maximum Allowable Delay(Note 8)

CLKoutX

(Delay is limited to maximum programmable value)

f

> 1 GHz

CLKoutX

(Delay is limited to 1/2 of a period)

2250

0.5/

f

CLKoutX

Clock Distribution Section - Divides

Divide

CLKoutX

Allowable divide range. (Note that 1 is the only allowable odd divide value)

f

≤ 1300 MHz

CLKinX

1300 MHz < f

CLKinX

≤ 1600 MHz

1 510

1 2

Clock Distribution Section - LVDS Clock Outputs

f

Jitter

ADD

Additive RMS Jitter (Note 7)

Noise Floor Divider Noise Floor(Note 7)

RL = 100 Ω Bandwidth = 100 Hz to 20 MHz Vboost = 1

RL = 100 Ω Vboost = 1

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

= 200 MHz

= 800 MHz

= 1600 MHz

= 200 MHz

= 800 MHz

= 1600 MHz

80

30

25

-156

-153

-148

Equal loading and identical clock

t

SKEW

CLKoutX to CLKoutY (Note 8)

configuration

-30 ±4 30 ps

RL = 100 Ω

V

ΔV

V

ΔV

I

SA

I

SB

I

SAB

OD

OS

OD

OS

Differential Output Voltage (Note 9)

Change in magnitude of VOD for complementary output states

Output Offset Voltage

Change in magnitude of VOS for complementary output states

Clock Output Short Circuit Current single ended

Clock Output Short Circuit Current differential

RL = 100 Ω

Single ended outputs shorted to GND -24 24 mA

Complementary outputs tied together -12 12 mA

Vboost=0 250 350 450

Vboost=1 390

-50 50 mV

1.070 1.25 1.370 V

-35 35 mV

LMK01000 Family

ps

n/a

fs

dBc/Hz

mV

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Symbol Parameter Conditions Min Typ Max Units

Clock Distribution Section - LVPECL Clock Outputs

f

Jitter

ADD

Additive RMS Jitter(Note 7)

LMK01000 Family

Noise Floor Divider Noise Floor(Note 7)

RL = 100 Ω Bandwidth = 100 Hz to 20 MHz Vboost = 1

RL = 100 Ω Vboost = 1

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

f

CLKoutX

= 200 MHz

= 800 MHz

= 1600 MHz

= 200 MHz

= 800 MHz

= 1600 MHz

65

25

-158

-154

-148

Equal loading and identical clock

t

SKEW

CLKoutX to CLKoutY (Note 8)

configuration

-30 ±3 30 ps

Termination = 50 Ω to Vcc - 2 V

V

OH

Output High Voltage

Termination = 50 Ω to Vcc - 2 V

V

OL

V

OD

Output Low Voltage

Differential Output Voltage (Note 9)

Vboost = 0 660 810 965

Vboost = 1 865

Vcc -

0.98

Vcc -

1.8

Digital LVTTL Interfaces (Note 10)

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

High-Level Input Voltage 2.0 Vcc V

Low-Level Input Voltage 0.8 V

High-Level Input Current

Low-Level Input Current

High-Level Output Voltage

Low-Level Output Voltage

VIH = Vcc

VIL = 0

IOH = +500 µA

IOL = -500 µA

-5.0 5.0 µA

-40.0 5.0 µA

Vcc -

0.4

V

0.4 V

fs

dBc/Hz

V

mV

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Symbol Parameter Conditions Min Typ Max Units

Digital MICROWIRE Interfaces (Note 11)

V

IH

V

IL

I

IH

I

IL

High-Level Input Voltage 1.6 Vcc V

Low-Level Input Voltage 0.4 V

High-Level Input Current

Low-Level Input Current

VIH = Vcc

VIL = 0

-5.0 5.0 µA

MICROWIRE Timing

t

CS

t

CH

t

CWH

t

CWL

t

ES

t

CES

t

EWH

Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 5: See section 3.2 for more current consumption / power dissipation calculation information.

Note 6: For all frequencies the slew rate, SLEW

Note 7: The noise floor of the divider is measured as the far out phase noise of the divider. Typically this offset is 40 MHz, but for lower frequencies this

measurement offset can be as low as 5 MHz due to measurement equipment limitations. If the delay is used, then use section 1.3.

Note 8: Specification is guaranteed by characterization and is not tested in production.

Note 9: See characterization plots to see how this parameter varies over frequency.

Note 10: Applies to GOE, LD, and SYNC*.

Note 11: Applies to CLKuWire, DATAuWire, and LEuWire.

Data to Clock Set Up Time See Data Input Timing 25 ns

Data to Clock Hold Time See Data Input Timing 8 ns

Clock Pulse Width High See Data Input Timing 25 ns

Clock Pulse Width Low See Data Input Timing 25 ns

Clock to Enable Set Up Time See Data Input Timing 25 ns

Enable to Clock Set Up Time See Data Input Timing 25 ns

Enable Pulse Width High See Data Input Timing 25 ns

, is measured between 20% and 80%.

CLKin1

LMK01000 Family

Serial Data Timing Diagram

30042803

Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. The slew rate of CLKuWire, DatauWire, and LEuWire should be at least 30 V/µs.

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