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LM6118/LM6218
Fast Settling Dual Operational Amplifiers
LM6118/LM6218 Fast Settling Dual Operational Amplifiers
May 1999
General Description
The LM6118/LM6218 are monolithic fast-settling
unity-gain-compensated dual operational amplifiers with
mAoutputdrivecapability. The PNP input stage has a typical
bias current of 200 nA, and the operating supply voltage is
±
5V to±20V.
These dual op amps use slew enhancement with special
mirror circuitry to achieve fast response and high gain with
low total supply current.
The amplifiers are built on a junction-isolated VIP
cally Integrated PNP) process which produces fast PNP’s
that complement the standard NPN’s.
™
(Verti-
±
20
Features
j
Low offset voltage: 0.2 mV
j
0.01%settling time: 400 ns
j
Slew rate A
j
Slew rate A
j
Gain bandwidth: 17 MHz
j
Total supply current: 5.5 mA
j
Output drives 50Ω load (±1V)
Applications
n D/A converters
n Fast integrators
n Active filters
Connection Diagrams and Order Information
Small Outline Package (WM)
DS010254-3
Top View
Order Number LM6218WM
See NS Package Number M14B
=
−1: 140 V/µs
v
=
+1: 75 V/µs
v
Dual-In-Line Package (J or N)
DS010254-4
Top View
Order Number LM6118N,
LM6218AN or LM6218N
See NS Package Number N08E
Typical
VIP™is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS010254 www.national.com
Typical Applications
Single ended input to differential output
=
10, BW=3.2 MHz
A
V
Response=1.4 MHz
40 V
PP
=
±
15V
V
S
Wide-Band, Fast-Settling
40 V
Amplifier
PP
DS010254-1
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Supply Voltage 42V
Input Voltage (Note 2)
Differential Input Current (Note 3)
Output Current (Note 4) Internally Limited
Power Dissipation (Note 5) 500 mW
ESD Tolerance
(C=100 pF, R=1.5 kΩ)
±
10 mA
±
2kV
Junction Temperature 150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 10 sec.) 300˚C
Operating Temp. Range
LM6118 −55˚C to +125˚C
LM6218A −40˚C to +85˚C
LM6218 −40˚C to +85˚C
Electrical Characteristics
±
5V ≤ VS≤±20V, V
25˚C, and Bold Face Type are for Temperature Extremes.
=
0V, V
CM
Parameter Conditions 25˚C Limits Limits Limits Units
Input Offset Voltage V
Input Offset Voltage V− + 3V ≤ V
Input Offset Current V− + 3V ≤ V
Input Bias Current V− + 3V ≤ V
Input Common Mode V− + 3V ≤ V
Rejection Ratio V
Positive Power Supply V−=−15V 100 90 90 80 dB (min)
Rejection Ratio 5V ≤ V+ ≤ 20V 85 85 75
Negative Power Supply V+=15V 100 90 90 80 dB (min)
Rejection Ratio −20V ≤ V− ≤ −5V 85 85 75
Large Signal V
Voltage Gain V
V
Output Voltage Supply
O
Swing
Total Supply Current V
Output Current Limit V
Slew Rate, Av=−1 V
Slew Rate, Av=+1 V
Gain-Bandwidth Product V
0.01%Settling Time ∆V
=
A
−1 R
V
Input Capacitance Inverter 5 pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its rated operating conditions.
Note 2: Input voltage range is (V
+
OUT
=
0V, I
=
0A, unless otherwise specified. Limits with standard type face are for T
OUT
Typ LM6118 LM6218A LM6218
(Note 6) (Note 6) (Note 6)
=
±
15V 0.2 1 1 3 mV (max)
S
224
≤ V+ − 3.5V 0.3 1.5 1.5 3.5 mV (max)
CM
2.5 2.5 4.5
≤ V+ − 3.5V 20 50 50 100 nA (max)
CM
250 100 200
≤ V+ − 3.5V 200 350 350 500 nA (max)
CM
950 950 1250
≤ V+ − 3.5V 100 90 90 80 dB (min)
CM
=
±
20V 85 85 75
S
=
±
15V R
out
=
±
20V 100 100 70
S
=
±
V
10V R
out
=
±
V
15V (±20 mA) 30 30 25
S
=
±
20V R
=
±
15V 5.5 7 7 7 mA (max)
S
=
10k 500 150 150 100 V/mV (min)
L
=
500 200 50 50 40 V/mV (min)
L
=
10k 17.3
L
±
17
±
17
±
17 V (min)
7.5 7.5 7.5
=
±
15V, Pulsed 65 100 100 100 mA (max)
S
=
±
15V, V
S
=
R
R
S
f
=
±
15V, V
S
=
R
R
S
f
=
±
15V, f
S
=
out
=
R
S
f
=
±
10V 140 100 100 100 V/µs (min)
out
=
=
2k, C
10 pF 50 50 50
f
=
±
10V 75 50 50 50 V/µs (min)
out
=
=
2k, C
10 pF 30 30 30
f
=
200 kHz 17 14 14 13 MHz (min)
o
=
±
10V, V
=
2k, C
15V,
S
=
10 pF
f
400
Follower 3 pF
− 1V) to (V−).
=
J
ns
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Electrical Characteristics (Continued)
Note 3: The inputs are shunted with three series-connected diodes back-to-back for input differential clamping. Therefore differential input voltages greater than
about 1.8V will cause excessive current to flow unless limited to less than 10 mA.
Note 4: Current limiting protects the output from a short to ground or any voltage less than the supplies. With a continuous overload, the package dissipation must
be taken into account and heat sinking provided when necessary.
Note 5: Devices must be derated using a thermal resistance of 90˚C/W for the N and WM packages.
Note 6: Limits are guaranteed by testing or correlation.
Typical Performance Characteristics
Input Bias Current
Common Mode Rejection
Unity Gain Bandwidth
DS010254-25
DS010254-28
Input Noise Voltage
Power Supply Rejection
Unity Gain Bandwidth
vs Output Load
DS010254-26
DS010254-29
Common Mode Limits
DS010254-27
Frequency Response
High Frequency
DS010254-30
Large Signal Response
(Sine Wave)
DS010254-31
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DS010254-32
DS010254-33
Typical Performance Characteristics (Continued)
Total Harmonic Distortion
Output Current Limit
Inverter Settling Time
DS010254-34
DS010254-37
Output Impedance
Supply Current
(Both Amplifiers)
Follower Settling Time
DS010254-35
DS010254-38
Output Saturation
DS010254-36
Slew Rate
DS010254-39
Typical Stability Range
DS010254-40
DS010254-41
DS010254-42
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Typical Performance Characteristics (Continued)
Amplifier to Amplifier Coupling
DS010254-23
Settling Time, Vs
=
±
15V
DS010254-7
=
Step Response, Av=+1, Vs
±
15V
DS010254-8
Application Information
General
The LM6118/LM6218 are high-speed, fast-settling dual
op-amps. Toinsure maximum performance, circuit board layout is very important. Minimizing stray capacitance at the inputs and reducing coupling between the amplifier’s input and
output will minimize problems.
Supply Bypassing
To assure stability, it is recommended that each power supply pin be bypassed with a 0.1 µF low inductance capacitor
near the device. If high frequency spikes from digital circuits
or switching supplies are present, additional filtering is recommended. To prevent these spikes from appearing at the
output, R-C filtering of the supplies near the device may be
necessary.
Power Dissipation
These amplifiers are specified to 20 mA output current. If accompanied with high supply voltages, relatively high power
dissipation in the device will occur, resulting in high junction
temperatures. In these cases the package thermal resistance must be taken into consideration. (See Note 5 under
Electrical Characteristics.) For high dissipation, an N package with large areas of copper on the pc board is recommended.
=
Step Response, Av=−1, Vs
±
15V
DS010254-9
Amplifier Shut Down
If one of the amplifiers is not used, it can be shut down by
connecting both the inverting and non-inverting inputs to the
V− pin. This will reduce the power supply current by approximately 25%.
Capacitive Loading
Maximum capacitive loading is about 50 pF for a closed-loop
gain of +1, before the amplifier exhibits excessive ringing
and becomes unstable. A curve showing maximum capacitive loads, with different closed-loop gains, is shown in the
Typical Performance Characteristics section.
To drive larger capacitive loads at low closed-loop gains, isolate the amplifier output from the capacitive load with 50Ω.
Connect a small capacitor directly from the amplifier output
to the inverting input. The feedback loop is closed from the
isolated output with a series resistor to the inverting input.
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Application Information (Continued)
Voltage Follower
Integrator
=
For C
1000 pF, Small signal BW=5 MHz
L
Settling time to 0.01%, 10V Step
For C
For C
BW=500 kHz
20 V
p-p
=
1000 pF, settling time ≈ 1500 ns
L
=
300 pF, settling time ≈ 500 ns
L
Inverter
DS010254-10
DS010254-11
DS010254-12
Examples of unity gain connections for a voltage follower, Inverter, and integrator driving capacitive loads up to 1000 pF
are shown here. Different R1–C1 time constants and capacitive loads will have an effect on settling times.
Input Bias Current Compensation
Input bias current of the first op amp can be reduced or balanced out by the second op amp. Both amplifiers are laid out
in mirror image fashion and in close proximity to each other,
thus both input bias currents will be nearly identical and will
track with temperature. With both op amp inputs at the same
potential, a second op amp can be used to convert bias current to voltage, and then back to current feeding the first op
amp using large value resistors to reduce the bias current to
the level of the offset current.
Examples are shown here for an inverting application, (a)
where the inputs are at ground potential, and a second circuit (b) for compensating bias currents for both inputs.
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Application Information (Continued)
Bias Current Compensation
*
adjust for zero integrator drift
(a) Inverting Input Bias Compensation
for Integrator Application
=
A
V
V
S
Large and small signal B.W.=1.3 MHz (THD=3%)
+5, I
OUT
=
±
15V, CL≤ 0.01 µF
≤ 80 mA
DS010254-13
*
mount resistor close to input pin to minimize stray capacitance
Amplifier/Parallel Buffer
DS010254-14
(b) Compensation to Both Inputs
DS010254-15
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Application Information (Continued)
Constant-Voltage Crossover Network With 12 dB/Octave Slope
DS010254-16
Bilateral Current Source
=
±
V
15V, −10 ≤ VIN≤ 10V
S
Output dynamic range=10V−R6|I
=
500Ω, small signal BW=6 MHz
R
L
Large signal response=800 kHz
OUT
Coaxial Cable Driver
DS010254-17
|
Small signal (200 mV
)BW≈5 MHz
p-p
DS010254-19
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Application Information (Continued)
Instrumentation Amplifier
=
=
10, V
S
±
15V,All resistors 0.01
) B.W. ≈ 800 kHz
P-P
A
V
Small signal and large signal (20 V
Schematic Diagram
150 MHz Gain-Bandwidth Amplifier
=
=
100, V
±
15V,
S
) ≈ 800 kHz
p-p
%
DS010254-18
A
V
Small signal BW ≈ 1.5 MHz
Large signal BW (20 V
DS010254-20
1/2 LM6118 (Op Amp A)
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DS010254-21
Schematic Diagram (Continued)
Bias Circuit
DS010254-22
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Molded Small Outline Package (M)
Order Number LM6218AWM or LM6218WM
NS Package Number M14B
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Dual-In-Line Package (N)
Order Number LM6118N, LM6218AN or LM6218N
NS Package Number N08E
LM6118/LM6218 Fast Settling Dual Operational Amplifiers
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can be reasonably expected to cause the failure of
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safety or effectiveness.
labeling, can be reasonably expected to result in a
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Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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