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LM6165/LM6265/LM6365
High Speed Operational Amplifier
General Description
The LM6165 family of high-speed amplifiers exhibits an excellent speed-power product in delivering 300 V/µs and
725 MHz GBW (stable for gains as low as +25) with only
5 mA of supply current. Further power savings and application convenience are possible by taking advantage of the
wide dynamic range in operating supply voltage which extends all the way down to +5V.
These amplifiers are built with National’s VIP
tegrated PNP) process which produces fast PNP transistors
that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed
performance without the need for complex and expensive dielectric isolation.
™
(VerticallyIn-
n High GBW product: 725 MHz
n Low supply current: 5 mA
n Fast settling: 80 ns to 0.1
n Low differential gain:
n Low differential phase:
n Wide supply range: 4.75V to 32V
n Stable with unlimited capacitive load
%
<
%
0.1
<
0.1˚
Applications
n Video amplifier
n Wide-bandwidth signal conditioning
n Radar
n Sonar
LM6165/LM6265/LM6365 High Speed Operational Amplifier
May 1999
Features
n High slew rate: 300 V/µs
Connection Diagrams
10-Lead Flatpak
Top View
Order Number LM6165W/883
See NS Package Number W10A
DS009152-14
DS009152-8
Order Number LM6165J/883
See NS Package Number J08A
Order Number LM6365M
See NS Package Number M08A
Order Number LM6265N or LM6365N
See NS Package Number N08E
VIP™is a trademark of National SemiconductorCorporation.
© 1999 National Semiconductor Corporation DS009152 www.national.com
Connection Diagrams (Continued)
Temperature Range Package NSC
Military Industrial Commercial
−55˚C ≤ T
LM6165J/883 8-Pin J08A
5962-8962501PA Ceramic DIP
LM6165WG/883 10-Lead WG10A
5962-8962501XA Ceramic SOIC
LM6165W883 10-Pin W10A
5962-8962501HA Ceramic Flatpak
≤ +125˚C −25˚C ≤ TA≤ +85˚C 0˚C ≤ TA≤ +70˚C
A
LM6265N LM6365N 8-Pin N08E
LM6365M 8-Pin Molded M08A
Molded DIP
Surface Mt.
Drawing
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Differential Input Voltage
(Note 7)
Common-Mode Voltage
Range (Note 11) (V
Output Short Circuit to GND
(Note 2) Continuous
Soldering Information
Dual-In-Line Package (N, J)
Soldering (10 sec.) 260˚C
Small Outline Package (M)
Vapor Phase (60 sec.)
Infrared (15 sec.)
+−V−
) 36V
+
− 0.7V) to (V−+ 0.7V)
±
215˚C
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
Storage Temp Range −65˚C to +150˚C
Max Junction Temperature
(Note 3) 150˚C
ESD Tolerance (Notes 7, 8)
8V
Operating Ratings
Temperature Range (Note 3)
LM6165, LM6165J/883 −55˚C ≤ T
LM6265 −25˚C ≤ T
LM6365 0˚C ≤ T
Supply Voltage Range 4.75V to 32V
±
≤ +125˚C
J
≤ +85˚C
J
≤ +70˚C
J
700V
DC Electrical Characteristics
=
The following specifications apply for Supply Voltage
Boldface limits apply for T
=
=
T
A
to T
T
J
MIN
MAX
±
15V, V
; all other limits T
Symbol Parameter Conditions Typ LM6165 LM6265 LM6365 Units
V
V
Input Offset Voltage 1 3 3 6 mV
OS
Input Offset Voltage 3 µV/˚C
OS
Drift Average Drift
I
b
I
OS
I
OS
Input Bias Current 2.5 3 3 5 µA
Input Offset Current 150 350 350 1500 nA
Input Offset Current 0.3 nA/˚C
Drift Average Drift
R
C
A
V
Input Resistance Differential 20 kΩ
IN
Input Capacitance 6.0 pF
IN
Large Signal V
VOL
Voltage Gain R
(Note 10) R
Input Common-Mode Supply
CM
=
±
10V, 10.5 7.5 7.5 5.5 V/mV
OUT
=
2kΩ 5.0 6.0 5.0
L
=
10 kΩ 38
L
=
±
15V +14.0 +13.9 +13.9 +13.8 V
Voltage Range +13.8 +13.8 +13.7 Min
Supply=+5V 4.0 3.9 3.9 3.8 V
(Note 5) 3.8 3.8 3.7 Min
CMRR Common-Mode −10V ≤ V
≤ +10V 102 88 88 80 dB
CM
Rejection Ratio 82 84 78 Min
PSRR Power Supply
±
10V ≤ V±≤±16V 104 88 88 80 dB
Rejection Ratio 82 84 78 Min
=
≥ 100 kΩ and R
0, R
CM
L
=
=
T
25˚C.
A
J
=
50Ω unless otherwise noted.
S
Limit Limit Limit
(Notes 4, 12) (Note 4) (Note 4)
447Max
656Max
800 600 1900 Max
−13.6 −13.4 −13.4 −13.3 V
−13.2 −13.2 −13.2 Min
1.4 1.6 1.6 1.7 V
1.8 1.8 1.8 Max
Min
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DC Electrical Characteristics (Continued)
=
The following specifications apply for Supply Voltage
Boldface limits apply for T
=
=
T
A
to T
T
J
MIN
MAX
±
15V, V
; all other limits T
Symbol Parameter Conditions Typ LM6165 LM6265 LM6365 Units
=
V
Output Voltage Supply
O
Swing R
±
15V, +14.2 +13.5 +13.5 +13.4 V
=
2kΩ +13.3 +13.3 +13.3 Min
L
Supply=+5V 4.2 3.5 3.5 3.4 V
=
R
2kΩ(Note 5) 3.3 3.3 3.3 Min
L
Output Short Source 65 30 30 30 mA
Circuit Current 20 25 25 Min
Sink 65 30 30 30 mA
I
S
Supply Current 5.0 6.5 6.5 6.8 mA
=
≥ 100 kΩ and R
0, R
CM
L
=
=
T
25˚C.
A
J
=
50Ω unless otherwise noted.
S
Limit Limit Limit
(Notes 4, 12) (Note 4) (Note 4)
−13.4 −13.0 −13.0 −12.9 V
−12.7 −12.8 −12.8 Min
1.3 1.7 1.7 1.8 V
2.0 1.9 1.9 Max
20 25 25 Min
6.8 6.7 6.9 Max
AC Electrical Characteristics
=
The following specifications apply for Supply Voltage
Boldface limits apply for T
=
=
T
A
to T
T
J
MIN
MAX
±
15V, V
; all other limits T
Symbol Parameter Conditions Typ LM6165 LM6265 LM6365 Units
GBW Gain Bandwidth F=20 MHz 725 575 575 500 MHz
=
±
Product Supply
SR Slew Rate A
PBW Power Bandwidth V
V
Supply
OUT
5V 500
=
+25 (Note 9) 300 200 200 200 V/µs
=
±
5V 200
=
20 V
PP
Product
t
S
φ
m
A
φ
D
e
np-p
i
np-p
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C.
Note 3: The typical junction-to-ambient thermal resistance of the molded plastic DIP (N) is 105˚C/Watt, and the molded plastic SO (M) package is 155˚C/Watt, and
the cerdip (J) package is 125˚C/Watt. All numbers apply for packages soldered directly into a printed circuit board.
Note 4: All limits guaranteed by testing or correlation.
Note 5: For single supply operation, the following conditions apply: V+=5V, V−=0V, V
to Pin 4 (V−) to realize maximum output swing. This connection will degrade V
Note 6: C
Note 7: In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exeeding the maximum differential input voltage re-
sults in reverse breakdown of the base-emitter junction of one of the input transistors and probable degradation of the input parameters (especially V
Noise).
Settling Time 10V Step to 0.1
=
A
−25, R
V
Phase Margin A
Differential Gain NTSC, A
D
=
+25 45 Deg
V
Differential Phase NTSC, A
Input Noise Voltage F=10 kHz 5
Input Noise Current F=10 kHz 1.5
≤ 5pF.
L
%
=
2kΩ
L
=
+25
V
=
+25
V
=
≥ 100 kΩ and R
0, R
CM
=
A
L
=
T
25˚C. (Note 6)
J
=
50Ω unless otherwise noted.
S
Limit Limit Limit
(Notes 4, 12) (Note 4) (Note 4)
350
180
4.5 MHz
80 ns
<
0.1
<
0.1 Deg
=
2.5C, V
CM
.
OS
=
2.5V. Pin1&Pin8(V
OUT
Adjust) are each connected
OS
OS,IOS
Min
Min
%
, and
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AC Electrical Characteristics (Continued)
Note 8: The average voltage that the weakest pin combinations (those involving Pin 2 or Pin 3) can withstand and still conform to the datasheet limits. The test circuit
used consists of the human body model of 100 pF in series with 1500Ω.
Note 9: V
Note 10: Voltage Gain is the total output swing (20V) divided by the input signal required to produce that swing.
Note 11: The voltage between V
Note 12: A military RETS electrical test specification is available on request. At the time of printing, the LM6165J/883 RETS spec complied with the Boldface limits
in this column. The LM6165J/883 may also be procured as Standard Military Drawing
=
0.8V step. For supply
IN
=
=
±
5V, V
0.2V step.
IN
+
and either input pin must not exceed 36V.
#
5962-8962501PA.
Typical PerformanceCharacteristics R
Supply Current vs
Supply Voltage
DS009152-16
Gain-Bandwidth
Product
DS009152-19
Common-Mode
Rejection Ratio
Propagation Delay,
Rise and Fall Times
=10kΩ,TA= 25˚C unless otherwise specified
L
Power Supply
Rejection Ratio
DS009152-17
Gain-Bandwidth Product vs
Load Capacitance
DS009152-20
DS009152-18
DS009152-21
Slew Rate vs
Load Capacitance
DS009152-22
Overshoot vs
Capacitive Load
DS009152-23
Slew Rate
DS009152-24
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Typical Performance Characteristics R
=10kΩ,TA= 25˚C unless otherwise specified (Continued)
L
Output Impedance
Gain vs Supply Voltage
(Open-Loop)
DS009152-25
Differential Gain (Note 13)
DS009152-6
Note 13: Differential gain and differential phase measured for four series LM6365 op amps configured with gain of +25 (each output attenuated by 96%), in series
with an LM6321 buffer. Error added by LM6321 is negligible. Test performed using Tektronix Type 520 NTSC test system.
Differential Phase (Note 13)
DS009152-26
DS009152-7
Step Response; Av=+25
Input (0.2v/div) Output (5v/div)
TIME (50 (ns/div)
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DS009152-1
Typical Performance Characteristics R
=10kΩ,TA= 25˚C unless otherwise specified (Continued)
L
Input Noise Voltage
Open-Loop
Frequency Response
Common-Mode Input
Saturation Voltage
DS009152-27
DS009152-30
Input Noise Current
Open-Loop
Frequency Response
Output Saturation Voltage
DS009152-28
DS009152-31
Power Bandwidth
DS009152-29
Voltage Gain vs
Load Resistance
DS009152-32
Bias Current vs
Common-Mode Voltage
DS009152-33
DS009152-34
DS009152-35
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Simplified Schematic
Application Tips
The LM6365 is stable for gains of 25 or greater. The LM6361
and LM6364, specified in separate datasheets, are compensated versions of the LM6365. The LM6361 is unity-gain
stable, while the LM6364 is stable for gains as low as 5. The
LM6361, and LM6364 have the same high slew rate as the
LM6365, typically 300 V/µs.
To use the LM6365 for gains less than 25, a series
resistor-capacitor network should be added between the input pins (as shown in the Typical Applications, Noise Gain
Compensation) so that the high-frequency noise gain rises
to at least 25.
Power supply bypassing will improve stability and transient
response of the LM6365, and is recommended for every design. 0.01 µF to 0.1 µF ceramic capacitors should be used
Typical Applications
DS009152-3
(from each supply “rail” to ground); an additional 2.2 µF to
10 µF (tantalum) may be required for extra noise reduction.
Keep all leads short to reduce stray capacitance and lead inductance, and make sure ground paths are low-impedance,
especially where heavier currents will be flowing. Stray capacitance in the circuit layout can cause signal coupling between adjacent nodes, and can cause circuit gain to unintentionally vary with frequency.
Breadboarded circuits will work best if they are built using
generic PC boards with a good ground plane. If the op amps
are used with sockets, as opposed to being soldered into the
circuit, the additional input capacitance may degrade circuit
performance.
Offset Voltage Adjustment
DS009152-11
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Noise-Gain Compensation
RXCX≥ 1/(2π•25 MHz)
(1 + R1/R2)]=25 R
[R1+R
F
DS009152-12
X
Typical Applications (Continued)
All diodes 1N914
1 MHz Voltage-to-Frequency Converter
(f
OUT
=
1 MHz for V
=
10V)
IN
DS009152-13
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Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number LM6165J/883
NS Package Number J08A
Molded Package SO (M)
Order Number LM6365M
NS Package Number M08A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LM6265N or LM6365N
NS Package Number N08E
10-Pin Ceramic Flatpak
Order Number LM6165W/883
NS Package Number W10A
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Notes
LM6165/LM6265/LM6365 High Speed Operational Amplifier
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
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whose failure to perform when properly used in
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Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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