National Semiconductor LM27241 Technical data
LM27241
Synchronous Buck Regulator Controller for Mobile
Systems
LM27241 Synchronous Buck Regulator Controller for Mobile Systems
May 2005
General Description
The LM27241 is an adjustable 200kHz-500kHz single channel voltage-mode controlled high-speed synchronous buck
regulator controller. It is ideally suited for battery powered
applications such as laptop and notebook computers. The
LM27241 requires only N-channel FETs for both the upper
and lower positions of the synchronous stage. It features line
feedforward to improve the response to input transients. At
very light loads, the user can choose between the highefficiency Pulse-skip mode or the constant frequency
Forced-PWM mode. Lossless current limiting without the use
of external sense resistor is made possible by sensing the
voltage drop across the bottom FET. A unique adaptive duty
cycle clamping technique is incorporated to significantly reduce peak currents under abnormal load conditions. The
input voltage range is 5.5V to 28V while the output voltage is
adjustable down to 0.6V.
Standard supervisory and control features include soft-start,
power good, output under-voltage and over-voltage protection, under-voltage lockout, soft-shutdown and enable.
Typical Application
See Figure 17 for Expanded View
Features
n Input voltage range from 5.5V to 28V
n Forced-PWM or Pulse-skip modes
n Lossless bottom-side FET current sensing
n Adaptive duty cycle clamping
n High current N-channel FET drivers
n Low shutdown supply currents
n Reference voltage accurate to within
n Output voltage adjustable down to 0.6V
n Power Good flag and Chip Enable
n Under-voltage lockout
n Over-voltage/Under-voltage protection
n Soft-start and Soft-shutdown
n Switching frequency adjustable 200kHz-500kHz
±
1.5%
Applications
n Notebook Chipset Power Supplies
n Low Output Voltage High Efficiency Buck Regulators
20120104
© 2005 National Semiconductor Corporation DS201201 www.national.com
Connection Diagram
LM27241
20-Lead TSSOP (MTC)
Ordering Information
Order Number Package Drawing Supplied As
LM27241MTC MTC20 73 Units/Rail
LM27241MTCX MTC20 2500 Units/13" Reel
Pin Description
Pin 1, VDD: 5V supply rail for the control and logic sections.
For normal operation the voltage on this pin must be brought
above 4.5V. Subsequently, the voltage on this pin (including
any ripple component) should not be allowed to fall below 4V
for a duration longer than 7µs. Since this pin is also the
supply rail for the internal control sections, it should be
well-decoupled particularly at high frequencies. A minimum
0.1µF-0.47µF (ceramic) capacitor should be placed on the
component side very close to the IC with no intervening vias
between this capacitor and the VDD/SGND pins. If the voltage on Pin 1 falls below the lower UVLO threshold, upper
FET(s) are latched OFF and the lower FET(s) are latched
ON. Power Not Good is then signaled immediately (on Pin
6). To initiate recovery, the EN pin must be taken below 0.8V
and then back above 2V (with VDD held above 4.5V). Or the
voltage on the VDD pin must be taken below 1.0V and then
back again above 4.5V (with EN pin held above 2V). Normal
operation will then resume assuming that the fault condition
has been cleared.
Pin 2, SS: Soft-start pin. A Soft-start capacitor is placed
between this pin and ground. A typical capacitance of 0.1µF
is recommended between this pin and ground. The IC connects an internal 1.8 kΩ resistor (R
Characteristics table) between this pin and ground to discharge any remaining charge on the Soft-start capacitor
under several conditions. These conditions include the initial
power-up sequence, start-up by toggling the EN pin, and
also recovery from a fault condition. The purpose is to bring
down the voltage on the Soft-start pin to below 100mV for
obtaining reset. Reset having thus been obtained, an 11µA
current source at this pin charges up the Soft-start capacitor.
The voltage on this pin controls the maximum duty cycle,
and this produces a gradual ramp-up of the output voltage,
thereby preventing large inrush currents into the output capacitors. The voltage on this pin finally clamps close to 5V.
This pin is connected to an internal 115µA current sink
whenever a current limit event is in progress. This sink
SS_DCHG
, see Electrical
Top View
20120102
current discharges the Soft-start capacitor and forces the
duty cycle low to protect the power components. When a
fault condition is asserted (See Pin 9) the SS pin is internally
connected to ground via the 1.8 kΩ resistor.
Pin 3, FREQ: Frequency adjust pin. The switching frequency
is set by a resistor connected between this pin and ground.
A value of 22.1kΩ sets the frequency to 300kHz (nominal). If
the resistance is increased, the switching frequency decreases. An approximate relationship is that for every 7.3kΩ
increase or decrease in the value of the frequency set resistor, the total switching period increases or decreases by 1µs.
Pin 4, SGND: Signal Ground pin. This is the lower rail for the
control and logic sections. SGND should be connected on
the PCB to the system ground, which in turn is connected to
PGND. The layout is important and the recommendations in
the section Layout Guidelines should be followed.
Pin 5, EN: IC Enable pin. When EN is taken high, the output
is enabled by means of a Soft-start power-up sequence.
When EN is brought low, Power Not Good is signaled within
100ns. This causes Soft-shutdown to occur (see Pins 2 and
6). The Soft-start capacitor is then discharged by an internal
1.8kΩ resistor (R
table). When the Enable pin is toggled, a fault condition is
not asserted. Therefore in this case, the lower FET is not
latched ON, even as the output voltage ramps down, eventually falling below the under-voltage threshold. In fact, in
this situation, both the upper and the lower FETs are latched
OFF, until the Enable pin is taken high again. If a fault
shutdown has occurred, taking the Enable pin low and then
high again (toggling), resets the internal latches, and the IC
will resume normal switching operation.
Pin 6, PGOOD: Power Good output pin. An open-drain logic
output that is pulled high with an external pull-up resistor,
indicating that the output voltage is within a pre-defined
Power Good window. Outside this window, the pin is internally pulled low (Power Not Good signaled) provided the
output error lasts for more than 7µs. The pin is also pulled
low within 100ns of the Enable pin being taken low, irrespec-
SS_DCHG
, see Electrical Characteristics
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Pin Description (Continued)
tive of the output voltage level. PGOOD must always first be
"high" before it can respond to a proper fault "low" condition.
Under fault assertion, the low-side MOSFET is always
latched ON. This will not happen if regulation has not already
been achieved.
Pin 7, FPWM: Logic input for selecting either the Forced
PWM (FPWM) Mode or Pulse-skip Mode (SKIP). When the
pin is driven high, the IC operates in the FPWM mode, and
when pulled low or left floating, the SKIP mode is enabled. In
FPWM mode, the lower FET is always ON whenever the
upper FET is OFF (except for a narrow shoot-through protection deadband). This leads to continuous conduction
mode of operation, which has a fixed frequency and (almost)
fixed duty cycle down to very light loads. But this does
reduce efficiency at light loads. The alternative mode is SKIP
mode. This mode forces the lower MOSFET ON only until
the voltage on the Switch pin is more negative than 2.2mV
(typical). As an example, for a 21mΩ FET, this translates to
a current threshold of 2.2mV/21mΩ = 0.1A. Therefore, if the
(instantaneous) inductor current falls below this value, the
lower FET will turn OFF every cycle at this point (when
operated in SKIP mode). This threshold is set by the zerocross Comparator in the Block Diagram. Note that if the
inductor current is high enough to be always above this
zero-cross threshold (V
tics table), there will be no observable difference between
FPWM and SKIP mode settings (in steady-state). SKIP
mode is clearly a discontinuous mode of operation. However, in conventional discontinuous mode, the duty cycle
keeps falling (towards zero) as the load decreases. But the
LM27241 does not allow the duty cycle to fall by more than
15% of its original value (at the CCM-DCM boundary). This
forces pulse-skipping, and the average frequency is effectively decreased as the load decreases. This mode of operation improves efficiency at light loads, but the frequency is
effectively no longer a constant. Note that a minimum pre-
load of 0.1mA should be maintained on the output to ensure
regulation in SKIP mode. The resistive divider from output to
ground used to set the output voltage could be designed to
serve as part or all of this required pre-load.
Pin 8, COMP: Compensation pin. This is also the output of
the error amplifier. The voltage level on this pin is compared
with an internally generated ramp signal to set the duty cycle
for normal regulation. Since the Feedback pin is the inverting
input of the same error amplifier, appropriate control loop
compensation components are placed between this pin and
the Feedback pin. The COMP pin is internally pulled low
during Soft-start so as to limit the duty cycle. Once Soft-start
is completed, the voltage on this pin can take up the value
required to maintain output regulation. An internal voltage
clamp at this pin forms an adaptive duty cycle clamp feature.
This serves to limit the maximum allowable duty cycles and
peak currents under sudden overloads. But at the same time
it has enough headroom to permit an adequate response to
step loads within the normal operating range.
Pin 9, FB: Feedback pin. This is the inverting input of the
error amplifier. The voltage on this pin under regulation is
nominally at 0.6V. A Power Good window on this pin determines if the output voltage is within regulation limits (
If the voltage falls outside this window for more than 7µs,
Power Not Good is signaled on the PGOOD pin (Pin 6).
Output over-voltage and under-voltage conditions are also
detected by comparing the voltage on the Feedback pin with
appropriate internal reference voltage levels. If the voltage
exceeds the safe window (
SW_ZERO
, see Electrical Characteris-
±
13%).
±
30%) for longer than 7µs, a fault
condition is asserted. Then lower FET is latched ON and the
upper FET is latched OFF.
Pin 10, SENSE: Output voltage sense pin. It is tied directly
to the output rail. The SENSE pin voltage is used together
with the VIN voltage (on Pin 18) to (internally) calculate the
CCM (continuous conduction mode) duty cycle. This calculation is used by the IC to set the minimum duty cycle in the
SKIP mode to 85% of the CCM value. It is also used to set
the adaptive duty cycle clamp. An internal 20Ω resistor from
the SENSE pin to ground discharges the output capacitor
gently (Soft-shutdown) whenever Power Not Good is signaled on Pin 6.
Pin 11, ILIM: Current Limit pin. When the bottom FET is ON,
a 62µA (typical) current flows out of the ILIM pin and into an
external resistor that is connected to the drain of the lower
MOSFET. This current through the resistor creates a voltage
on the ILIM pin. However, the drain voltage of the lower
MOSFET will go more negative as the load current is increased through the R
of instantaneous current, the voltage on this pin will transit
from positive to negative. The point where it is zero is the
current limiting condition and is detected by the Current Limit
Comparator. When a current limit condition has been detected, the next ON-pulse of the upper FET will be omitted.
The lower FET will again be monitored to determine if the
current has fallen below the threshold. If it has, the next
ON-pulse will be permitted. If not, the upper FET will be
turned OFF and will stay so for several cycles if necessary,
until the current returns to normal. Eventually, if the overcurrent condition persists, and the upper FET has not been
turned ON, the output will clearly start to fall. Ultimately the
output will fall below the under-voltage threshold, and a fault
condition will be asserted by the IC.
Pin 12, SW: The Switching node of the buck regulator. Also
serves as the lower rail of the floating driver of the upper
FET.
Pin 13, HDRV: Gate drive pin for the upper FET. The top
gate driver is interlocked with the bottom gate driver to
prevent shoot-through/cross-conduction.
Pin 14, BOOT: Bootstrap pin. This is the upper supply rail for
the floating driver of the upper FET. It is bootstrapped by
means of a ceramic capacitor connected to the channel
Switching node. This capacitor is charged up by the IC to a
value of about 5V as derived from the V5 pin (Pin 17).
Pin 15, PGND: Power Ground pin. This is the return path for
the bottom FET gate drive. The PGND is to be connected on
the PCB to the system ground and also to the Signal ground
(Pin 4) in accordance with the recommended Layout Guidelines .
Pin 16, LDRV: Gate drive pin for the bottom FET (Low-side
drive). The bottom gate driver is interlocked with the top gate
driver to prevent shoot-through/cross-conduction. It is always latched high when a fault condition is asserted by the
IC.
Pin 17, V5: Upper rail of the lower FET driver. Also used to
charge up the bootstrap capacitor of the upper FET driver.
This is connected to an external 5V supply. The 5V rail may
be the same as the rail used to provide power to the VDD pin
(Pin 1), but the VDD pin will then require to be welldecoupled so that it does not interact with the V5 pin. A
low-pass RC filter consisting of a ceramic 0.1µF capacitor
(preferably 0.22µF) and a 10Ω resistor will suffice as shown
in the Typical Applications circuit.
Pin 18, VIN: The input to the Buck regulator power stage. It
is also used by the internal ramp generator to implement the
of the MOSFET. At some value
DS_ON
LM27241
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Pin Description (Continued)
line feedforward feature. The VIN pin is also used with the
LM27241
SENSE pin voltage to predict the CCM (continuous conduction mode) duty cycle and to thereby set the minimum al-
lowed DCM duty cycle to 85% of the CCM value. This is a
high input impedance pin, drawing only about 100µA (typical) from the input rail.
Pin 19, 20 NC: No Connect.
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LM27241
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltages from the indicated pins to SGND/PGND unless
otherwise indicated (Note 2):
VIN -0.3V to 30V
V5 -0.3V to 7V
VDD -0.3V to 7V
Junction Temperature +150˚C
ESD Rating (Note 4) 2kV
Ambient Storage Temperature
Range -65˚C to +150˚C
Soldering Dwell Time,
Temperature
Wave
Infrared
Vapor Phase
4 sec, 260˚C
10 sec, 240˚C
75 sec, 219˚C
BOOT -0.3V to 36V
BOOT to SW -0.3V to 7V
SW -0.3V to 30V
ILIM -0.3V to 30V
SENSE, FB -0.3V to 7V
Operating Ratings (Note 1)
VIN 5.5V to 28V
VDD, V5 4.5V to 5.5V
Junction Temperature -5˚C to +125˚C
PGOOD -0.3V to 7V
EN -0.3V to 7V
Power Dissipation (T
= 25˚C)
A
(Note 3) 0.75W
Electrical Characteristics
Specifications with standard typeface are for TJ= 25˚C, and those with boldface apply over full Operating Junction Temperature range. VDD = V5 = 5V, V
SGND=VPGND
= 0V, VIN = 15V, VEN= 3V, R
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol Parameter Conditions Min
Reference
V
FB_REG
V
FB_LINE REG
FB Pin Voltage at
Regualtion
VFBLine Regulation VDD = 4.5V to 5.5V,
VDD = 4.5V to 5.5V,
VIN = 5.5V to 28V
VIN = 5.5V to 28V
I
FB
FB Pin Current (sourcing) VFBat regulation 20 100 nA
Chip Supply
I
Q_VIN
I
SD_VIN
I
Q_VDD
I
SD_VDD
I
Q_V5
I
SD_V5
I
Q_BOOT
I
SD_BOOT
V
DD_UVLO
HYS
VDD_UVLO
VIN Quiescent Current VFB= 0.7V 100 200 µA
VIN Shutdown Current VEN=0V 0 5 µA
VDD Quiescent Current VFB= 0.7V 1.75 3 mA
VDD Shutdown Current VEN=0V 8 15 µA
V5 Normal Operating
Current
VFB= 0.7V 0.3 0.5 mA
V
= 0.5V 0.5 1.25
FB
V5 Shutdown Current VEN=0V 0 5 µA
BOOT Quiescent Current VFB= 0.7V 2 5 µA
V
= 0.5V 300 500
FB
BOOT Shutdown Current VEN=0V 1 5 µA
VDD UVLO Threshold VDD rising from 0V 3.9 4.2 4.5 V
VDD UVLO Hysteresis VDD = V5 falling from
V
DD_UVLO
Logic
I
EN
V
EN_HI
V
EN_LO
R
FPWM
V
FPWM_HI
V
FPWM_LO
EN Input Current VEN=0to5V 0 µA
EN Input Logic High 2 1.8 V
EN Input Logic Low 1.3 0.8 V
FPWM Pull-down V
=2V 100 200 1000 kΩ
FPWM
FPWM Input Logic High 2 1.8 V
FPWM Input Logic Low 1.3 0.8 V
= 22.1K unless otherwise stated (Note 5).
FADJ
Typical
(Note 7)
Max Units
591 600 609 mV
0.5
0.5 0.7 0.9 V
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Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ= 25˚C, and those with boldface apply over full Operating Junction Tempera-
LM27241
ture range. VDD = V5 = 5V, V
SGND=VPGND
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol Parameter Conditions Min
Power Good
V
PGOOD_HI
Power Good Upper
Threshold as a Percentage
of Internal Reference
V
PGOOD_LOW
Power Good Lower
Threshold as a Percentage
of Internal Reference
HYS
PGOOD
∆t
PG_OK
∆t
PG_NOK
∆t
SD
V
PGND_SAT
I
PGOOD_LEAK
Power Good Hysteresis 7 %
Power Good Delay From output voltage “good”
PGOOD Saturation Voltage PGOOD de-asserted (Power
PGOOD Leakage Current PGOOD = 5V and asserted 0 1 µA
OV and UV Protection
V
OVP_RISING
Fault OVP Latch Threshold
as a Percentage of Internal
Reference
V
OVP_FALLING
Fault UVP Latch Threshold
as a Percentage of Internal
Reference
∆t
FAULT
Fault Delay From Fault detection (any
Soft-start
I
SS_CHG
R
SS_DCHG
Soft-start Charging Current VSS=1V 8 11 14 µA
Soft-shutdown Resistance
(SS pin to SGND)
I
SS_DCHG
Soft-start Discharge
Current
V
SS_RESET
Soft-start pin reset voltage
(Note 6)
V
OS
SS to COMP Offset
Voltage
Error Amplifier
GAIN DC Gain 70 dB
V
SLEW
Voltage Slew Rate COMP rising 4.45 V/µs
BW Unity Gain Bandwidth 6.5 MHz
I
COMP_SOURCE
I
COMP_SINK
COMP Source Current V
COMP Sink Current V
Current Limit and Zero-Cross
= 0V, VIN = 15V, VEN= 3V, R
FB voltage rising above
V
FB_REG
FB voltage falling below
V
FB_REG
to PGOOD assertion.
From the output voltage
“bad” to PGOOD
de-assertion
From Enable low to PGOOD
low
Not Good) and sinking
1.5mA
FB voltage rising above
V
FB_REG
FB voltage falling below
V
FB_REG
output) to Fault assertion
VEN= 0V, VSS= 1V 1800 Ω
In Current Limit 80 115 160 µA
SS charged to 0.5V, EN low
to high
VSS= 0.5V and 1V, VFB=
0V
COMP falling 2.25
<
V
FB
FB_REG
V
= 0.5V
COMP
>
V
FB
FB_REG
V
= 0.5V
COMP
= 22.1K unless otherwise stated (Note 5).
FADJ
Typical
(Note 7)
Max Units
110 113 116 %
84 87 90 %
10 20 30 µs
4 7 10
0.03 0.1
0.12 0.4 V
125 130 135 %
65 70 75 %
7µs
100 mV
600 mV
2 5mA
7 14 mA
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Electrical Characteristics (Continued)
Specifications with standard typeface are for TJ= 25˚C, and those with boldface apply over full Operating Junction Temperature range. VDD = V5 = 5V, V
SGND=VPGND
= 0V, VIN = 15V, VEN= 3V, R
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol Parameter Conditions Min
I
ILIM
V
ILIM_TH
V
SW_ZERO
ILIM Pin Current (sourcing) V
I
Threshold Voltage -10 0 10 mV
ILIM
Zero-cross Threshold (SW
=0V 46 62 76 µA
ILIM
LDRV goes low -2.2 mV
Pin)
Oscillator
F
OSC
V
RAMP
V
VALLEY
∆F
OSC_VIN
PWM Frequency R
PWM Ramp Peak-to-peak
Amplitude
= 22.1kΩ 255 300 345 kHz
FADJ
R
= 12.4kΩ 500
FADJ
R
= 30.9kΩ 200
FADJ
VIN = 15V 1.6 V
VIN = 24V 2.95
PWM Ramp Valley 0.8 V
Frequency Change with
VIN = 5.5V to 24V
VIN
∆F
OSC_VDD
Frequency Change with
VDD = 4.5V to 5.5V
VDD
V
FREQ_VIN
FREQ Pin Voltage vs. VIN 0.105 V/V
System
t
ON_MIN
D
MAX
Minimum ON Time V
=3V 30 ns
FPWM
Maximum Duty Cycle VIN = 5.5V 60 75 %
VIN = 15V 40 50 %
VIN = 28V, VDD= 4.5V 22 28 %
Gate Drivers
R
HDRV_SOURCE
HDRV Source Impedance HDRV Pin Current
(sourcing)= 1.2A
R
HDRV_SINK
HDRV Sink Impedance HDRV Pin Current (sinking)
=1A
R
LDRV_SOURCE
LDRV Source Impedance LDRV Pin Current (sourcing)
= 1.2A
R
LDRV_SINK
LDRV Sink Impedance LDRV Pin Current (sinking)
=2A
t
DEAD
Cross-conduction
Protection Delay
(deadtime)
HDRV Falling to LDRV
Rising
LDRV Falling to HDRV
Rising
= 22.1K unless otherwise stated (Note 5).
FADJ
Typical
(Note 7)
±
1%
±
2%
Max Units
7 Ω
2 Ω
7 Ω
1 Ω
40 ns
70
LM27241
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics table.
Note 2: PGND and SGND are all electrically connected together on the PCB.
Note 3: The maximum allowable power dissipation is calculated by using P
ambient temperature, and θ
from using 125˚C, 25˚C, and 118˚C/W for T
TSSOP package. The θ
ambient temperatures. For detailed information on soldering plastic TSSOP package, refer to http://www.national.com/packaging/.
Note 4: ESD is applied by the human body model, which is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 5: R
Note 6: If the LM27241 starts up with a pre-charged soft start capacitor, it will first discharge the capacitor to V
process.
Note 7: Typical numbers are at 25˚C and represent the most likely norm.
is the frequency adjust resistor between FREQ pin and Ground.
FADJ
is the junction-to-ambient thermal resistance of the specified package. The 0.75W rating of the TSSOP-20 package for example results
JA
value above represents the worst-case condition with no heat sinking. Heat sinking will permit more power to be dissipated at higher
JA
, and θJArespectively. The rated power dissipation should be derated by 10mW/˚C above 25˚C ambient for the
JMAX,TA
Dmax
=(T
JMAX-TA
)/θJA, where T
is the maximum junction temperature, TAis the
JMAX
SS_RESET
and then begin the normal Soft-start
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Block Diagram
LM27241
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20120101
Typical Performance Characteristics Input Voltage is 12V, 18V, 24V (in order) starting from upper-
most curve to lowermost curve in each of the Efficiency plots below.
Efficiency for 2.5V Output Efficiency for 1.5V Output
LM27241
20120105
Efficiency for 1.05V Output Modulator (Plant) Gain
20120107
20120106
20120108
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