National Semiconductor DS92LV16 Technical data

February 2002

DS92LV16
16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV1616-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

General Description

The DS92LV16Serializer/Deserializer(SERDES)pairtrans­parently translates a 16–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 16-bit, or less bus over PCB
traces andcablesby eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar­rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.

This SERDES pair includes built-in system and device test
capability. The line loopback and local loopback features
provide the following functionality: the local loopback en­ables the user to check the integrity of the transceiver from
the local parallel-bus side and the system can check the
integrity of the data transmission line by enabling the line
loopback.

The DS92LV16 incorporates BLVDS signaling on the high­speed I/O. BLVDS provides a low power and low noise
environment for reliably transferring data over a serial trans­mission path. The equal and opposite currents through the
differential data path control EMI by coupling the resulting
fringing fields together.

Block Diagram

DS92LV16

Features

n 25–80 MHz 16:1/1:16 serializer/deserializer (2.56Gbps

full duplex throughput)

n Independent transmitter and receiver operation with

separate clock, enable, power down pins

n Hot plug protection (power up high impedance) and

synchronization (receiver locks to random data)

n Wide +/−5% reference clock frequency tolerance for

easy system design using locally-generated clocks

n Line and local loopback modes
n Robust BLVDS serial transmission across backplanes

and cables for low EMI

n No external coding required
n Internal PLL, no external PLL components required
n Single +3.3V power supply
n Low power: 104mA (typ) transmitter, 119mA (typ)

receiver at 80MHz

±

n

100mV receiver input threshold

n Loss of lock detection and reporting pin
n Industrial −40 to +85˚C temperature range

>

n

2.5kV HBM ESD

n Compact, standard 80-pin PQFP package

20014301

© 2002 National Semiconductor Corporation DS200143 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/

DS92LV16

Distributors for availability and specifications.

Supply Voltage (V
LVCMOS/LVTTL Input

Voltage −0.3V to (V

) −0.3V to +4V

CC

CC

+0.3V)

Maximum Package Power Dissipation Capacity
Package Derating:

23.2 mW/˚C above

80L PQFP

θ

JA

θ

JC

ESD Rating (HBM)

+25˚C

43˚C/W

11.1˚C/W

>

LVCMOS/LVTTL Output
Voltage −0.3V to (V

Bus LVDS Receiver Input
Voltage −0.3V to +3.9V

Bus LVDS Driver Output
Voltage −0.3V to +3.9V

Bus LVDS Output Short
Circuit Duration 10ms

Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C

CC

+0.3V)

Recommended Operating Conditions

Min Nom Max Units

Supply Voltage (V
Operating Free Air

Temperature (T

Clock Rate 25 80 MHz

) 3.15 3.3 3.45 V

CC

)

A

−40 +25 +85 ˚C

Lead Temperature

(Soldering, 4 seconds) +260˚C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

LVCMOS/LVTTL DC Specifications

V

IH

V

IL

V

CL

I

IN

V

OH

V

OL

I

OS

I

OZ

Bus LVDS DC specifications

VTH

VTL

I

IN

High Level Input Voltage 2.0 V

Low Level Input Voltage

TCLK_R/F,DEN,

TCLK, TPWDN, DIN,

GND 0.8 V

SYNC, RCLK_R/F,

Input Clamp Voltage ICL= −18 mA

REN, REFCLK,

-0.7 −1.5 V

PWRDN

Input Current VIN= 0V or 3.6V −10

±

2 +10 µA

High Level Output Voltage IOH= −9 mA 2.3 3.0 V

Low Level Output Voltage IOL=9mA R

, RCLK, LOCK GND 0.33 0.5 V

OUT

Output Short Circuit Current VOUT = 0V −15 −48 −85 mA

PWRDN or REN =

TRI-STATE Output Current

0.8V, V

OUT

=0Vor

R

, RCLK, −10

OUT

±

0.4 +10 µA

VCC

Differential Threshold High

Voltage

Differential Threshold Low

Voltage

Input Current

VCM = +1.1V +100 mV

RI+, RI- −100 mV

= +2.4V, VCC=

V

IN

3.6V or 0V

= 0V, VCC= 3.6V

V

IN

or 0V

−10

−10

±

5 +10 µA

±

5 +10 µA

2.5kV

CC

CC

V

V

www.national.com 2

Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

V

OD

∆V

OD

V

OS

∆V

OS

I

OS

I

OZ

I

OX

SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins)

I

CCT

I

CCX

Output Differential Voltage

(DO+) - (DO-)

Output Differential Voltage

Unbalance

RL = 100Ω,

Figure 17

350 500 550 mV

215mV

Offset Voltage 1.05 1.2 1.25 V

Offset Voltage Unbalance 2.7 15 mV

Output Short Circuit Current

DO = 0V, Din = H,

TXPWDN and DEN =

DO+, DO-

-35 -50 -70 mA

2.4V

TXPWDN or DEN =

Tri-State Output Current

0.8V, DO = 0V OR

-10

±

110µA

VDD

Power-Off Output Current

Total Supply Current (includes

load current)

VDD = 0V, DO = 0V

or 3.6V

= 15 pF, RL= 100Ωf = 80 MHz, PRBS15

C

L

pattern

f = 80 MHz, Worse

= 15 pF, RL= 100

C

L

Ω

case pattern

(Checker-board

-10

±

110µA

209 mA

225 320 mA

pattern)

Supply Current Powerdown

PWRDN = 0.8V,

REN = 0.8V

0.35 1.0 mA

DS92LV16

Serializer Timing Requirements for TCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

t

TCP

t

TCIH

t

TCIL

t

CLKT

t

JIT

Transmit Clock Period 12.5 T 40 ns
Transmit Clock High Time 0.4T 0.5T 0.6T ns
Transmit Clock Low Time 0.4T 0.5T 0.6T ns

TCLK Input Transition

Time

TCLK Input Jitter 80

36ns

ps

(RMS)

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

t

LLHT

t

LHLT

t
t

DIS

DIH

Bus LVDS Low-to-High

Transition Time

Bus LVDS High-to-Low

Transition Time

DIN (0-15) Setup to TCLK

DIN (0-15) Hold from

TCLK

= 100Ω

R

L

Figure 3

CL=10pF to GND

Figure 6

RL= 100Ω,

=10pF to GND

C

L

2.4 ns
0ns

0.2 0.4 ns

0.2 0.4 ns

www.national.com3

Serializer Switching Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

DS92LV16

t

t

t

t

t

t

t
t

HZD

LZD

ZHD

ZLD

SPW

PLD

t

SD

RJIT

DJIT

DO±HIGH to

TRI-STATE Delay

DO±LOW to

TRI-STATE Delay

DO±TRI-STATE to

HIGH Delay

Figure 7

C

(Note 4)

= 100Ω,

R

L

=10pF to GND

L

DO±TRI-STATE to

LOW Delay

SYNC Pulse Width

Serializer PLL Lock Time 510*t

Serializer Delay

Figure 8

RL= 100Ω

Figure 9

RL= 100Ω t

5*t

TCP

TCP

TCP

+ 1.0 t

2.3 10 ns

1.9 10 ns

1.0 10 ns

1.0 10 ns
6*t

TCP

513*t

TCP

+ 2.0 t

TCP

+ 4.0 ns

TCP

Random Jitter 10 ps(rms)

Deterministic Jitter

Figure 15

35 MHz -240 140 ps
80 MHz -75 100 ps

Deserializer Timing Requirements for REFCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

t

RFCP

t

RFDC

t

RFCP

t

t

RFTT

/

TCP

REFCLK Period 12.5 T 40 ns
REFCLK Duty Cycle 40 50 60 %
Ratio of REFCLK to

TCLK

0.95 1.05

REFCLK Transition Time 6ns

ns
ns

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

t
t

Receiver out Clock

RCP

RDC

RCLK Duty Cycle RCLK 45 50 55 %

Period

CMOS/TTL

t

CLH

Low-to-High

Transition Time

CMOS/TTL

t

CHL

High-to-Low

Transition Time

t

t

t

t

t

t

ROUT (0-9) Setup

ROS

ROH

HZR

LZR

ZHR

ZLR

t

DD

Data to RCLK

ROUT (0-9) Hold

Data to RCLK

HIGH to TRI-STATE

Delay

LOW to TRI-STATE

Delay

TRI-STATE to HIGH

Delay

TRI-STATE to LOW

Delay

Deserializer Delay RCLK

Figure 9

t

RCP=tTCP

CL=15pF

Figure 4

Figure 11

Figure 12

RCLK 12.5 40 ns

24ns

Rout(0-9),

LOCK,

24ns

RCLK

0.35*t

−0.35*t

RCP

RCP

0.5*t

−0.5*t

RCP

RCP

2.2 10 ns

Rout(0-9),

LOCK

2.2 10 ns

2.3 10 ns

2.9 10 ns

1.75*t
+2

RCP

1.75*t

+ 5 1.75*t

RCP

+7 ns

RCP

ns

ns

www.national.com 4

Deserializer Switching Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

Deserializer PLL

t

DSR1

Lock Time from

PWRDWN (with

SYNCPAT)

(Note 7)

Deserializer PLL

t

DSR2

Lock time from

SYNCPAT

t

RNMI-R

t

RNMI-L

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,

VTH and VTL which are differential voltages.

Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions

of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time
required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change
from not receiving data to receiving synchronization patterns (SYNCPATs).

Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
in reference with the ideal bit position, please see National’s AN-1217 for detail.

Note 7: Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.

Ideal Deserializer

Noise Margin Right

Ideal Deserializer
Noise Margin Left

Figure 16

(Note 6)

Figure 16

(Note 6)

= 3.3V and TA= +25˚C.

CC

35MHz 3.7 10 µs

80 MHz 1.9 4 µs

35MHz 1.5 5 µs

80 MHz 0.9 2 µs
35 MHz +630 ps

80 MHz +230 ps
35 MHz −630 ps
80 MHz −230 ps

DS92LV16

www.national.com5

AC Timing Diagrams and Test Circuits

DS92LV16

FIGURE 1. “Worst Case” Serializer ICC Test Pattern

20014303

20014304

FIGURE 2. “Worst Case” Deserializer ICC Test Pattern

FIGURE 3. Serializer Bus LVDS Output Load and Transition Times

20014306

FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times

20014305

www.national.com 6