National Semiconductor DAC128S085 Technical data

September 2007

DAC128S085
12-Bit Micro Power OCTAL Digital-to-Analog Converter
with Rail-to-Rail Outputs

DAC128S085 12-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail Outputs

General Description

The DAC128S085 is a full-featured, general purpose OCTAL
12-bit voltage-output digital-to-analog converter (DAC) that
can operate from a single +2.7V to +5.5V supply and con­sumes 1.95 mW at 3V and 4.85 mW at 5V. The DAC128S085
is packaged in a 16-lead LLP package and a 16-lead TSSOP
package. The LLP package makes the DAC128S085 the
smallest OCTAL DAC in its class. The on-chip output ampli­fiers allow rail-to-rail output swing and the three wire serial
interface operates at clock rates up to 40 MHz over the entire
supply voltage range. Competitive devices are limited to 25
MHz clock rates at supply voltages in the 2.7V to 3.6V range.
The serial interface is compatible with standard SPI™, QSPI,
MICROWIRE and DSP interfaces. The DAC128S085 also of­fers daisy chain operation where an unlimited number of
DAC128S085s can be updated simultaneously using a single
serial interface.

There are two references for the DAC128S085. One refer­ence input serves channels A through D while the other
reference serves channels E through H. Each reference can
be set independently between 0.5V and VA, providing the
widest possible output dynamic range. The DAC128S085 has
a 16-bit input shift register that controls the mode of operation,
the power-down condition, and the DAC channels' register/
output value. All eight DAC outputs can be updated simulta­neously or individually.

A power-on reset circuit ensures that the DAC outputs power
up to zero volts and remain there until there is a valid write to
the device. The power-down feature of the DAC128S085 al­lows each DAC to be independently powered with three dif­ferent termination options. With all the DAC channels
powered down, power consumption reduces to less than 0.3
µW at 3V and less than 1 µW at 5V. The low power consump­tion and small packages of the DAC128S085 make it an
excellent choice for use in battery operated equipment.

The DAC128S085 is one of a family of pin compatible DACs,
including the 8-bit DAC088S085 and the 10-bit DAC108S085.
All three parts are offered with the same pinout, allowing sys­tem designers to select a resolution appropriate for their
application without redesigning their printed circuit board. The
DAC128S085 operates over the extended industrial temper­ature range of −40°C to +125°C.

Features

Guaranteed Monotonicity

■

Low Power Operation

■

Rail-to-Rail Voltage Output

■

Daisy Chain Capability

■

Power-on Reset to 0V

■

Simultaneous Output Updating

■

Individual Channel Power Down Capability

■

Wide power supply range (+2.7V to +5.5V)

■

Dual Reference Voltages with range of 0.5V to V

■

Operating Temperature Range of −40°C to +125°C

■

Industry's Smallest Package

■

Key Specifications

Resolution 12 bits

■

INL ±8 LSB (max)

■

DNL +0.75 / −0.4 LSB (max)

■

Settling Time 8.5 µs (max)

■

Zero Code Error +15 mV (max)

■

Full-Scale Error −0.75 %FSR (max)

■

Supply Power

■

Normal 1.95 mW (3V) / 4.85 mW (5V) typ

—

■

Power Down 0.3 µW (3V) / 1 µW (5V) typ

—

Applications

Battery-Powered Instruments

■

Digital Gain and Offset Adjustment

■

Programmable Voltage & Current Sources

■

Programmable Attenuators

■

Voltage Reference for ADCs

■

Sensor Supply Voltage

■

Range Detectors

■

A

Ordering Information

Order Numbers Temperature Range Package Top Mark

DAC128S085CISQ

DAC128S085CISQX

DAC128S085CIMT

DAC128S085CIMTX

DAC128S085EB Evaluation Board - BOTH

SPI™ is a trademark of Motorola, Inc.

© 2007 National Semiconductor Corporation 300169 www.national.com

−40°C ≤ TA ≤ +125°C

−40°C ≤ TA ≤ +125°C

−40°C ≤ TA ≤ +125°C

−40°C ≤ TA ≤ +125°C

16-Lead LLP

LLP Tape-and-Reel

16-Lead TSSOP X78C

TSSOP Tape-and-Reel X78C

Block Diagram

DAC128S085

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30016903

Pin Configuration

DAC128S085

30016901

Pin Descriptions

LLP

Pin No.

1 3

2 4

3 5

4 6

5 7

6 8

7 9

8 10 GND Ground Ground reference for all on-chip circuitry.

9 11

10 12

11 13

12 14

13 15 SYNC Digital Input

14 16 SCLK Digital Input

15 1

16 2

17

TSSOP
Pin No.

Symbol Type Description

V

V

V

V

V

V

V

V

V

V

OUTA

OUTB

OUTC

OUTD

V

A

REF1

REF2

OUTH

OUTG

OUTF

OUTE

Analog Output Channel A Analog Output Voltage.

Analog Output Channel B Analog Output Voltage.

Analog Output Channel C Analog Output Voltage.

Analog Output Channel D Analog Output Voltage.

Supply Power supply input. Must be decoupled to GND.

Analog Input

Analog Input

Unbuffered reference voltage shared by Channels A, B, C, and D.
Must be decoupled to GND.

Unbuffered reference voltage shared by Channels E, F, G, and H.
Must be decoupled to GND.

Analog Output Channel H Analog Output Voltage.

Analog Output Channel G Analog Output Voltage.

Analog Output Channel F Analog Output Voltage.

Analog Output Channel E Analog Output Voltage.

Frame Synchronization Input. When this pin goes low, data is
written into the DAC's input shift register on the falling edges of
SCLK. After the 16th falling edge of SCLK, a rising edge of SYNC
causes the DAC to be updated. If SYNC is brought high before the
15th falling edge of SCLK, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the DAC.

Serial Clock Input. Data is clocked into the input shift register on
the falling edges of this pin.

D

IN

D

OUT

Digital Input

Digital Output

Serial Data Input. Data is clocked into the 16-bit shift register on
the falling edges of SCLK after the fall of SYNC.

Serial Data Output. D

is utilized in daisy chain operation and is

OUT

connected directly to a DIN pin on another DAC128S085. Data is
not available at D

unless SYNC remains low for more than 16

OUT

SCLK cycles.

PAD

(LLP only)

Ground

Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance
and enhances package self-alignment during reflow.

30016902

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

DAC128S085

Supply Voltage, V

Voltage on any Input Pin −0.3V to 6.5V
Input Current at Any Pin (Note 3) 10 mA
Package Input Current (Note 3) 30 mA
Power Consumption at TA = 25°C

ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Charge Device Mode

Junction Temperature +150°C
Storage Temperature −65°C to +150°C

A

See (Note 4)

6.5V

2500V

250V

1000V

Operating Ratings (Notes 1, 2)

Operating Temperature Range

Supply Voltage, V

Reference Voltage, V

A

REF1,2

Digital Input Voltage (Note 7) 0.0V to 5.5V
Output Load 0 to 1500 pF
SCLK Frequency Up to 40 MHz

−40°C ≤ TA ≤ +125°C

Package Thermal Resistances

Package

16-Lead LLP 38°C/W

16-Lead TSSOP 130°C/W

Soldering process must comply with National
Semiconductor's Reflow Temperature Profile specifications.

θ

JA

Refer to www.national.com/packaging. (Note 6)

Electrical Characteristics

The following specifications apply for VA = +2.7V to +5.5V, V
range 48 to 4047. Boldface limits apply for T

≤ TA ≤ T

MIN

Symbol Parameter Conditions Typical

STATIC PERFORMANCE

Resolution 12 Bits (min)

Monotonicity 12 Bits (min)

INL Integral Non-Linearity ±2.0 ±8 LSB (max)

DNL Differential Non-Linearity

I

ZE Zero Code Error

FSE Full-Scale Error

OUT

I

OUT

= 0

= 0

GE Gain Error −0.2 −1.0 % FSR (max)

ZCED Zero Code Error Drift −20 µV/°C

TC GE Gain Error Tempco −1.0 ppm/°C

OUTPUT CHARACTERISTICS

Output Voltage Range

I

High-Impedance Output

OZ

Leakage Current (Note 9)

±1 µA (max)

VA = 3V, I

ZCO Zero Code Output

VA = 3V, I

VA = 5V, I

VA = 5V, I

VA = 3V, I

FSO Full Scale Output

VA = 3V, I

VA = 5V, I

VA = 5V, I

VA = 3V, V

I

Output Short Circuit Current

OS

(source) (Note 10)

Input Code = FFFh

VA = 5V, V
Input Code = FFFh

= V

REF1

and all other limits are at TA = 25°C, unless otherwise specified.

MAX

= VA, CL = 200 pF to GND, f

REF2

= 30 MHz, input code

SCLK

Limits

(Note 8)

+0.15 +0.75 LSB (max)

−0.09 −0.4 LSB (min)

+5 +15 mV (max)

−0.1 −0.75 % FSR (max)

0

V

REF1,2

= 200 µA

OUT

= 1 mA

OUT

= 200 µA

OUT

= 1 mA

OUT

= 200 µA

OUT

= 1 mA

OUT

= 200 µA

OUT

= 1 mA

OUT

OUT

OUT

= 0V,

= 0V,

10 mV

45 mV

8 mV

34 mV

2.984 V

2.933 V

4.987 V

4.955 V

−50 mA

−60 mA

+2.7V to 5.5V

+0.5V to V

Units

(Limits)

V (min)

V (max)

A

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DAC128S085

Symbol Parameter Conditions Typical

VA = 3V, V

I

OS

Output Short Circuit Current (sink)
(Note 10)

Input Code = 000h

VA = 5V, V

OUT

OUT

= 3V,

= 5V,

Input Code = 000h

TA = 105°C

TA = 125°C

RL = ∞

RL = 2kΩ

1500 pF

1500 pF

Z

I

O

C

OUT

Continuous Output Current per
channel (Note 9)

Maximum Load Capacitance

L

DC Output Impedance 8

REFERENCE INPUT CHARACTERISTICS

Input Range Minimum 0.5 2.7 V (min)

VREF1,2

Input Range Maximum

Input Impedance 30

LOGIC INPUT CHARACTERISTICS

I

V

V

C

Input Current (Note 9) ±1 µA (max)

IN

Input Low Voltage

IL

Input High Voltage

IH

Input Capacitance (Note 9) 3 pF (max)

IN

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

POWER REQUIREMENTS

V

Supply Voltage Minimum 2.7 V (min)

A

Supply Voltage Maximum 5.5 V (max)

VA = 2.7V

Normal Supply Current for supply
pin V

A

I

N

Normal Supply Current for V
V

REF2

REF1

f

= 30 MHz,

SCLK

output unloaded

or

f

= 30 MHz,

SCLK

output unloaded

to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V

Static Supply Current for supply pin
V

A

I

ST

Static Supply Current for V
V

REF2

REF1

f

SCLK

output unloaded

or

f

SCLK

output unloaded

= 0,

= 0,

to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

f

= 30 MHz, SYNC =

SCLK

VA and DIN = 0V after PD

Total Power Down Supply Current

I

PD

for all PD Modes
(Note 9)

mode loaded

f

= 0, SYNC = VA and

SCLK

DIN = 0V after PD mode
loaded

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

Limits

(Note 8)

Units

(Limits)

50 mA

70 mA

10 mA (max)

6.5 mA (max)

Ω

V

A

V (max)

kΩ

1.0 0.6 V (max)

1.1 0.8 V (max)

1.4 2.1 V (min)

2.0 2.4 V (min)

460 560 µA (max)

650 830 µA (max)

95 130 µA (max)

160 220 µA (max)

370 µA

440 µA

95 µA

160 µA

0.2 1.5 µA (max)

0.5 3.0 µA (max)

0.1 1.0 µA (max)

0.2 2.0 µA (max)

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Symbol Parameter Conditions Typical

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V
to 3.6V

VA = 4.5V

DAC128S085

P

N

Total Power Consumption (output
unloaded)

f

= 30 MHz

SCLK

output unloaded

f

= 0

SCLK

output unloaded

to 5.5V

f

= 30 MHz, SYNC =

SCLK

VA and DIN = 0V after PD

Total Power Consumption in all PD

P

PD

Modes,
(Note 9)

mode loaded

f

= 0, SYNC = VA and

SCLK

DIN = 0V after PD mode
loaded

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

VA = 2.7V
to 3.6V

VA = 4.5V
to 5.5V

1.95 3.0 mW (max)

4.85 7.0 mW (max)

1.68 mW

3.80 mW

0.6 5.4 µW (max)

2.5 16.5 µW (max)

0.3 3.6 µW (max)

1 11 µW (max)

Limits

(Note 8)

A.C. and Timing Characteristics

The following specifications apply for VA = +2.7V to +5.5V, V
48 to 4047. Boldface limits apply for T

≤ TA ≤ T

MIN

and all other limits are at TA = 25°C, unless otherwise specified.

MAX

Symbol Parameter Conductions Typical

f

SCLK Frequency 40 30 MHz (max)

SCLK

Output Voltage Settling Time

t

s

(Note 9)

400h to C00h code change

RL = 2kΩ, CL = 200 pF

SR Output Slew Rate 1 V/µs

GI Glitch Impulse Code change from 800h to 7FFh 40 nV-sec

DF Digital Feedthrough 0.5 nV-sec

DC Digital Crosstalk 0.5 nV-sec

CROSS DAC-to-DAC Crosstalk 1 nV-sec

V

MBW Multiplying Bandwidth

THD+N Total Harmonic Distortion Plus Noise

= 2.5V ± 2Vpp

REF1,2

V

= 2.5V ± 0.5Vpp

REF1,2

100Hz < fIN < 20kHz

ONSD Output Noise Spectral Density DAC Code = 800h, 10kHz 40 nV/sqrt(Hz)

ON Output Noise BW = 30kHz 14 µV

VA = 3V

VA = 5V

1.0 2.5 ns (min)

1.0 2.5 ns (min)

1/f

t

t

WU

SCLK

t

CH

t

CL

t

SS

t

DS

t

DH

t

SH

SYNC

Wake-Up Time

SCLK Cycle Time 25 33 ns (min)

SCLK High time 7 10 ns (min)

SCLK Low Time 7 10 ns (min)

SYNC Set-up Time prior to SCLK
Falling Edge

Data Set-Up Time prior to SCLK
Falling Edge

Data Hold Time after SCLK Falling
Edge

SYNC Hold Time after the 16th falling
edge of SCLK

SYNC High Time 5 15 ns (min)

= VA, CL = 200 pF to GND, f

REF1,2

= 30 MHz, input code range

SCLK

Limits

(Note 8)

6 8.5 µs (max)

360 kHz

−80 dB

3 µsec

20 µsec

3 10 ns (min)

1 / f

SCLK

- 3

0 3 ns (min)

1 / f

SCLK

- 3

Units

(Limits)

Units

(Limits)

ns (max)

ns (max)

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 30 mA maximum package

input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to three.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the operating ratings, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0 Ω. Charge device model
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For

example, if VA is 3V, the digital input pins can be driven with a 5V logic device.

30016904

Note 8: Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 10: This parameter does not represent a condition which the DAC can sustain continuously. See the continuous output current specification for the maximum

DAC output current per channel.

DAC128S085

Timing Diagrams

30016906

FIGURE 1. Serial Timing Diagram

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Specification Definitions

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB,
which is V

DAC128S085

DAC-to-DAC CROSSTALK is the glitch impulse transferred

to a DAC output in response to a full-scale change in the out­put of another DAC.

DIGITAL CROSSTALK is the glitch impulse transferred to a
DAC output at mid-scale in response to a full-scale change in
the input register of another DAC.

DIGITAL FEEDTHROUGH is a measure of the energy inject­ed into the analog output of the DAC from the digital inputs
when the DAC outputs are not updated. It is measured with a
full-scale code change on the data bus.

FULL-SCALE ERROR is the difference between the actual
output voltage with a full scale code (FFFh) loaded into the
DAC and the value of VA x 4095 / 4096.

GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Zero and Full­Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE
is Full-Scale Error and ZE is Zero Error.

GLITCH IMPULSE is the energy injected into the analog out­put when the input code to the DAC register changes. It is
specified as the area of the glitch in nanovolt-seconds.

INTEGRAL NON-LINEARITY (INL) is a measure of the de­viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Tables.

LEAST SIGNIFICANT BIT (LSB) is the bit that has the small­est value or weight of all bits in a word. This value is

/ 4096 = VA / 4096.

REF

LSB = V

REF

/ 2

n

where V
the DAC resolution in bits, which is 12 for the DAC128S085.

is the supply voltage for this product, and "n" is

REF

MAXIMUM LOAD CAPACITANCE is the maximum capaci­tance that can be driven by the DAC with output stability
maintained.

MONOTONICITY is the condition of being monotonic, where
the DAC has an output that never decreases when the input
code increases.

MOST SIGNIFICANT BIT (MSB) is the bit that has the largest
value or weight of all bits in a word. Its value is 1/2 of VA.

MULTIPLYING BANDWIDTH is the frequency at which the
output amplitude falls 3dB below the input sine wave on
V

with the DAC code at full-scale.

REF1,2

NOISE SPECTRAL DENSITY is the internally generated ran­dom noise. It is measured by loading the DAC to mid-scale
and measuring the noise at the output.

POWER EFFICIENCY is the ratio of the output current to the
total supply current. The output current comes from the power
supply. The difference between the supply and output cur­rents is the power consumed by the device without a load.

SETTLING TIME is the time for the output to settle to within
1/2 LSB of the final value after the input code is updated.

TOTAL HARMONIC DISTORTION PLUS NOISE (THD+N)

is the ratio of the harmonics plus the noise present at the out­put of the DACs to the rms level of an ideal sine wave applied
to V

with the DAC code at mid-scale.

REF1,2

WAKE-UP TIME is the time for the output to exit power-down
mode. This is the time from the rising edge of SYNC to when
the output voltage deviates from the power-down voltage of
0V.

ZERO CODE ERROR is the output error, or voltage, present
at the DAC output after a code of 000h has been entered.

Transfer Characteristic

30016905

FIGURE 2. Input / Output Transfer Characteristic

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