National Semiconductor CD4002M, CD4012M, CD4002C, CD4012C Service Manual
CD4002M/CD4002C Dual 4-Input NOR Gate
CD4012M/CD4012C Dual 4-Input NAND Gate
March 1988
CD4002M/CD4002C Dual 4-Input NOR Gate
CD4012M/CD4012C Dual 4-Input NAND Gate
General Description
These NOR and NAND gates are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel
enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply
voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs
are protected against static discharge and latching conditions.
Connection Diagrams
CD4002
Dual-In-Line Package
TL/F/5940– 1
Top View
Order Number CD4002 or CD4012
Features
Y
Wide supply voltage range 3.0V to 15V
Y
Low power 10 nW (typ.)
Y
High noise immunity 0.45 VDD(typ.)
Applications
Y
Automotive
Y
Data terminals
Y
Instrumentation
Y
Medical Electronics
Dual-In-Line Package
Y
Y
Y
Y
CD4012
Top View
Alarm system
Industrial controls
Remote metering
Computers
TL/F/5940– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/5940
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin V
Operating Temperature Range
CD4002M, CD4012M
CD4002C, CD4012C
SS
b
0.3V to V
DD
b
55§Ctoa125§C
b
40§Ctoa85§C
a
0.3V
Storage Temperature Range (T
S
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating Range (V
)V
DD
Lead Temperature (TL)
(Soldering, 10 seconds) 260
b
)
SS
a
3.0V to V
65§Ctoa150§C
SS
DC Electrical Characteristics CD4002M, CD4012M
Limits
Symbol Parameter Conditions
b
55§C
Min Max Min Typ Max Min Max
I
P
V
V
V
V
IDN Output Drive Current V
IDP Output Drive Current V
IDN Output Drive Current V
IDP Output Drive Current V
I
Quiescent V
DD
Device Current V
Quiescent Device V
D
Dissipation/Package V
Output Voltage V
OL
Low Level V
Output Voltage V
OH
High Level V
Noise Immunity V
NL
(All Inputs) V
Noise Immunity V
NH
(All Inputs) V
N-Channel (4002) V
(Note 2)
P-Channel (4002) V
(Note 2)
N-Channel (4012) V
(Note 2)
P-Channel (4012) V
(Note 2)
Input Current 10 pA
I
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: I
N and IDP are tested one output at a time.
D
e
5.0V 0.05 0.001 0.05 3.0 mA
DD
e
10V 0.1 0.001 0.1 6 mA
DD
e
5.0V 0.25 0.005 0.25 15 mW
DD
e
10V 1.0 0.01 1.0 60 mW
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
5.0V, V
10V, V
e
I
e
I
e
I
e
I
e
O
e
O
e
O
e
O
e
O
e
O
e
O
e
O
e
O
e
O
e
O
e
O
VDD,I
VDD,I
VSS,I
VSS,I
3.6V, I
7.2V, I
0.95V, I
2.9V, I
0.4V, V
0.5V, V
2.5V, V
9.5V, V
0.4V, V
0.5V, V
2.5V, V
9.5V, V
e
0A 0.05 0 0.05 0.05 V
O
e
0A 0.05 0 0.05 0.05 V
O
e
0A 4.95 4.95 5.0 4.95 V
O
e
0A 9.95 9.95 10 9.95 V
O
e
0A 1.5 1.5 2.25 1.4 V
O
e
0A 3.0 3.0 4.5 2.9 V
O
e
0A 1.4 1.5 2.25 1.5 V
O
e
0A 2.9 3.0 4.5 3.0 V
O
e
V
I
e
I
e
I
e
I
e
I
e
I
e
I
e
I
0.5 0.40 1.0 0.28 mA
DD
V
1.1 0.9 2.5 0.65 mA
DD
b
V
0.62
SS
b
V
0.62
SS
VDD0.31 0.25 0.5 0.175 mA
V
0.63 0.5 0.6 0.35 mA
DD
b
V
0.31
SS
b
V
0.75
SS
a
b
0.5b2.0
b
0.5b1.0
b
0.25b0.5
b
0.6b1.2
25§C
a
125§C Units
b
0.35 mA
b
0.35 mA
b
0.175 mA
b
0.4 mA
a
15V
C
§
2
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