National Semiconductor CD4010C Service Manual

CD4010C
Hex Buffers (Non-Inverting)

CD4010C Hex Buffers (Non-Inverting)

October 1987
Revised June 2000

General Description

The CD4010C hex b uffers are monolithic compleme ntary
MOS (CMOS) integrated circuit s. The N- and P-channel
enhancement mode transistors provid e a symmetrical c ir­cuit with output swings essent ially equ al to the su pply vo lt­age. This results in high noise immunity over a wide supply
voltage range. No DC power other than that caused by
leakage current is consumed during static conditions. All
inputs are protected agains t static dischar ge. These gates
may be used as hex buffers, CMOS to DTL or TTL inte r­face or as CMOS current drivers. Co nversion ranges are
from 3V to 15V providing V

have buffered outputs which improve tr ansfer character is­tics by providing very high gain.

≤ VDD. The devices also

CC

Features

■ Wide supply voltage range: 3.0V to 15V

■ Low power: 100 nW (typ.)

■ High noise immunity: 0.45 V

■ High current sinking: 8 mA (min.) at V

capability: and V

DD

= 10V

DD

(typ.)

O

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm system

• Industrial controls

• Remote metering

• Computers

= 0.5V

Ordering Code:

Order Number Package Number Package Description

CD4010CM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4010CN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also availab l e in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Schematic Diagram

Hex COS/MOS to DTL or TTL
converter (inverting).
Connect V
Connect V

Top View

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to DTL or TTL suppl y.

CC

to COS/MOS supply.

DD

Absolute Maximum Ratings(Note 1)

Voltage at Any Pin (Note 2) VSS − 0.3V to VSS +15.5V
Operating Temperature Range

CD4010C

Storage Temperature Range (T
Power Dissipation (P

)

D

) −65°C to +150°C

S

Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temper ature (T

)

L

(Soldering, 10 seco nds) 260

Operating Range (V

)V

DD

−45°C to +85°C

+ 3V to VSS + 15V

SS

Note 1: “Absolute Maximum Ratings indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which
the device is functional, but do not guarantee specific performance limits.”

Note 2: This device should not be connected to circuits with the power on

°C

because high transient voltage may cause permanent damage.

DC Electrical Characteristics

Symbol Characteristics (Volts) −40°C +25°C +85°CUnits

I

Quiescent Device 5 3 0.03 3 42 µA

CC

Current 10 5 0.05 5 70 µA

P

Quiescent Device 5 15 0.15 15 210 µW

D

Dissipation/Package 10 50 0.5 50 700 µW
Output Voltage 5 0.01 0 0.01 0.05 V

V

LOW Level 10 0.01 0 0.01 0.05 V

OL

V

HIGH Level 5 4.99 4.99 5 4.95 V

OH

Noise Immunity
(All Inputs)

V

NL

V

NH

Output Drive Current 0.4 5 3.6 3 2.4 mA

N N-Channel (Note 3) 0.5 10 9.6 8 6.4 mA

I

D

I

P P-Channel (Note 3) 2.5 5 −1.5 −1.25 −1mA

D

Input Current 10 pA

I

IN

Note 3: IDN and IDP are tested one output at a time.

Test Conditions Limits

V

VO ≥ 1.5 5 1.6 1.5 2.25 1.4 V

≥ 3.0 10 3.2 3 4.5 2.9 V

V

O

VO ≥ 3.5 5 1.4 1.5 2.25 1.5 V
V

≥ 7.0 10 2.9 3 4.5 3 V

O

9.5 10 −0.72 −0.6 −0.48 mA

V

O

Min Max Min Typ Max Min Max

DD

10 9.99 9.99 10 9.95 V

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