National Semiconductor CD4001BM, CD4011BM, CD4001BC, CD4011BC Service Manual

CD4001BM/CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM/CD4011BC Quad 2-Input NAND Buffered B Series Gate

March 1988

CD4001BM/CD4001BC Quad 2-Input NOR Buffered B Series Gate

CD4011BM/CD4011BC Quad 2-Input NAND Buffered B Series Gate

General Description

These quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.

All inputs are protected against static discharge with diodes to V

and VSS.

DD

Schematic Diagrams

TL/F/5939– 1

Features

Y

Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS

Y

5V–10V–15V parametric ratings

Y

Symmetrical output characteristics

Y

Maximum input leakage 1 m A at 15V over full temperature range

CD4001BC/BM

(/4 of device shown

eAa

J

B

TL/F/5939– 2

Logical ‘‘1’’eHigh Logical ‘‘0’’

*All inputs protected by standard

CMOS protection circuit.

e

Low

CD4011BC/BM

(/4 of device shown

e

A#B

J Logical ‘‘1’’eHigh Logical ‘‘0’’

TL/F/5939– 6

TL/F/5939– 5

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/5939

*All inputs protected by standard

CMOS protection circuit.

e

Low

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Voltage at any Pin

b

0.5V to V

DD

a

0.5V

Operating Conditions

Operating Range (VDD)3V

Operating Temperature Range

CD4001BM, CD4011BM CD4001BC, CD4011BC

Power Dissipation (PD)

Dual-In-Line 700 mW Small Outline 500 mW

V

Range

DD

Storage Temperature (TS)

Lead Temperature (T

(Soldering, 10 seconds) 260

)

L

b

0.5 VDCtoa18 V

b

65§Ctoa150§C

DC

C

§

DC Electrical Characteristics CD4001BM, CD4011BM (Note 2)

b

Symbol Parameter Conditions

I

DD

V

I

OL

Quiescent Device V Current V

Low Level V

OL

Output Voltage V

High Level V

OH

Output Voltage V

Low Level V

IL

Input Voltage V

High Level V

IH

Input Voltage V

Low Level Output V Current V (Note 3) V

I

OH

High Level Output V Current V (Note 3) V

I

IN

Input Current V

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

V

DD

e

5V, V 10V, V 15V, V

IN

IN IN

VDDor V

e

5V 0.05 0 0.05 0.05 V 10VlI

O

15V ( 0.05 0 0.05 0.05 V

5V 4.95 4.95 5 4.95 V 10VlI

O

15V ( 14.95 14.95 15 14.95 V

e

5V, V 10V, V 15V, V

15V, V 15V, V

4.5V 1.5 2 1.5 1.5 V

O

e

O

e

O

e

0.5V 3.5 3.5 3 3.5 V

O

e

O

e

O

e

0.4V 0.64 0.51 0.88 0.36 mA

O

e

O

e

O

e

4.6V

O

e

O

e

O

e

IN

e

IN

SS

VDDor V

SS

VDDor V

SS

k

1 mA 0.05 0 0.05 0.05 V

l

k

1 mA 9.95 9.95 10 9.95 V

l

9.0V 3.0 4 3.0 3.0 V

13.5V 4.0 6 4.0 4.0 V

1.0V 7.0 7.0 6 7.0 V

1.5V 11.0 11.0 9 11.0 V

0.5V 1.6 1.3 2.25 0.9 mA

1.5V 4.2 3.4 8.8 2.4 mA

9.5V

13.5V

0V 15V 0.10 10

55§C

Min Max Min Typ Max Min Max

0.25 0.004 0.25 7.5 mA

0.50 0.005 0.50 15 m A

1.0 0.006 1.0 30 m A

b

0.64

b

1.6

b

4.2

b

0.10

Connection Diagrams

CD4001BC/CD4001BM

Dual-In-Line Package

a

25§C

b

0.51b0.88

b

1.3b2.25

b

3.4

8.8

b

5

b

10

b

5

CD4011BC/CD4011BM

Dual-In-Line Package

to 15 V

DC

b

55§Ctoa125§C

b

40§Ctoa85§C

a

125§C

b

0.36 mA

b

0.9 mA

b

2.4 mA

b

0.10

b

1.0 mA

0.10 1.0 mA

DC

Units

Top View

TL/F/5939– 3

Top View

TL/F/5939– 4

Order Number CD4001B or CD4011B

2

DC Electrical Characteristics CD4001BC, CD4011BC (Note 2)

b

Symbol Parameter Conditions

I

DD

V

I

OL

Quiescent Device V Current V

Low Level V

OL

Output Voltage V

High Level V

OH

Output Voltage V

Low Level V

IL

Input Voltage V

High Level V

IH

Input Voltage V

Low Level Output V Current V (Note 3) V

I

OH

High Level Output V Current V (Note 3) V

I

IN

Input Current V

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

V

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

DD

e

V

DD

e

5V, V 10V, V 15V, V

IN

VDDor V

e

5V 0.05 0 0.05 0.05 V 10VlI

O

15V ( 0.05 0 0.05 0.05 V

5V 4.95 4.95 5 4.95 V 10VlI

O

15V ( 14.95 14.95 15 14.95 V

e

5V, V 10V, V 15V, V

15V, V 15V, V

4.5V 1.5 2 1.5 1.5 V

O

e

O

e

O

e

0.5V 3.5 3.5 3 3.5 V

O

e

O

e

O

e

0.4V 0.52 0.44 0.88 0.36 mA

O

e

O

e

O

e

4.6V

O

e

O

e

O

e

IN

e

IN

SS

VDDor V

SS

VDDor V

SS

k

1 mA 0.05 0 0.05 0.05 V

l

k

1 mA 9.95 9.95 10 9.95 V

l

9.0V 3.0 4 3.0 3.0 V

13.5V 4.0 6 4.0 4.0 V

1.0V 7.0 7.0 6 7.0 V

1.5V 11.0 11.0 9 11.0 V

0.5V 1.3 1.1 2.25 0.9 mA

1.5V 3.6 3.0 8.8 2.4 mA

9.5V

13.5V

0V 15V 0.30 10

40§C

Min Max Min Typ Max Min Max

1 0.004 1 7.5 mA 2 0.005 2 15 mA 4 0.006 4 30 mA

b

0.52

b

1.3

b

3.6

b

0.30

b

0.44b0.88

b

1.1b2.25

b

3.0b8.8

b

a

25§C

b

5

b

10

0.30

b

5

0.30 1.0 mA

a

85§C

b

0.36 mA

b

0.9 mA

b

2.4 mA

b

1.0 mA

Units

AC Electrical Characteristics* CD4001BC, CD4001BM

e

T

25§C, Input tr;t

A

e

f

20 ns. C

L

e

50 pF, R

e

200k. Typical temperature coefficient is 0.3%/§C.

L

Symbol Parameter Conditions Typ Max Units

t

PHL

t

PLH

t

THL,tTLH

C

IN

C

PD

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

Note 2: All voltages measured with respect to V

Note 3: I

and IOHare tested one output at a time.

OL

Propagation Delay Time, V High-to-Low Level V

Propagation Delay Time, V Low-to-High Level V

Transition Time V

Average Input Capacitance Any Input 5 7.5 pF

Power Dissipation Capacity Any Gate 14 pF

unless otherwise specified.

SS

e

5V 120 250 ns

DD

e

10V 50 100 ns

DD

e

V

15V 35 70 ns

DD

e

5V 110 250 ns

DD

e

10V 50 100 ns

DD

e

V

15V 35 70 ns

DD

e

5V 90 200 ns

DD

e

V

10V 50 100 ns

DD

e

V

15V 40 80 ns

DD

3

AC Electrical Characteristics* CD4011BC, CD4011BM

e

T

25§C, Input tr;t

A

e

f

20 ns. C

L

e

50 pF, R

e

200k. Typical Temperature Coefficient is 0.3%/§C.

L

Symbol Parameter Conditions Typ Max Units

t

PHL

t

PLH

t

THL,tTLH

C

IN

C

PD

*AC Parameters are guaranteed by DC correlated testing.

Propagation Delay, V High-to-Low Level V

Propagation Delay, V Low-to-High Level V

Transition Time V

Average Input Capacitance Any Input 5 7.5 pF

Power Dissipation Capacity Any Gate 14 pF

e

5V 120 250 ns

DD

e

10V 50 100 ns

DD

e

V

15V 35 70 ns

DD

e

5V 85 250 ns

DD

e

10V 40 100 ns

DD

e

V

15V 30 70 ns

DD

e

5V 90 200 ns

DD

e

V

10V 50 100 ns

DD

e

V

15V 40 80 ns

DD

Typical Performance Characteristics

Typical Transfer Characteristics

TL/F/5939– 7

Typical Transfer Characteristics

TL/F/5939– 10

Typical Transfer Characteristics

TL/F/5939– 8

TL/F/5939– 11

FIGURE 5

Typical Transfer Characteristics

TL/F/5939– 9

TL/F/5939– 12

FIGURE 6

4

Typical Performance Characteristics (Continued)

FIGURE 7

FIGURE 10

TL/F/5939– 13

TL/F/5939– 16

FIGURE 8

FIGURE 11

TL/F/5939– 14

TL/F/5939– 17

FIGURE 9

TL/F/5939– 15

TL/F/5939– 18

FIGURE 12

FIGURE 13

TL/F/5939– 19

FIGURE 14

TL/F/5939– 20

5

Physical Dimensions inches (millimeters)

Order Number CD4001BMJ, CD4001BCJ, CD40011BMJ or CD4011BCJ

Ceramic Dual-In-Line Package (J)

NS Package Number J14A

Molded Dual-In-Line Package (N)

Order Number CD4001BMN, CD4001BCN, CD4011BMN or CD4011BCN

CD4001BM/CD4001BC Quad 2-Input NOR Buffered B Series Gate

NS Package Number N14A

CD4011BM/CD4011BC Quad 2-Input NAND Buffered B Series Gate

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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