National Semiconductor ADC102S021 Technical data

ADC102S021
2 Channel, 200 KSPS, 10-Bit A/D Converter

ADC102S021 2 Channel, 200 KSPS, 10-Bit A/D Converter

May 2005

General Description

The ADC102S021 is a low-power, two-channel CMOS 10-bit
analog-to-digital converter with a high-speed serial interface.
Unlike the conventional practice of specifying performance
at a single sample rate only, the ADC102S021 is fully speci­fied over a sample rate range of 50 kSPS to 200 kSPS. The
converter is based on a successive-approximation register
architecture with an internal track-and-hold circuit. It can be
configured to accept one or two input signals at inputs IN1
and IN2.

The output serial data is straight binary, and is compatible
with several standards, such as SPI
IRE, and many common DSP serial interfaces.

The ADC102S021 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3V or +5V supply is 1.94 mW and 6.9 mW, respec­tively. The power-down feature reduces the power consump­tion to just 0.12 µW using a +3V supply, or 0.47 µW using a
+5V supply.

The ADC102S021 is packaged in an 8-lead MSOP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.

™

, QSPI™, MICROW-

Features

n Specified over a range of sample rates.
n Two input channels
n Variable power management
n Single power supply with 2.7V - 5.25V range

Key Specifications

n DNL
n INL
n SNR 61.8 dB (typ)
n Power Consumption

— 3V Supply 1.94 mW (typ)
— 5V Supply 6.9 mW (typ)

Applications

n Portable Systems
n Remote Data Aquisitions
n Instrumentation and Control Systems

Pin-Compatible Alternatives by Resolution and Speed

All devices are fully pin and function compatible.

Resolution Specified for Sample Rates of:

50 to 200 kSPS 200 to 500 kSPS 500 kSPS to 1MSPS

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

±

0.13 LSB (typ)

±

0.13 LSB (typ)

Connection Diagram

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Ordering Information

Order Code Temperature Range Description Top Mark

ADC102S021CIMM −40˚C to +85˚C 8-Lead MSOP Package X17C

ADC102S021CIMMX −40˚C to +85˚C 8-Lead MSOP Package, Tape & Reel X17C

ADC102S021EVAL Evaluation Board

TRI-STATE®is a trademark of National Semiconductor Corporation

™

QSPI

and SPI™are trademarks of Motorola, Inc.

© 2005 National Semiconductor Corporation DS201247 www.national.com

Block Diagram

ADC102S021

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

ANALOG I/O

5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to V

DIGITAL I/O

8 SCLK

7 DOUT

6 DIN

1CS

POWER SUPPLY

2V

3 GND The ground return for the analog supply and signals.

A

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.

A

Digital clock input. This clock directly controls the conversion
and readout processes.

Digital data output. The output samples are clocked out of this
pin on falling edges of the SCLK pin.

Digital data input. The ADC102S021’s Control Register is
loaded through this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process
begins. Conversions continue as long as CS is held low.

Positive supply pin. This pin should be connected to a quiet
+2.7V to +5.25V source and bypassed to GND witha1µF
capacitor and a 0.1 µF monolithic capacitor located within 1
cm of the power pin.

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ADC102S021

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Analog Supply Voltage V

A

Voltage on Any Pin to GND −0.3V to V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Power Consumption at T

= 25˚C See (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model
Machine Model

Junction Temperature +150˚C

Storage Temperature −65˚C to +150˚C

−0.3V to 6.5V

+0.3V

A

±

10 mA

±

20 mA

2500V

250V

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T

V

Supply Voltage +2.7V to +5.25V

A

Digital Input Pins Voltage Range −0.3V to V

Clock Frequency 0.8 to 3.2 MHz

Analog Input Voltage 0V to V

Package Thermal Resistance

Package θ

8-lead MSOP 250˚C / W

Soldering process must comply with National Semiconduc­tor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)

ADC102S021 Converter Electrical Characteristics (Note 9)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, CL= 50 pF, f
f

= 50 kSPS to 200 kSPS, unless otherwise noted. Boldface limits apply for TA=T

SAMPLE

25˚C.

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 10 Bits

INL Integral Non-Linearity

DNL Differential Non-Linearity

V

OFF

OEM

Offset Error +0.1

Channel to Channel Offset Error
Match

FSE Full-Scale Error −0.11

FSEM

Channel to Channel Full-Scale Error
Match

DYNAMIC CONVERTER CHARACTERISTICS

V

= +2.7 to 5.25V

SINAD Signal-to-Noise Plus Distortion Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

SFDR Spurious-Free Dynamic Range

ENOB Effective Number of Bits

Channel-to-Channel Crosstalk

Intermodulation Distortion, Second

IMD

Order Terms

Intermodulation Distortion, Third
Order Terms

FPBW -3 dB Full Power Bandwidth

A

= 39.9 kHz, −0.02 dBFS

f

IN

V

= +2.7 to 5.25V

A

= 39.9 kHz, −0.02 dBFS

f

IN

V

= +2.7 to 5.25V

A

= 39.9 kHz, −0.02 dBFS

f

IN

V

= +2.7 to 5.25V

A

= 39.9 kHz, −0.02 dBFS

f

IN

V

= +2.7 to 5.25V

A

= 39.9 kHz, −0.02 dBFS

f

IN

V

= +5.25V

A

= 39.9 kHz

f

IN

V

= +5.25V

A

= 40.161 kHz, fb= 41.015 kHz

f

a

V

= +5.25V

A

= 40.161 kHz, fb= 41.015 kHz

f

a

V

= +5V 11 MHz

A

V

= +3V 8 MHz

A

= 0.8 MHz to 3.2 MHz,

SCLK

MIN

±

0.13

±

0.13

±

0.02

+0.02

61.8 61 dB (min)

61.8 61.3 dB (min)

−86 −72 dB (max)

82 75 dB (min)

9.9 9.8 Bits (min)

−87 dB

−82 dB

−81 dB

JA

to T

: all other limits TA=

MAX

Limits

(Note 9)

+0.3 LSB (max)

−0.4 LSB (min)

±

0.4 LSB (max)

±

0.4 LSB (max)

±

0.5 LSB (max)

±

0.7 LSB (max)

±

0.5 LSB (max)

≤ +85˚C

A

Units

A

A

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ADC102S021 Converter Electrical Characteristics (Note 9) (Continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, CL= 50 pF, f
f

= 50 kSPS to 200 kSPS, unless otherwise noted. Boldface limits apply for TA=T

SAMPLE

25˚C.

ADC102S021

Symbol Parameter Conditions Typical

ANALOG INPUT CHARACTERISTICS

V

IN

I

DCL

C

INA

DIGITAL INPUT CHARACTERISTICS

V

IH

V

IL

I

IN

C

IND

DIGITAL OUTPUT CHARACTERISTICS

V

OH

V

OL

I

OZH

I

OZL

C

OUT

POWER SUPPLY CHARACTERISTICS (C

V

A

I

A

P

D

AC ELECTRICAL CHARACTERISTICS

f

SCLK

f

S

t

CONV

DC SCLK Duty Cycle f

t

ACQ

Input Range 0 to V

DC Leakage Current

Input Capacitance

Input High Voltage

Track Mode 33 pF

Hold Mode 3 pF

= +5.25V 2.4 V (min)

V

A

V

= +3.6V 2.1 V (min)

A

Input Low Voltage 0.8 V (max)

Input Current VIN=0VorV

A

Digital Input Capacitance 2 4 pF (max)

Output High Voltage

Output Low Voltage

,

TRI-STATE®Leakage Current

I

SOURCE

I

SOURCE

I

SINK

I

SINK

= 200 µA VA− 0.03 VA− 0.5 V (min)

=1mA VA− 0.1 V

= 200 µA 0.03 0.4 V (max)

= 1 mA 0.1 V

TRI-STATE®Output Capacitance 2 4 pF (max)

Output Coding Straight (Natural) Binary

=10pF)

L

Supply Voltage

VA= +5.25V,
Supply Current, Normal Mode
(Operational, CS low)

f

V

f

= 200 kSPS, fIN=40kHz

SAMPLE

= +3.6V,

A

= 200 kSPS, fIN=40kHz

SAMPLE

VA= +5.25V,

Supply Current, Shutdown (CS high)

Power Consumption, Normal Mode
(Operational, CS low)

Power Consumption, Shutdown (CS
high)

f

V

f

VA= +5.25V 6.9 9.5 mW (max)

V

V

V

= 0 kSPS

SAMPLE

= +3.6V,

A

= 0 kSPS

SAMPLE

= +3.6V 1.94 2.5 mW (max)

A

= +5.25V 0.47 µW

A

= +3.6V 0.12 µW

A

Clock Frequency (Note 8)

Sample Rate (Note 8)

Conversion Time 13 SCLK cycles

= 3.2 MHz 50

CLK

Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

= 0.8 MHz to 3.2 MHz,

SCLK

±

±

0.01

1.3 1.8 mA (max)

0.55 0.7 mA (max)

MIN

0.1

to T

A

: all other limits TA=

MAX

Limits

(Note 9)

±

1 µA (max)

±

10 µA (max)

±

1 µA (max)

Units

2.7 V (min)

5.25 V (max)

90 nA

32 nA

0.8 MHz (min)

3.2 MHz (max)

50 kSPS (min)

200 kSPS (max)

30 % (min)

70 % (max)

V

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ADC102S021 Timing Specifications

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, CL= 50 pF, f
f

SAMPLE

= 50 kSPS to 200 kSPS, Boldface limits apply for TA=T

MIN

to T

: all other limits TA= 25˚C.

MAX

Symbol Parameter Conditions Typical

= +3.0V −3.5

V

t

t

t

CSU

CLH

t

ACC

t

t

t

Setup Time SCLK High to CS Falling Edge (Note 10)

Hold time SCLK Low to CS Falling Edge (Note 10)

Delay from CS Until DOUT active

EN

Data Access Time after SCLK Falling Edge

Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)

SU

t

Data Valid SCLK Hold Time +3 10 ns (min)

H

SCLK High Pulse Width

CH

SCLK Low Pulse Width

CL

Output Falling

t

DIS

CS Rising Edge to DOUT High-Impedance

Output Rising

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply (that is, V

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V

Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms

Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under

Operating Ratings.

Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 10: Clock may be in any state (high or low) when CS is asserted, with the restrictions on setup and hold time given by t

), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. The values

JA

pin. The current into the VApin is limited by the Analog Supply Voltage specification.

A

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

J

IN

<

GND or V

A

V

= +5.0V −0.5

A

= +3.0V +4.5

V

A

V

= +5.0V +1.5

A

VA= +3.0V +4

V

= +5.0V +2

A

= +3.0V +16.5

V

A

V

= +5.0V +15

A

= +3.0V 1.7

V

A

V

= +5.0V 1.2

A

V

= +3.0V 1.0

A

V

= +5.0V 1.0

A

>

VA), the current at that pin should be limited to 10 mA. The 20

IN

= 0.8 MHz to 3.2 MHz,

SCLK

0.5 x

t

SCLK

0.5 x

t

SCLK

CSU

and t

Limits

(Note 7)

0.3 x

t

SCLK

0.3 x

t

SCLK

.

CLH

Units

10 ns (min)

10 ns (min)

30

30

(max)

(max)

ns (min)

ns (min)

20

(max)

ADC102S021

ns

ns

ns

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Timing Diagrams

ADC102S021

ADC102S021 Operational Timing Diagram

20124708

Timing Test Circuit

20124751

ADC102S021 Serial Timing Diagram

SCLK and CS Timing Parameters

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20124750