National Instruments DAQ S User Manual

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DAQ S Series

NI 6124/6154 User Manual

DAQ-STC2 S Series Simultaneous Sampling Multifunction Input/Output Devices

NI 6124/6154 User Manual

August 2008 372613A-01

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NI 6124 and NI 6154 devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

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Compliance

Compliance with FCC/Canada Radio Frequency Interference Regulations

Determining FCC Class

The Federal Communications Commission (FCC) has rules to protect wireless communications from interference. The FCC places digital electronics into two classes. These classes are known as Class A (for use in industrial-commercial locations only) or Class B (for use in residential or commercial locations). All National Instruments (NI) products are FCC Class A products.

Depending on where it is operated, this Class A product could be subject to restrictions in the FCC rules. (In Canada, the Department of Communications (DOC), of Industry Canada, regulates wireless interference in much the same way.) Digital electronics emit weak signals during normal operation that can affect radio, television, or other wireless products.

All Class A products display a simple warning statement of one paragraph in length regarding interference and undesired operation. The FCC rules have restrictions regarding the locations where FCC Class A products can be operated.

Consult the FCC Web site at

FCC/DOC Warnings

This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual and the CE marking Declaration of Conformity*, may cause interference to radio and television reception. Classification requirements are the same for the Federal Communications Commission (FCC) and the Canadian Department of Communications (DOC).

Changes or modifications not expressly approved by NI could void the user’s authority to operate the equipment under the FCC Rules.

Class A

Federal Communications Commission

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference at their own expense.

www.fcc.gov for more information.

Canadian Department of Communications

This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations. Cet appareil numérique de la classe A respecte toutes les exigences du Règlement sur le matériel brouilleur du Canada.

Compliance with EU Directives

Users in the European Union (EU) should refer to the Declaration of Conformity (DoC) for information* pertaining to the CE marking. Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory compliance information. To obtain the DoC for this product, visit and click the appropriate link in the Certification column.

* The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or

installer.

ni.com/certification, search by model number or product line,

About This Manual

Conventions ...................................................................................................................xi

Related Documentation..................................................................................................xii

Chapter 1 Getting Started

Installing NI-DAQmx ....................................................................................................1-1

Installing Other Software...............................................................................................1-1

Installing the Hardware..................................................................................................1-2

Device Self-Calibration .................................................................................................1-2

Device Pinouts ...............................................................................................................1-3

Device Specifications ....................................................................................................1-3

Chapter 2 DAQ System Overview

DAQ Hardware ..............................................................................................................2-2

DAQ-STC2......................................................................................................2-3

Calibration Circuitry ......................................................................................................2-4

Internal or Self-Calibration..............................................................................2-4

External Calibration.........................................................................................2-5

Signal Conditioning .......................................................................................................2-5

Sensors and Transducers................................................................................................2-5

Programming Devices in Software ................................................................................2-6

Chapter 3 I/O Connector

NI 6124 I/O Connector Signal Descriptions..................................................................3-1

NI 6154 I/O Connector Signal Descriptions..................................................................3-2

+5 V Power Source ........................................................................................................3-3

Chapter 4 Analog Input

Analog Input Terminal Configuration ...........................................................................4-2

Input Polarity and Range ...............................................................................................4-3

Working Voltage Range ................................................................................................4-4

AI Data Acquisition Methods ........................................................................................4-4

Analog Input Triggering ................................................................................................4-6

Contents

Connecting Analog Input Signals.................................................................................. 4-6

Types of Signal Sources.................................................................................. 4-7

Differential Connections for Ground-Referenced Signal Sources.................. 4-7

Common-Mode Signal Rejection Considerations ............................ 4-9

Differential Connections for Non-Referenced or Floating Signal Sources .... 4-9

DC-Coupled...................................................................................... 4-10

AC-Coupled...................................................................................... 4-11

Field Wiring Considerations ........................................................................... 4-11

Minimizing Drift in Differential Mode........................................................... 4-12

Analog Input Timing Signals ........................................................................................ 4-13

AI Sample Clock Signal.................................................................................. 4-14

Using an Internal Source .................................................................. 4-14

Using an External Source ................................................................. 4-15

Routing AI Sample Clock Signal to an Output Terminal................. 4-15

Other Timing Requirements ............................................................. 4-15

AI Sample Clock Timebase Signal ................................................................. 4-16

AI Convert Clock Signal................................................................................. 4-16

Using an Internal Source .................................................................. 4-17

Using an External Source ................................................................. 4-17

Routing AI Convert Clock Signal to an Output Terminal ................ 4-17

AI Convert Clock Timebase Signal ................................................................ 4-17

AI Hold Complete Event Signal ..................................................................... 4-18

AI Start Trigger Signal.................................................................................... 4-18

Using a Digital Source...................................................................... 4-18

Using an Analog Source ................................................................... 4-19

Routing AI Start Trigger to an Output Terminal .............................. 4-19

AI Reference Trigger Signal ........................................................................... 4-19

Using a Digital Source...................................................................... 4-20

Using an Analog Source ................................................................... 4-20

Routing AI Reference Trigger Signal to an Output Terminal .......... 4-20

Getting Started with AI Applications in Software ........................................................ 4-21

Chapter 5 Analog Output

Minimizing Glitches on the Output Signal.................................................................... 5-2

AO Data Generation Methods ....................................................................................... 5-2

Analog Output Triggering .............................................................................................5-4

Connecting Analog Output Signals ............................................................................... 5-4

Waveform Generation Timing Signals.......................................................................... 5-6

AO Sample Clock Signal ................................................................................ 5-6

Using an Internal Source .................................................................. 5-6

Using an External Source ................................................................. 5-7

Routing AO Sample Clock Signal to an Output Terminal ............... 5-7

NI 6124/6154 User Manual vi ni.com

Getting Started with AO Applications in Software .......................................................5-11

Chapter 6 Digital I/O

Digital I/O for Non-Isolated Devices.............................................................................6-1

Digital I/O for Isolated Devices.....................................................................................6-11

Contents

Other Timing Requirements..............................................................5-7

AO Sample Clock Timebase Signal................................................................5-8

AO Start Trigger Signal...................................................................................5-9

Using a Digital Source ......................................................................5-9

Using an Analog Source ...................................................................5-10

Routing AO Start Trigger Signal to an Output Terminal..................5-10

AO Pause Trigger Signal.................................................................................5-10

Using a Digital Source ......................................................................5-11

Using an Analog Source ...................................................................5-11

Static DIO for Non-Isolated Devices ..............................................................6-2

Digital Waveform Triggering for Non-Isolated Devices ................................6-3

Digital Waveform Acquisition for Non-Isolated Devices ...............................6-3

DI Sample Clock Signal....................................................................6-4

Digital Waveform Generation for Non-Isolated Devices................................6-5

DO Sample Clock Signal ..................................................................6-5

I/O Protection for Non-Isolated Devices .........................................................6-7

Programmable Power-Up States for Non-Isolated Devices ............................6-7

DI Change Detection for Non-Isolated Devices..............................................6-8

DI Change Detection Applications for Non-Isolated Devices..........6-9

Connecting Digital I/O Signals on Non-Isolated Devices...............................6-9

Getting Started with DIO Applications in Software on Non-Isolated Devices ..... 6-10

Static DIO for Isolated Devices.......................................................................6-11

I/O Protection for Isolated Devices .................................................................6-12

Connecting Digital I/O Signals on Isolated Devices .......................................6-12

Getting Started with DIO Applications in Software on Isolated Devices .......6-13

Chapter 7 Counters

Counter Input Applications............................................................................................7-2

Counting Edges ...............................................................................................7-2

Single Point (On-Demand) Edge Counting ......................................7-2

Buffered (Sample Clock) Edge Counting .........................................7-3

Controlling the Direction of Counting ..............................................7-4

Pulse-Width Measurement ..............................................................................7-4

Single Pulse-Width Measurement.....................................................7-4

Buffered Pulse-Width Measurement.................................................7-5

Contents

Period Measurement ....................................................................................... 7-6

Single Period Measurement.............................................................. 7-6

Buffered Period Measurement.......................................................... 7-7

Semi-Period Measurement.............................................................................. 7-7

Single Semi-Period Measurement .................................................... 7-8

Buffered Semi-Period Measurement ................................................ 7-8

Frequency Measurement ................................................................................. 7-9

Choosing a Method for Measuring Frequency ................................. 7-12

Position Measurement..................................................................................... 7-14

Measurements Using Quadrature Encoders...................................... 7-14

Measurements Using Two Pulse Encoders ...................................... 7-16

Buffered (Sample Clock) Position Measurement ............................. 7-17

Two-Signal Edge-Separation Measurement ................................................... 7-17

Single Two-Signal Edge-Separation Measurement.......................... 7-18

Buffered Two-Signal Edge-Separation Measurement...................... 7-18

Counter Output Applications......................................................................................... 7-19

Simple Pulse Generation.................................................................................7-19

Single Pulse Generation.................................................................... 7-19

Single Pulse Generation with Start Trigger...................................... 7-20

Retriggerable Single Pulse Generation............................................. 7-20

Pulse Train Generation.................................................................................... 7-21

Continuous Pulse Train Generation.................................................. 7-21

Finite Pulse Train Generation........................................................... 7-22

Frequency Generation ..................................................................................... 7-23

Using the Frequency Generator ........................................................ 7-23

Frequency Division ......................................................................................... 7-24

Pulse Generation for ETS ............................................................................... 7-24

Counter Timing Signals................................................................................................. 7-25

Counter n Source Signal ................................................................................. 7-26

Routing a Signal to Counter n Source .............................................. 7-26

Routing Counter n Source to an Output Terminal............................ 7-27

Counter n Gate Signal..................................................................................... 7-27

Routing a Signal to Counter n Gate .................................................. 7-27

Routing Counter n Gate to an Output Terminal ............................... 7-27

Counter n Aux Signal...................................................................................... 7-28

Routing a Signal to Counter n Aux .................................................. 7-28

Counter n A, Counter n B, and Counter n Z Signals ...................................... 7-28

Routing Signals to A, B, and Z Counter Inputs................................ 7-28

Routing Counter n Z Signal to an Output Terminal ......................... 7-28

Counter n Up_Down Signal............................................................................ 7-29

Counter n HW Arm Signal.............................................................................. 7-29

Routing Signals to Counter n HW Arm Input.................................. 7-29

Counter n Internal Output and Counter n TC Signals..................................... 7-29

Routing Counter n Internal Output to an Output Terminal .............. 7-30

NI 6124/6154 User Manual viii ni.com

Frequency Output Signal.................................................................................7-30

Routing Frequency Output to a Terminal .........................................7-30

Default Counter/Timer Pinouts......................................................................................7-30

Counter Triggering ........................................................................................................7-31

Other Counter Features..................................................................................................7-32

Cascading Counters .........................................................................................7-32

Counter Filters .................................................................................................7-32

Prescaling ........................................................................................................7-33

Duplicate Count Prevention ............................................................................7-34

Example Application That Works Correctly (No Duplicate Counting) ... 7-35

Example Application That Works Incorrectly (Duplicate Counting) ....7-36

Example Application That Prevents Duplicate Count ......................7-36

When To Use Duplicate Count Prevention.......................................7-37

Enabling Duplicate Count Prevention in NI-DAQmx ......................7-37

Synchronization Modes ...................................................................................7-37

80 MHz Source Mode .......................................................................7-38

Other Internal Source Mode..............................................................7-39

External Source Mode.......................................................................7-39

Chapter 8 Programmable Function Interfaces (PFI)

PFI for Non-Isolated Devices ........................................................................................8-1

PFI for Isolated Devices ................................................................................................8-2

Using PFI Terminals as Timing Input Signals...............................................................8-4

Exporting Timing Output Signals Using PFI Terminals ...............................................8-4

Using PFI Terminals as Static Digital Inputs and Outputs ............................................8-5

Connecting PFI Input Signals ........................................................................................8-6

PFI Filters ......................................................................................................................8-6

I/O Protection.................................................................................................................8-8

Programmable Power-Up States....................................................................................8-8

Contents

Chapter 9 Digital Routing and Clock Generation

Clock Routing ................................................................................................................9-1

80 MHz Timebase ...........................................................................................9-2

20 MHz Timebase ...........................................................................................9-2

100 kHz Timebase...........................................................................................9-2

External Reference Clock................................................................................9-2

10 MHz Reference Clock ................................................................................9-3

Synchronizing Multiple Devices ...................................................................................9-3

Contents

Real-Time System Integration (RTSI) ..........................................................................9-4

PXI Clock and Trigger Signals...................................................................................... 9-8

Routing Signals in Software.......................................................................................... 9-10

Chapter 10 Bus Interface

MITE and DAQ-PnP ..................................................................................................... 10-1

PXI Considerations........................................................................................................ 10-1

Data Transfer Methods .................................................................................................. 10-2

RTSI Connector Pinout................................................................................... 9-4

Using RTSI as Outputs ................................................................................... 9-5

Using RTSI Terminals as Timing Input Signals ............................................. 9-6

RTSI Filters.....................................................................................................9-6

PXI_CLK10 .................................................................................................... 9-8

PXI Triggers.................................................................................................... 9-8

PXI_STAR Trigger ......................................................................................... 9-8

PXI_STAR Filters........................................................................................... 9-9

PXI Clock and Trigger Signals ....................................................................... 10-1

PXI Express..................................................................................................... 10-1

Changing Data Transfer Methods between DMA and IRQ............................ 10-2

Chapter 11 Triggering

Triggering with a Digital Source...................................................................................11-1

Triggering with an Analog Source ................................................................................ 11-2

Analog Input Channel ..................................................................................... 11-3

Analog Trigger Actions .................................................................................. 11-3

Analog Trigger Types.................................................................................................... 11-3

Analog Trigger Accuracy .............................................................................................. 11-6

Appendix A Device-Specific Information

Appendix B Technical Support and Professional Services

Glossary

Index

NI 6124/6154 User Manual x ni.com

About This Manual

The NI 6124/6154 User Manual contains information about using the National Instruments S Series NI 6124 and NI 6154 data acquisition (DAQ) devices with NI-DAQmx 8.8 and later.

Conventions

The following conventions appear in this manual:

<> Angle brackets that contain numbers separated by an ellipsis represent

a range of values associated with a bit or signal name—for example, AO <3. .0>.

» The » symbol leads you through nested menu items and dialog box options

to a final action. The sequence File»Page Setup»Options directs you to pull down the File menu, select the Page Setup item, and select Options from the last dialog box.

This icon denotes a note, which alerts you to important information.

This icon denotes a caution, which advises you of precautions to take to avoid injury, data loss, or a system crash. When this symbol is marked on a product, refer to the Read Me First: Safety and Radio-Frequency Interference document for information about precautions to take.

bold Bold text denotes items that you must select or click in the software, such

as menu items and dialog box options. Bold text also denotes parameter names.

italic Italic text denotes variables, emphasis, a cross-reference, or an introduction

to a key concept. Italic text also denotes text that is a placeholder for a word or value that you must supply.

monospace Text in this font denotes text or characters that you should enter from the

keyboard, sections of code, programming examples, and syntax examples. This font is also used for the proper names of disk drives, paths, directories, programs, subprograms, subroutines, device names, functions, operations, variables, filenames, and extensions.

Platform Text in this font denotes a specific platform and indicates that the text

following it applies only to that platform.

About This Manual

Installing NI-DAQmx

The DAQ Getting Started Guide, which you can download at ni.com/

manuals, offers NI-DAQmx users step-by-step instructions for installing

software and hardware, configuring channels and tasks, and getting started developing an application.

Installing Other Software

If you are using other software, refer to the installation instructions that accompany your software.

Chapter 1 Getting Started

Installing the Hardware

The DAQ Getting Started Guide contains non-software-specific information about how to install PCI and PXI Express devices, as well as accessories and cables.

Device Self-Calibration

NI recommends that you self-calibrate your S Series device after installation and whenever the ambient temperature changes. Self-calibration should be performed after the device has warmed up for the recommended time period. Refer to the device specifications to find your device warm-up time. This function measures the onboard reference voltage of the device and adjusts the self-calibration constants to account for any errors caused by short-term fluctuations in the environment. Disconnect all external signals when you self-calibrate a device.

You can initiate self-calibration using Measurement & Automation Explorer (MAX), by completing the following steps.

1. Launch MAX.

2. Select My System»Devices and Interfaces»NI-DAQmx Devices»your device.

3. Initiate self-calibration using one of the following methods:

•Click Self-Calibrate in the upper right corner of MAX.

• Right-click the name of the device in the MAX configuration tree

and select Self-Calibrate from the drop-down menu.

Note You can also programmatically self-calibrate your device with NI-DAQmx,

as described in Device Calibration in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

NI 6124/6154 User Manual 1-2 ni.com

Device Pinouts

Refer to Appendix A, Device-Specific Information, for NI 6124 and NI 6154 device pinouts.

Device Specifications

Refer to the specifications for your device, the NI 6124 Specifications or the NI 6154 Specifications, available on the NI-DAQ Device Document Browser or NI 6124 and NI 6154 devices.

Chapter 1 Getting Started

ni.com/manuals, for more detailed information about the

DAQ System Overview

Figure 2-1 shows a typical DAQ system setup, which includes transducers, signal conditioning, cables that connect the various devices to the accessories, the S Series device, and the programming software. Refer to Appendix A, Device-Specific Information, for a list of devices and their compatible accessories.

–

1 Sensors and Transducers 2 Signal Conditioning 3 Cable Assembly

Figure 2-1. Typical DAQ System

4 DAQ Hardware 5 Personal Computer/Chassis

and DAQ Software

Chapter 2 DAQ System Overview

DAQ Hardware

DAQ hardware digitizes signals, performs D/A conversions to generate analog output signals, and measures and controls digital I/O signals. The following sections contain more information about specific components of the DAQ hardware.

Figure 2-2 shows the components of the non-isolated S Series (NI 6124) device.

Analog Input

Analog Output

Digital I/O

I/O Connector

Counters

PFI

Digital

Routing

RTSI

Figure 2-2. General NI 6124 Block Diagram

Bus

Interface

Bus

NI 6124/6154 User Manual 2-2 ni.com

Analog Input

Analog Output

Counters

I/O Connector

PFI/Static DI

Chapter 2 DAQ System Overview

(NI 6154 Only) S Series isolated hardware also includes bank and

channel-to-channel isolation. Isolated DAQ hardware allows for increased protection against hazardous voltages, rejection of common-mode voltages, and reduction of ground loops and their associated noise. Figure 2-3 shows the components of the isolated S Series (NI 6154) device.

Isolation

Barrier

AI GND

AO GND

P0.GND

Digital

Isolators

Digital

Routing

RTSI

Bus

Interface

Bus

PFI/Static DO

P1.GND

Figure 2-3. General NI 6154 Block Diagram

DAQ-STC2

The DAQ-STC2 implements a high-performance digital engine for S Series data acquisition hardware. Some key features of this engine include the following:

• Flexible AI and AO sample and convert timing

• Many triggering modes

• Independent AI, AO, DI, and DO FIFOs

• Generation and routing of RTSI signals for multi-device synchronization

• Generation and routing of internal and external timing signals

Chapter 2 DAQ System Overview

• Two flexible 32-bit counter/timer modules with hardware gating

• Digital waveform acquisition and generation

• Static DIO signals

• True 5 V high current drive DO

• PLL for clock synchronization

• PCI/PXI interface

• Independent scatter-gather DMA controllers for all acquisition and generation functions

Calibration Circuitry

Calibration is the process of making adjustments to a measurement device to reduce errors associated with measurements. Without calibration, the measurement results of your device will drift over time and temperature. Calibration adjusts for these changes to improve measurement accuracy and ensure that your product meets its required specifications.

DAQ devices have high precision analog circuits that must be adjusted to obtain optimum accuracy in your measurements. Calibration determines what adjustments these analog circuits should make to the device measurements. During calibration, the value of a known, high precision measurement source is compared to the value your device acquires or generates. The adjustment values needed to minimize the difference between the known and measured values are stored in the EEPROM of the device as calibration constants. Before performing a measurement, these constants are read out of the EEPROM and are used to adjust the calibration hardware on the device. NI-DAQmx determines when this is necessary and does it automatically. If you are not using NI-DAQmx, you must load these values yourself.

You can calibrate S Series devices in two ways—through internal (or self-calibration) or through external calibration.

Internal or Self-Calibration

Self-calibration is a process to adjust the device relative to a highly accurate and stable internal reference on the device. Self-calibration is similar to the autocalibration or autozero found on some instruments. You should perform a self-calibration whenever environmental conditions, such as ambient temperature, change significantly. To perform self-calibration, use the self-calibrate function or VI that is included with your driver software. Self-calibration requires no external connections.

NI 6124/6154 User Manual 2-4 ni.com

External Calibration

External calibration is a process to adjust the device relative to a traceable, high precision calibration standard. The accuracy specifications of your device change depending on how long it has been since your last external calibration. National Instruments recommends that you calibrate your device at least as often as the intervals listed in the accuracy specifications.

For a detailed calibration procedure for NI 6154 S Series devices, refer to the Isolated M/S Series Calibration Procedure, which you can find at

ni.com/calibration and selecting Manual Calibration Procedures.

Signal Conditioning

Many sensors and transducers require signal conditioning before a computer-based measurement system can effectively and accurately acquire the signal. The front-end signal conditioning system can include functions such as signal amplification, attenuation, filtering, electrical isolation, simultaneous sampling, and multiplexing. In addition, many transducers require excitation currents or voltages, bridge completion, linearization, or high amplification for proper and accurate operation. Therefore, most computer-based measurement systems include some form of signal conditioning in addition to plug-in data acquisition DAQ devices.

Chapter 2 DAQ System Overview

Sensors and Transducers

Sensors can generate electrical signals to measure physical phenomena, such as temperature, force, sound, or light. Some commonly used sensors are strain gages, thermocouples, thermistors, angular encoders, linear encoders, and resistance temperature detectors (RTDs).

To measure signals from these various transducers, you must convert them into a form that a DAQ device can accept. For example, the output voltage of most thermocouples is very small and susceptible to noise. Therefore, you may need to amplify or filter the thermocouple output before digitizing it. The manipulation of signals to prepare them for digitizing is called signal conditioning.

For more information about sensors, refer to the following documents.

• For general information about sensors, visit

• If you are using LabVIEW, refer to the LabVIEW Help by selecting

Help»Search the LabVIEW Help in LabVIEW and then navigate to the Taking Measurements book on the Contents tab.

ni.com/sensors.

Chapter 2 DAQ System Overview

• If you are using other application software, refer to Common Sensors in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

Programming Devices in Software

National Instruments measurement devices are packaged with NI-DAQmx driver software, an extensive library of functions and VIs you can call from your application software, such as LabVIEW or LabWindows/CVI, to program all the features of your NI measurement devices. NI-DAQmx driver software has an application programming interface (API), which is a library of VIs, functions, classes, attributes, and properties for creating applications for your device.

NI-DAQ includes two NI-DAQ drivers—Traditional NI-DAQ (Legacy) and NI-DAQmx. DAQ-STC2-based S Series devices use the NI-DAQmx driver. Each driver has its own API, hardware configuration, and software configuration. Refer to the DAQ Getting Started Guide for more information about the two drivers.

NI-DAQmx includes a collection of programming examples to help you get started developing an application. You can modify example code and save it in an application. You can use examples to develop a new application or add example code to an existing application.

To locate LabVIEW and LabWindows/CVI examples, open the National Instruments Example Finder. In LabVIEW and LabWindows/CVI, select Help»Find Examples.

Measurement Studio, Visual Basic, and ANSI C examples are in the following directories:

• NI-DAQmx examples for Measurement Studio-supported languages are in the following directories:

– MeasurementStudio\VCNET\Examples\NIDaq

– MeasurementStudio\DotNET\Examples\NIDaq

• NI-DAQmx examples for ANSI C are in the NI-DAQ\Examples\

DAQmx ANSI C Dev

For additional examples, refer to

NI 6124/6154 User Manual 2-6 ni.com

NI 6124 I/O Connector Signal Descriptions

(NI 6124 Only) Table 3-1 describes the signals found on the NI 6124 I/O

connector. For more information about these signals, refer to the NI 6124 Specifications.

Table 3-1. NI 6124 Device Signal Descriptions

I/O Connector Pin Reference Direction Signal Description

AI <0..3> GND — — Analog Input Channels 0 through 3 Ground—These

pins are the bias current return point for differential measurements.

AI <0..3> + AI <0..3> GND Input Analog Input Channels 0 through 3 (+)—These pins

AI <0..3> – AI <0..3> GND Input Analog Input Channels 0 through 3 (–)—These pins

AO <0..1> AO GND Output Analog Output Channels 0 through 1—These pins

AO GND — — Analog Output Ground—The AO voltages and the

D GND — — Digital Ground—These pins supply the reference for the

are routed to the (+) terminal of the respective channel amplifier.

are routed to the (–) terminal of the respective channel amplifier.

supply the voltage output of analog output channels 0 and 1.

external reference voltage are referenced to these pins.

digital signals at the I/O connector and the +5 VDC supply.

Chapter 3 I/O Connector

Table 3-1. NI 6124 Device Signal Descriptions (Continued)

I/O Connector Pin Reference Direction Signal Description

P0.<0..7> D GND Input or Output Digital I/O Channels 0 through 7—You can

individually configure each signal as an input or output. P0.6 and P0.7 can also control the up/down signal of Counters 0 and 1, respectively.

PFI <0..7>/P1.<0..7> PFI <8..15>/P2.<0..7>

+5 V D GND Output +5 Power Source—These pins provide +5 V power. For

D GND Input or Output Programmable Function Interface or Digital I/O

Channels 0 through 7 and Channels 8 through 15—Each of these terminals can be individually

configured as a PFI terminal or a digital I/O terminal.

As an input, each PFI terminal can be used to supply an external source for AI, AO, DI, and DO timing signals or counter/timer inputs.

As a PFI output, you can route many different internal AI, AO, DI, or DO timing signals to each PFI terminal. You also can route the counter/timer outputs to each PFI terminal.

As a Port 1 or Port 2 digital I/O signal, you can individually configure each signal as an input or output.

more information, refer to the +5 V Power Source section.

NI 6154 I/O Connector Signal Descriptions

(NI 6154 Only) Table 3-2 describes the signals found on the NI 6154 I/O

connector. For more information about these signals, refer to the NI 6154 Specifications.

Table 3-2. NI 6154 I/O Connector Signal Descriptions

I/O Connector Pin Reference Direction Signal Description

AI <0..3> + AI <0..3> – Input Analog Input Channels 0 through 3 (+)—These pins are

AI <0..3> –

AO <0..3> + AO <0.. 3> – Output Analog Output Channels 0 through 3 (+)—These pins

AO <0..3> – — Output Analog Output Channels 0 through 3 (–)—The

NI 6124/6154 User Manual 3-2 ni.com

—

Input Analog Input Channels 0 through 3 (–)—The reference

routed to the (+) terminal of the respective channel amplifier.

pins for the corresponding AI <0..3> + pin.

supply the voltage output of Analog Output channels 0 through 3.

reference pins for the corresponding AO <0..3> + pin.

Chapter 3 I/O Connector

Table 3-2. NI 6154 I/O Connector Signal Descriptions (Continued)

I/O Connector Pin Reference Direction Signal Description

PFI <0..5>/P0.<0..5> D GND Input Programmable Function Interface or Static Digital

Input Channels 0 to 5—Each of these terminals can be

individually configured as a PFI terminal or a digital input terminal.

As an input, each PFI terminal can be used to supply an external source for AI or AO timing signals or counter/timer inputs.

Note: PFI <0..5>/P0.<0..5> are isolated from earth ground and chassis ground.

PFI <6..9>/P1.<0..3> D GND Output Programmable Function Interface or Static Digital

Output Channels 6 to 9—Each of these terminals can be individually configured as a PFI terminal or a digital output terminal.

As a PFI output, you can route many different internal AI or AO timing signals to each PFI terminal. You also can route the counter/timer outputs to each PFI terminal.

Note: PFI <6..9>/P1.<0..3> are isolated from earth ground and chassis ground.

D GND — — Digital Ground—D GND supplies the reference

for input PFI <0..5>/P0.<0..5> and output PFI <6..9>/ P1.<0..3>.

Note: D GND is isolated from earth ground and chassis ground.

NC — — No Connect—Do not connect signals to these terminals.

+5 V Power Source

(NI 6124 Only) The +5 V pins on the I/O connector supply +5 V power. You

can use these pins, referenced to D GND, to power external circuitry.

Power rating (most devices): +4.65 to +5.25 VDC at 1 A.

To find your device’s power rating, refer to the specifications document for your device.

Caution Never connect these +5 V power pins to analog or digital ground or to any other

voltage source on the S Series device or any other device. Doing so can damage the device and the computer. NI is not liable for damage resulting from such a connection.

Analog Input

Figure 4-1 shows the analog input circuitry of each channel of the non-isolated S Series (NI 6124) device.

AI+

AI–

Mux

Instrumentation

Amplifier

Filter

ADC

AI FIFO

AI Data

AI+

AI–

Mux

CAL

Figure 4-1. Non-Isolated S Series Analog Input Block Diagram

Figure 4-2 shows the analog input circuitry of each channel of the isolated S Series (NI 6154) device.

Instrumentation

Amplifier

CAL

Filter

Figure 4-2. Isolated S Series Analog Input Block Diagram

Analog Trigger

ADC

AI Timing Signals

Isolation

Barrier

Digital

Isolators

AI FIFO

AI Timing Signals

AI Data

Chapter 4 Analog Input

On S Series devices, each channel uses its own instrumentation amplifier, FIFO, multiplexer (mux), and A/D converter (ADC) to achieve simultaneous data acquisition. The main blocks featured in the S Series analog input circuitry are as follows:

• Mux—By default, the mux is set to route AI signals to the analog front end. When you calibrate your device, the state of the mux switches. You can manually switch the state of the mux to measure AI GND.

• Instrumentation Amplifier—The instrumentation amplifier can amplify or attenuate an AI signal to ensure that you get the maximum resolution of the ADC. Some S Series devices provide programmable instrumentation amplifiers that allow you to select the input range.

• Analog Trigger— circuitry of S Series devices, refer to the Analog Input Triggering section.

• Filter—The filter on these S Series devices minimizes high frequency noise and some attenuating signals by 3 dB at 2 MHz.

• ADC—The analog-to-digital converter (ADC) digitizes the AI signal by converting the analog voltage into a digital number.

• AI Timing Signals—For information about the analog input timing signals available on S Series devices, refer to the Analog Input Timing

Signals section.

• Isolation Barrier and Digital Isolators— isolators across the isolation barrier provide a ground break between the isolated analog front end and the chassis ground. For more information about isolation and digital isolators, refer to the NI 6154

Isolation and Digital Isolators section of Appendix A, Device-Specific Information.

• AI FIFO—A large first-in-first-out (FIFO) buffer, located inside the FPGA, holds data during A/D conversions to ensure that no data is lost. S Series devices can handle multiple A/D conversion operations with DMA, interrupts, or programmed I/O.

(NI 6124 Only) For information about the trigger

(NI 6154 Only) The digital

Analog Input Terminal Configuration

S Series devices support only differential (DIFF) input mode. The channels on S Series devices are true differential inputs, meaning both positive and negative inputs can carry signals of interest. For more information about DIFF input, refer to the Connecting Analog Input Signals section, which contains diagrams showing the signal paths for DIFF input mode.

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Caution Exceeding the differential and common-mode input ranges distorts the input

signals. Exceeding the maximum input voltage rating can damage the device and the computer. NI is not liable for any damage resulting from such signal connections. The maximum input voltage ratings can be found in the specifications document for each S Series device.

Input Polarity and Range

Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy. On some S Series devices, you can individually program the input range of each AI channel.

The input range affects the resolution of the S Series device for an AI channel. Resolution refers to the magnitude of one ADC code. For example, a 16-bit ADC converts analog inputs into one of 65,536 (=2 codes, meaning one of 65,536 possible digital values. These values are spread fairly evenly across the input range. So, for an input range of –5 V to 5 V, the code width of a 16-bit ADC is:

5 V 5 V–()–

-------------------------------- 153 μV=

Chapter 4 Analog Input

)

S Series devices support bipolar input ranges. A bipolar input range means that the input voltage range is between –V

and V

ref

The instrumentation amplifier applies a different gain setting to the AI signal depending on the input range. Gain refers to the factor by which the instrumentation amplifier multiplies (amplifies) the input signal before sending it to the ADC.

On S Series devices with programmable input ranges, choose an input range that matches the expected input range of your signal. A large input range can accommodate a large signal variation, but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution, but may result in the input signal going out of range. For more information about programming these settings, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

Chapter 4 Analog Input

Working Voltage Range

On most S Series devices, the PGIA operates normally by amplifying signals of interest while rejecting common-mode signals under the following three conditions:

• The common-mode voltage (V AI <0..x> GND from AI <0..x> –, must be less than ±10 V. This V is a constant for all range selections.

• The signal voltage (V from AI <0..x> –, must be less than or equal to the range selection of the given channel. If V clips and information are lost.

• The total working voltage of the positive input, which is equivalent to (V

+ Vs), or subtracting AI <0..x> GND from AI <0..x> +, must be

less than ±11 V.

If any of these conditions are exceeded, the input voltage is clamped until the fault condition is removed.

Note All inputs are protected at up to ±35 V.

), which is equivalent to subtracting

), which is equivalent to subtracting AI <0..x>+

is greater than the range selected, the signal

(NI 6154 Only) The isolation features of the NI 6154 improve the working

voltage range in your applications. Refer to the NI 6154 Specifications for more information.

AI Data Acquisition Methods

When performing analog input measurements, there are several different data acquisition methods available. You can either perform software-timed or hardware-timed acquisitions:

• Software-Timed Acquisitions—With a software-timed acquisition, software controls the rate of the acquisition. Software sends a separate command to the hardware to initiate each ADC conversion. In NI-DAQmx, software-timed acquisitions are referred to as having On Demand timing. Software-timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single point of data.

• Hardware-Timed Acquisitions—With hardware-timed acquisitions, a digital hardware signal controls the rate of the acquisition. This signal can be generated internally on your device or provided externally.

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Chapter 4 Analog Input

Hardware-timed acquisitions have several advantages over software-timed acquisitions:

– The time between samples can be much shorter.

– The timing between samples can be deterministic.

– Hardware-timed acquisitions can use hardware triggering. For

more information, refer to Chapter 11, Triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in the computer memory where acquired samples are stored.

– Buffered—In a buffered acquisition, data is moved from the DAQ

device’s onboard FIFO memory to a PC buffer using DMA or interrupts before it is transferred to ADE memory. Buffered acquisitions typically allow for much faster transfer rates than non-buffered acquisitions because data is moved in large blocks, rather than one point at a time. For more information about DMA and interrupts, refer to the Data Transfer Methods section of Chapter 10, Bus Interface.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode acquisition refers to the acquisitions of a specific, predetermined number of data samples. After the specified number of samples has been collected into the buffer, the acquisition stops. If you use a reference trigger, you must use finite sample mode. Refer to the AI Reference Trigger Signal section for more information.

Continuous acquisition refers to the acquisition of an unspecified number of samples. Instead of acquiring a set number of data samples and stopping, a continuous acquisition continues until you stop the operation. A continuous acquisition is also referred to as double-buffered or circular-buffered acquisition.

If data cannot be transferred across the bus fast enough, the data in the FIFO will be overwritten and an error will be generated. With continuous operations, if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer, the buffer could reach an overflow condition, causing an error to be generated.

– Non-Buffered—In non-buffered acquisitions, data is read directly

from the FIFO on the device. Typically, hardware-timed non-buffered operations are used to read single samples with known time increments between them and small latency.

Chapter 4 Analog Input

Analog Input Triggering

Analog input supports two different triggering actions: start and reference. An analog or digital hardware trigger can initiate these actions. All S Series devices support digital triggering, and some also support analog triggering. To find your device’s triggering options, refer to the specifications document for your device.

The AI Start Trigger Signal and AI Reference Trigger Signal sections contain information about the analog input trigger signals.

Refer to Chapter 11, Triggering, for more information about triggers.

Connecting Analog Input Signals

Table 4-1 summarizes the recommended input configuration for different types of signal sources for S Series devices.

Table 4-1. S Series Analog Input Signal Configuration

Floating Signal Sources

(Not Connected to Earth Ground)

Ground-Referenced Signal Sources

Examples:

• Ungrounded thermocouples

• Signal conditioning with isolated

Example:

• Plug-in instruments with non-isolated outputs

outputs

Input

NI 6124 Non-Isolated Differential (DIFF)

• Battery devices

–

AI 0+

AI 0–

AI GND

–

AI 0+

AI 0–

–

AI GND

NI 6154 Isolated Differential

AI+

A I–

–

(DIFF)

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Isolation

Barrier

–

AI+

AI–

–

Isolation

Barrier

–

Refer to the Analog Input Terminal Configuration section for descriptions of the input modes.

Types of Signal Sources

When configuring the input channels and making signal connections, first determine whether the signal sources are floating or ground-referenced:

• Floating Signal Sources—A floating signal source is not connected in

any way to the building ground system, and instead has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolators, and isolation amplifiers. An instrument or device that has an isolated output is a floating signal source. You must connect the ground reference of a floating signal to the AI ground of the device to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats outside the common-mode input range.

• Ground-Referenced Signal Sources—A ground-referenced signal

source is connected in some way to the building system ground and is, therefore, already connected to a common ground point with respect to the device, assuming that the computer is plugged into the same power system as the source. Non-isolated outputs of instruments and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV, but the difference can be much higher if power distribution circuits are improperly connected. If a grounded signal source is incorrectly measured, this difference can appear as measurement error. Follow the connection instructions for grounded signal sources to eliminate this ground potential difference from the measured signal.

Isolated devices have isolated front ends that are isolated from ground-reference signal sources and are not connected to building system grounds. Isolated devices require the user to provide a ground-reference terminal to which its input signals are referenced.

Chapter 4 Analog Input

Differential Connections for Ground-Referenced Signal Sources

Figure 4-6 shows how to connect a ground-referenced signal source to a channel on a non-isolated S Series device.

Chapter 4 Analog Input

Ground-

Referenced

Signal

Source

CommonMode Noise and Ground

Potential

Non-Isolated S Series Device

AI 0+

–

AI 0–

AI 0 GND

Instrumentation

–

Amplifier

–

Measured

Voltage

Gro

und-

Referenced

Signal

Source

Common-

Mode Noise

and Ground

Potential

I/O Connector

–

AI 0 Connections Shown

Figure 4-3. Differential Connection for Ground-Referenced Signals

on Non-Isolated Devices

Figure 4-4 shows how to connect a ground-referenced signal source to a channel on an isolated S Series device.

Isolated S Series Device

AI 0+

AI 0–

AI 0 Connections Shown

Instrumentation

–

Amplifier

Measured

Voltage

–

Isolation

Barrier

Digital

Isolators

Figure 4-4. Differential Connection for Ground-Referenced Signals

on Isolated Devices

NI 6124/6154 User Manual 4-8 ni.com

Chapter 4 Analog Input

With these types of connections, the instrumentation amplifier rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the device ground, shown as V

in these

figures.

Common-Mode Signal Rejection Considerations

The instrumentation amplifier can reject any voltage caused by ground potential differences between the signal source and the device. In addition, the instrumentation amplifier can reject common-mode noise pickup in the leads connecting the signal sources to the device. The instrumentation amplifier can reject common-mode signals as long as V+

and V–in (input

signals) are both within the working voltage range of the device.

Differential Connections for Non-Referenced or Floating Signal Sources

Figure 4-5 shows how to connect a floating signal source to a channel on a non-isolated S Series device.

Non-Isolated S Series Device

AI 0+

Floating

Signal

Source

–

Current

Return

Paths

Bias

Resistor

I/O Connector

AI 0–

Bias

AI 0 GND

AI 0 Connections Shown

Instrumentation

–

Amplifier

–

Measured

Voltage

Figure 4-5. Differential Connection for Non-Referenced Signals on

Non-Isolated Devices

Chapter 4 Analog Input

Figure 4-5 shows a bias resistor connected between AI 0 – and the floating signal source ground. This resistor provides a return path for the bias current. A value of 10 kΩ to 100 kΩ is usually sufficient. If you do not use the resistor and the source is truly floating, the source is not likely to remain within the common-mode signal range of the instrumentation amplifier, so the instrumentation amplifier saturates, causing erroneous readings. You must reference the source to the respective channel ground.

Figure 4-6 shows how to connect a floating signal source to a channel on an isolated S Series device.

Floating

Signal

Source

Isolated S Series Device

AI 0+

–

AI 0–

AI 0 Connections Shown

Instrumentation

Amplifier

–

Measured

Voltage

Isolation

Barrier

Digital

Isolators

Figure 4-6. Differential Connection for Non-Referenced Signals on Isolated Devices

DC-Coupled

You can connect low source impedance and high source impedance DC-coupled sources:

• Low Source Impedance—You must reference the source to AI GND.

The easiest way to make this reference is to connect the positive side of the signal to the positive input of the instrumentation amplifier and connect the negative side of the signal to AI GND as well as to the negative input of the instrumentation amplifier, without using resistors. This connection works well for DC-coupled sources with low source impedance (less than 100 Ω).

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Chapter 4 Analog Input

• High Source Impedance—For larger source impedances, this

connection leaves the DIFF signal path significantly off balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground. Hence, this noise appears as a DIFF-mode signal instead of a common-mode signal, and the instrumentation amplifier does not reject it. In this case, instead of directly connecting the negative line to AI GND, connect the negative line to AI GND through a resistor that is about 100 times the equivalent source impedance. The resistor puts the signal path nearly in balance, so that about the same amount of noise couples onto both connections, yielding better rejection of electrostatically coupled noise. This configuration does not load down the source (other than the very high input impedance of the instrumentation amplifier).

You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND. This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination (sum) of the two resistors. If, for example, the source impedance is 2kΩ and each of the two resistors is 100 kΩ, the resistors load down the source with 200 kΩ and produce a –1% gain error.

AC-Coupled

Both inputs of the instrumentation amplifier require a DC path to ground in order for the instrumentation amplifier to work. If the source is AC-coupled (capacitively coupled), the instrumentation amplifier needs a resistor between the positive input and AI GND. If the source has low-impedance, choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current (typically 100 kΩ to 1 MΩ). In this case, connect the negative input directly to AI GND. If the source has high output impedance, balance the signal path as previously described using the same value resistor on both the positive and negative inputs; be aware that there is some gain error from loading down the source.

Field Wiring Considerations

Environmental noise can seriously affect the measurement accuracy of the S Series device if you do not take proper care when running signal wires between signal sources and the device. The following recommendations apply mainly to AI signal routing, although they also apply to signal routing in general.

Chapter 4 Analog Input

Minimize noise pickup and maximize measurement accuracy by taking the following precautions.

• Use differential AI connections to reject common-mode noise.

• Use individually shielded, twisted-pair wires to connect AI signals to the device. With this type of wire, the signals attached to the AI + and AI – inputs are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

• Route signals to the device carefully. Keep cabling away from noise sources. The most common noise source in a PCI DAQ system is the video monitor. Separate the monitor from the analog signals as far as possible.

• Separate the signal lines of the S Series device from high-current or high-voltage lines. These lines can induce currents in or voltages on the signal lines of the S Series device if they run in close parallel paths. To reduce the magnetic coupling between lines, separate them by a reasonable distance if they run in parallel, or run the lines at right angles to each other.

•Do not run signal lines through conduits that also contain power lines.

• Protect signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running them through special metal conduits.

Refer to the NI Developer Zone document, Field Wiring and Noise Considerations for Analog Signals, for more information.

Minimizing Drift in Differential Mode

If the readings from the DAQ device are random and drift rapidly, you should check the ground-reference connections. The signal can be referenced to a level that is considered floating with reference to the device ground reference. Even though you are in DIFF mode, you must still reference the signal to the same ground level as the device reference. There are various methods of achieving this reference while maintaining a high common-mode rejection ratio (CMRR). These methods are outlined in the

Connecting Analog Input Signals section.

AI GND is an AI common signal that routes directly to the ground connection point on the devices. You can use this signal if you need a general analog ground connection point to the device.

NI 6124/6154 User Manual 4-12 ni.com

Analog Input Timing Signals

An acquisition with posttrigger data allows you to view data that is acquired after a trigger event is received. A typical posttrigger DAQ sequence is shown in Figure 4-7. The sample counter is loaded with the specified number of posttrigger samples, in this example, five. The value decrements with each pulse on AI Sample Clock (ai/SampleClock), until the value reaches zero and all desired samples have been acquired.

AI Start Trigger

AI Sample Clock

Chapter 4 Analog Input

An acquisition with pretrigger data allows you to view data that is acquired before the trigger of interest, in addition to data acquired after the trigger. Figure 4-8 shows a typical pretrigger DAQ sequence. The AI Start Trigger signal (ai/StartTrigger) can be either a hardware or software signal. If AI Start Trigger is set up to be a software start trigger, an output pulse appears on the AI START TRIG line when the acquisition begins. When the AI Start Trigger pulse occurs, the sample counter is loaded with the number of pretrigger samples, in this example, four. The value decrements with each pulse on AI Sample Clock, until the value reaches zero. The sample counter is then loaded with the number of posttrigger samples, in this example, three.

AI Start Trigger

AI Reference Trigger

AI Sample Clock

Sample Counter

Don't Care

13042

Figure 4-7. Typical Posttriggered DAQ Sequence

01231 0222

Figure 4-8. Typical Pretriggered DAQ Sequence

Chapter 4 Analog Input

If an AI Reference Trigger (ai/ReferenceTrigger) pulse occurs before the specified number of pretrigger samples are acquired, the trigger pulse is ignored. Otherwise, when the AI Reference Trigger pulse occurs, the sample counter value decrements until the specified number of posttrigger samples have been acquired. For more information about start and reference triggers, refer to the Analog Input Triggering section.

In order to provide all of the timing functionality described throughout this section, the DAQ-STC2 provides an extremely powerful and flexible timing engine. For more information about all of the clock routing and timing options that the analog input timing engine provides, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

S Series devices feature the following analog input timing signals:

• AI Sample Clock Signal

• AI Sample Clock Timebase Signal

• AI Convert Clock Signal

• AI Convert Clock Timebase Signal

• AI Hold Complete Event Signal

• AI Start Trigger Signal

• AI Reference Trigger Signal

AI Sample Clock Signal

Use the AI Sample Clock (ai/SampleClock) signal to initiate a set of measurements. Your S Series device samples the AI signals of every channel in the task once for every AI Sample Clock.

You can specify an internal or external source for AI Sample Clock. You also can specify whether the measurement sample begins on the rising edge or falling edge of AI Sample Clock.

Using an Internal Source

One of the following internal signals can drive AI Sample Clock:

• Counter n Internal Output

• AI Sample Clock Timebase (divided down)

• A pulse initiated by host software

A programmable internal counter divides down the sample clock timebase.

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Chapter 4 Analog Input

Several other internal signals can be routed to AI Sample Clock through RTS I. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

Using an External Source

Use one of the following external signals as the source of AI Sample Clock:

• PFI <0..15>

•RTSI <0..7>

•PXI_STAR

• Analog Comparison Event (an analog trigger)

Routing AI Sample Clock Signal to an Output Terminal

You can route AI Sample Clock out to any PFI <0..15> or RTSI <0..7> terminal. This pulse is always active high.

You can specify the output to have one of two behaviors. With the pulse behavior, your DAQ device briefly pulses the PFI terminal once for every occurrence of AI Sample Clock.

With level behavior, your DAQ device drives the PFI terminal high during the entire sample.

All PFI terminals are configured as inputs by default.

Other Timing Requirements

A counter on your device internally generates AI Sample Clock unless you select some external source. AI Start Trigger starts this counter and either software or hardware can stop it once a finite acquisition completes. When using an internally generated AI Sample Clock, you also can specify a configurable delay from AI Start Trigger to the first AI Sample Clock pulse. By default, this delay is set to two ticks of the AI Sample Clock Timebase signal.

Chapter 4 Analog Input

Figure 4-9 shows the relationship of AI Sample Clock to AI Start Trigger.

AI Sample Clock Timebase

Figure 4-9. AI Sample Clock and AI Start Trigger

AI Sample Clock Timebase Signal

You can route any of the following signals to be the AI Sample Clock Timebase (ai/SampleClockTimebase) signal:

• 20 MHz Timebase

• 100 kHz Timebase

•PXI_CLK10

•RTSI <0..7>

• PFI <0..15>

•PXI_STAR

• Analog Comparison Event (an analog trigger)

AI Start Trigger

AI Sample Clock

Delay

From

Start

Trigger

AI Sample Clock Timebase is not available as an output on the I/O connector. AI Sample Clock Timebase is divided down to provide one of the possible sources for AI Sample Clock. You can configure the polarity selection for AI Sample Clock Timebase as either rising or falling edge.

AI Convert Clock Signal

Use the AI Convert Clock (ai/ConvertClock) signal to initiate a single A/D conversion on every channel.

You can specify either an internal or external signal as the source of AI Convert Clock. You also can specify whether the measurement sample begins on the rising edge or falling edge of AI Convert Clock.

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Chapter 4 Analog Input

Using an Internal Source

One of the following internal signals can drive AI Convert Clock:

• AI Convert Clock Timebase (divided down)

• Counter n Internal Output

A programmable internal counter divides down the AI Convert Clock Timebase to generate AI Convert Clock. The counter is started by AI Sample Clock and continues to count down to zero, produces an AI Convert Clock, reloads itself, and repeats the process until the sample is finished. It then reloads itself in preparation for the next AI Sample Clock pulse.

Using an External Source

Use one of the following external signals as the source of AI Convert Clock:

• PFI <0..15>

•RTSI <0..7>

•PXI_STAR

• Analog Comparison Event (an analog trigger)

Routing AI Convert Clock Signal to an Output Terminal

You can route AI Convert Clock (as an active low signal) out to any PFI <0..15> or RTSI <0..7> terminal.

All PFI terminals are configured as inputs by default.

AI Convert Clock Timebase Signal

The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is divided down to provide on of the possible sources for AI Convert Clock. Use one of the following signals as the source of AI Convert Clock Timebase:

• AI Sample Clock Timebase

• 20 MHz Timebase

AI Convert Clock Timebase is not available as an output on the I/O connector.

Chapter 4 Analog Input

AI Hold Complete Event Signal

The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates a pulse after each A/D conversion begins. You can route ai/HoldCompleteEvent out to any PFI <0..15> or RTSI <0..7> terminal.

The polarity of ai/HoldCompleteEvent is software-selectable, but is typically configured so that a low-to-high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed.

AI Start Trigger Signal

Use the AI Start Trigger (ai/StartTrigger) signal to begin a measurement acquisition. A measurement acquisition consists of one or more samples. If you do not use triggers, begin a measurement with a software command. Once the acquisition begins, configure the acquisition to stop:

• When a certain number of points are sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a posttriggered acquisition.

Using a Digital Source

To use AI Start Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• PFI <0..15>

•RTSI <0..7>

• Counter n Internal Output

•PXI_STAR

The source also can be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

You also can specify whether the measurement acquisition begins on the rising edge or falling edge of AI Start Trigger.

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Using an Analog Source

When you use an analog trigger source, the acquisition begins on the first rising edge of the Analog Comparison Event signal.

Routing AI Start Trigger to an Output Terminal

You can route AI Start Trigger out to any PFI <0..15> or RTSI <0..7> terminal. The output is an active high pulse. All PFI terminals are configured as inputs by default.

The device also uses AI Start Trigger to initiate pretriggered DAQ operations. In most pretriggered applications, a software trigger generates AI Start Trigger. Refer to the AI Reference Trigger Signal section for a complete description of the use of AI Start Trigger and AI Reference Trigger in a pretriggered DAQ operation.

AI Reference Trigger Signal

Use AI Reference Trigger (ai/ReferenceTrigger) signal to stop a measurement acquisition. To use a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples that occur before the reference trigger). The number of posttrigger samples (samples that occur after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

Chapter 4 Analog Input

Once the acquisition begins, the DAQ device writes samples to the buffer. After the DAQ device captures the specified number of pretrigger samples, the DAQ device begins to look for the reference trigger condition. If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples, the DAQ device ignores the condition.

If the buffer becomes full, the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample. This data can be accessed (with some limitations) before the DAQ device discards it. Refer to the KnowledgeBase document, Can a Pretriggered Acquisition be Continuous?, for more information. To access this KnowledgeBase, go to

ni.com/info and enter the info code rdcanq.

Chapter 4 Analog Input

When the reference trigger occurs, the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired. Figure 4-10 shows the final buffer.

Reference Trigger

Pretrigger Samples

lete Buffer

Com

Figure 4-10. Reference Trigger Final Buffer

Using a Digital Source

To use AI Reference Trigger with a digital source, specify a source and an edge. The source can be any of the following signals:

• PFI <0..15>

•RTSI <0..7>

•PXI_STAR

The source also can be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

You also can specify whether the measurement acquisition stops on the rising edge or falling edge of AI Reference Trigger.

Using an Analog Source

When you use an analog trigger source, the acquisition stops on the first rising edge of the Analog Comparison Event signal.

Routing AI Reference Trigger Signal to an Output Terminal

You can route AI Reference Trigger out to any PFI <0..15> or RTSI <0..7> terminal.

All PFI terminals are configured as inputs by default.

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Chapter 4 Analog Input

Getting Started with AI Applications in Software

You can use the S Series device in the following analog input applications:

• Simultaneous sampling

• Single-point analog input

• Finite analog input

• Continuous analog input

You can perform these applications through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start and reference pause triggers.

Note For more information about programming analog input applications and triggers in

software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

Analog Output

Figure 5-1 shows the analog output circuitry of a non-isolated S Series (NI 6124) device.

DAC0

DAC1

Isolation

Barrier

Digital

Isolators

AO FIFO

AO Data

AO Sample Cloc

AO Data

AO 0

AO 1

Figure 5-1. Non-Isolated S Series Device Analog Output Block Diagram

Figure 5-2 shows the analog output circuitry of an isolated S Series (NI 6154) device.

AO+

AO Sample Cloc

Figure 5-2. Isolated S Series Device Analog Output Block Diagram

Chapter 5 Analog Output

The main blocks featured in the S Series analog output circuitry are as follows:

• AO FIFO—The AO FIFO enables analog output waveform generation. It is a first-in-first-out (FIFO) memory buffer between the computer and the DACs that allows you to download all the points of a waveform to your board without host computer interaction.

• AO Sample Clock—The DAC reads a sample from the FIFO with every cycle of the AO Sample Clock signal and generates the AO voltage. For more information, refer to the AO Sample Clock Signal section.

Isolation and Digital Isolators section of Appendix A, Device-Specific Information.

• DAC—Digital-to-analog converters (DACs) convert digital codes to analog voltages.

Minimizing Glitches on the Output Signal

(NI 6154 Only) The digital

When you use a DAC to generate a waveform, you may observe glitches on the output signal. These glitches are normal; when a DAC switches from one voltage to another, it produces glitches due to released charges. The largest glitches occur when the most significant bit (MSB) of the DAC code switches. You can build a lowpass deglitching filter to remove some of these glitches, depending on the frequency and nature of the output signal. Visit

ni.com/support for more information about minimizing glitches.

AO Data Generation Methods

When performing an analog output operation, there are several different data generation methods available. You can either perform software-timed or hardware-timed generations:

• Software-Timed Generations—With a software-timed generation, software controls the rate at which data is generated. Software sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx, software-timed generations are referred to as On Demand timing. Software-timed generations are also referred to as immediate or static operations. They are typically used for writing a single value out, such as a constant DC voltage.

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Chapter 5 Analog Output

• Hardware-Timed Generations—With a hardware-timed generation,

a digital hardware signal controls the rate of the generation. This signal can be generated internally on your device or provided externally.

Hardware-timed generations have several advantages over software-timed generations:

– The time between samples can be much shorter.

– The timing between samples can be deterministic.

– Hardware-timed generations can use hardware triggering. For

more information, refer to Chapter 11, Triggering.

Hardware-timed operations can be buffered or non-buffered. A buffer is a temporary storage in computer memory for acquired or to-be-generated samples.

– Buffered—In a buffered generation, data is moved from a PC

buffer to the DAQ device’s onboard FIFO using DMA or interrupts before it is written to the DACs one sample at a time. Buffered generations typically allow for much faster transfer rates than non-buffered generations because data is moved in large blocks, rather than one point at a time. For more information about DMA and interrupts, refer to the Data Transfer Methods section of Chapter 10, Bus Interface.

One property of buffered I/O operations is the sample mode. The sample mode can be either finite or continuous.

Finite sample mode generation refers to the generation of a specific, predetermined number of data samples. When the specified number of samples has been written out, the generation stops.

Continuous generation refers to the generation of an unspecified number of samples. Instead of generating a set number of data samples and stopping, a continuous generation continues until you stop the operation. There are several different methods of continuous generation that control what data is written. These methods are regeneration, FIFO regeneration and non-regeneration modes.

Regeneration is the repetition of the data that is already in the buffer. Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out. New data can be written to the PC buffer at any time without disrupting the output.

Chapter 5 Analog Output

With FIFO regeneration, the entire buffer is downloaded to the FIFO and regenerated from there. After the data is downloaded, new data cannot be written to the FIFO. To use FIFO regeneration, the entire buffer must fit within the FIFO size. The advantage of using FIFO regeneration is that it does not require communication with the main host memory after the operation is started, thereby preventing any problems that may occur due to excessive bus traffic.

With non-regeneration, old data will not be repeated. New data must be continually written to the buffer. If the program does not write new data to the buffer at a fast enough rate to keep up with the generation, the buffer will underflow and cause an error.

– Non-Buffered—In hardware-timed non-buffered generations,

data is written directly to the FIFO on the device. Typically, hardware-timed non-buffered operations are used to write single samples with known time increments between them and good latency.

Analog Output Triggering

Analog output supports two different triggering actions: start and pause. An analog or digital hardware trigger can initiate these actions. All S Series devices support digital triggering, and some also support analog triggering. To find your device’s triggering options, refer to the specifications document for your device.

The AO Start Trigger Signal and AO Pause Trigger Signal sections contain information about the analog output trigger signals.

Refer to Chapter 11, Triggering, for more information about triggers.

Connecting Analog Output Signals

The AO signals are AO 0, AO 1, and AO GND. AO 0 is the voltage output signal for AO channel 0. AO 1 is the voltage output signal for AO channel 1. AO GND is the ground reference for the AO channels.

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Chapter 5 Analog Output

Figure 5-3 shows how AO 0 and AO 1 are wired on a non-isolated S Series device.

AO 0

Load

VOUT 0

VOUT 1

–

AO GND

AO 1

Non-Isolated S Series Device

Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices

Channel 0

Channel 1

Analog Output Channels

Figure 5-4 shows how AO 0 is wired on an isolated S Series device.

Isolation

AO+

DAC

VOUT

Analog Output Channel

–

AO–

Isolated S Series Device

Figure 5-4. Analog Output Connections for Isolated S Series Devices

Barrier

Digital

Isolators

Chapter 5 Analog Output

Waveform Generation Timing Signals

There is one AO Sample Clock that causes all AO channels to update simultaneously. Figure 5-5 summarizes the timing and routing options provided by the analog output timing engine.

RTSI 7

20 MHz

Timebase

Master

Timebase

Onboard

Clock

÷200

S Series devices feature the following waveform generation timing signals:

• AO Sample Clock Signal

• AO Sample Clock Timebase Signal

• AO Start Trigger Signal

• AO Pause Trigger Signal

AO Sample Clock Signal

You can use the AO Sample Clock (ao/SampleClock) signal to initiate AO samples. Each sample updates the outputs of all of the DACs.

The source of the AO Sample Clock signal can be internal or external. You can specify whether the DAC update begins on the rising edge or falling edge of the AO Sample Clock signal.

Onboard

Clock

Divisor

Ctr1InternalOutput

PFI 0–9,

RTSI 0–6

PFI 0–9,

RTSI 0–6

ao/SampleClock

Timebase

Figure 5-5. Analog Output Engine Routing Options

ao/SampleClock

Using an Internal Source

By default, AO Sample Clock is created internally by dividing down the AO Sample Clock Timebase signal.

Several other internal signals can be routed to the sample clock. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

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Chapter 5 Analog Output

Using an External Source

You can use a signal connected to any PFI or RTSI <0..6> pin as the source of AO Sample Clock. Figure 5-6 shows the timing requirements of the AO Sample Clock source.

Rising-Edge

Polarity

Falling-Edge

Polarity

= 10 ns minimum

Figure 5-6. AO Sample Clock Timing Requirements

Routing AO Sample Clock Signal to an Output Terminal

You can route ao/SampleClock (as an active low signal) out to any PFI <0..15> or RTSI <0..7> terminal.

Other Timing Requirements

A counter on your device internally generates AO Sample Clock unless you select some external source. The AO Start Trigger signal starts this counter. It is stopped automatically by hardware after a finite acquisition completes or manually through software. When using an internally generated AO Sample Clock in NI-DAQmx, you can also specify a configurable delay from the AO Start Trigger to the first AO Sample Clock pulse. By default, this delay is two ticks of the AO Sample Clock Timebase signal.

Chapter 5 Analog Output

Figure 5-7 shows the relationship of the AO Sample Clock signal to the AO Start Trigger signal.

AO Sample Clock Timebase

AO Start Trigger

AO Sample Clock

Figure 5-7. AO Sample Clock and AO Start Trigger

AO Sample Clock Timebase Signal

You can select any PFI or RTSI pin as well as many other internal signals as the AO Sample Clock Timebase (ao/SampleClockTimebase) signal. This signal is not available as an output on the I/O connector. AO Sample Clock Timebase is divided down to provide the Onboard Clock source for the AO Sample Clock. You specify whether the samples begin on the rising or falling edge of AO Sample Clock Timebase.

Delay

From Start

Trigger

You might use the AO Sample Clock Timebase signal if you want to use an external sample clock signal, but need to divide the signal down. If you want to use an external sample clock signal, but do not need to divide the signal, then you should use the AO Sample Clock signal rather than the AO Sample Clock Timebase. If you do not specify an external sample clock timebase, NI-DAQmx uses the Onboard Clock.

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Figure 5-8 shows the timing requirements for the AO Sample Clock Timebase signal.

The maximum allowed frequency is 20 MHz, with a minimum pulse width of 10 ns high or low. There is no minimum frequency.

Unless you select an external source, either the 20MHzTimebase or 100kHzTimebase generates the AO Sample Clock Timebase signal.

AO Start Trigger Signal

You can use the AO Start Trigger signal (ao/StartTrigger) to initiate a waveform generation. If you do not use triggers, you begin a generation with a software command.

Chapter 5 Analog Output

tp = 50 ns minimum

= 23 ns minimum

Figure 5-8. AO Sample Clock Timebase Timing Requirements

Using a Digital Source

To use AO Start Trigger, specify a source and an edge. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

Chapter 5 Analog Output

Figure 5-9 shows the timing requirements of the AO Start Trigger digital source.

Rising-Edge

Polarity

Falling-Edge

Polarity

tw = 10 ns minimum

Figure 5-9. AO Start Trigger Timing Requirements

Using an Analog Source

When you use an analog trigger source, the waveform generation begins on the first rising edge of the Analog Comparison Event signal. For more information, refer to the Triggering with an Analog Source section of Chapter 11, Triggering.

Routing AO Start Trigger Signal to an Output Terminal

You can route ao/StartTrigger out to any PFI <0..15> or RTSI <0..7> terminal.

The output is an active high pulse.

PFI terminals are configured as inputs by default.

AO Pause Trigger Signal

You can use the AO Pause Trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence. That is, when AO Pause Trigger is active, no samples occur.

The AO Pause Trigger does not stop a sample that is in progress. The pause does not take effect until the beginning of the next sample. This signal is not available as an output.

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Chapter 5 Analog Output

Using a Digital Source

To use ao/Pause Trigger, specify a source and a polarity. The source can be an external signal connected to any PFI or RTSI <0..6> pin. The source can also be one of several other internal signals on your DAQ device. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

Also, specify whether the samples are paused when AO Pause Trigger is at a logic high or low level.

Using an Analog Source

When you use an analog trigger source, the samples are paused when the Analog Comparison Event signal is at a high level. For more information, refer to the Triggering with an Analog Source section of Chapter 11,

Triggering.

Getting Started with AO Applications in Software

You can use the S Series device in the following analog output applications:

• Single-point generation

• Finite generation

• Continuous generation

• Waveform generation

You can perform these generations through DMA, interrupt, or programmed I/O data transfer mechanisms. Some of the applications also use start triggers and pause triggers.

Note For more information about programming analog output applications and triggers in

software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

Digital I/O

Refer to one of the following sections, depending on your device:

• Digital I/O for Non-Isolated Devices—NI 6124 devices have eight lines of bidirectional DIO lines on Port 0, and 16 PFI signals that can function as static DIO lines.

• Digital I/O for Isolated Devices—NI 6154 devices have six bank-isolated digital inputs and four bank-isolated digital outputs.

Digital I/O for Non-Isolated Devices

(NI 6124 Only) NI 6124 devices contain eight lines of bidirectional DIO lines

on Port 0. In addition, The NI 6124 has 16 PFI lines that can function as static DIO lines.

These S Series devices support the following DIO features on Port 0:

• Eight lines of DIO

• Direction and function of each terminal individually controllable

• Static digital input and output

• High-speed digital waveform generation

• High-speed digital waveform acquisition

• DI change detection trigger/interrupt

Chapter 6 Digital I/O

DO Sample Clock

Figure 6-1 shows the circuitry of one DIO line. Each DIO line is similar. The following sections provide information about the various parts of the DIO circuit.

DO Waveform

Generation FIFO

Static DO

Buffer

DO.x Direction Control

I/O Protection

P0.x

Static DI

DI Waveform

Measurement

FIFO

DI Sample Clock

DI Change

Detection

Figure 6-1. Non-Isolated S Series Digital I/O Circuitry

The DIO terminals are named P0.<0..7> on the device I/O connector.

The voltage input and output levels and the current drive levels of the DIO lines are listed in the specifications of your device.

Static DIO for Non-Isolated Devices

(NI 6124 Only) Each DIO line can be used as a static DI or DO line. You can

use static DIO lines to monitor or control digital signals. Each DIO can be individually configured as a digital input (DI) or digital output (DO).

All samples of static DI lines and updates of DO lines are software-timed.

Weak Pull-Down

P0.6 and P0.7 on these devices also can control the up/down input of general-purpose counters 0 and 1, respectively. However, it is recommended that you use PFI signals to control the up/down input of the counters. The up/down control signals, Counter 0 Up_Down and Counter 1 Up_Down, are input-only and do not affect the operation of the DIO lines.

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Digital Waveform Triggering for Non-Isolated Devices

(NI 6124 Only) NI 6124 devices do not have an independent DI or DO Start

Trigger for digital waveform acquisition or generation. To trigger a DI or DO operation, first select a signal to be the source of DI Sample Clock or DO Sample Clock. Then, generate a trigger that initiates pulses on the source signal. The method for generating this trigger depends on which signal is the source of DI Sample Clock or DO Sample Clock.

For example, consider the case where you are using AI Sample Clock as the source of DI Sample Clock. To initiate pulses on AI Sample Clock (and therefore on DI Sample Clock), you use AI Start Trigger to trigger the start of an AI operation. The AI Start Trigger causes the non-isolated DAQ-STC2 S Series device to begin generating AI Sample clock pulses, which in turn generates DI Sample clock pulses, as shown in Figure 6-2.

Chapter 6 Digital I/O

(AI Start Trigger)

PFI 1

AI Sample Clock

DI Sample Clock

AI Start Trigger initiates AI Sample Clock and DI Sample Clock.

Figure 6-2. Digital Waveform Triggering

Similarly, if you are using AO Sample Clock as the source of DI Sample Clock, then AO Start Trigger initiates both AO and DI operations.

If you are using a Counter output as the source of DI Sample Clock, the counter’s start trigger, enables the counter which drives DI Sample Clock.

If you are using an external signal (such as PFI x) as the source for DI Sample Clock or DO Sample Clock, you must trigger that external signal.

Digital Waveform Acquisition for Non-Isolated Devices

(NI 6124 Only) You can acquire digital waveforms on the Port 0 DIO lines.

The DI waveform acquisition FIFO stores the digital samples. S Series devices have a DMA controller dedicated to moving data from the DI waveform acquisition FIFO to system memory. The DAQ device samples the DIO lines on each rising or falling edge of a clock signal, DI Sample Clock.

Chapter 6 Digital I/O

You can configure each DIO line to be an output, a static input, or a digital waveform acquisition input.

DI Sample Clock Signal

(NI 6124 Only) Use the DI Sample Clock (di/SampleClock) signal to sample

the P0.<0..7> terminals and store the result in the DI waveform acquisition FIFO. These S Series devices do not have the ability to divide down a timebase to produce an internal DI Sample Clock for digital waveform acquisition. Therefore, you must route an external signal or one of many internal signals from another subsystem to be the DI Sample Clock. For example, you can correlate digital and analog samples in time by sharing your AI Sample Clock or AO Sample Clock as the source of your DI Sample Clock. To sample a digital signal independent of an AI, AO, or DO operation, you can configure a counter to generate the desired DI Sample Clock or use an external signal as the source of the clock.

If the DAQ device receives a DI Sample Clock when the FIFO is full, it reports an overflow error to the host software.

Using an Internal Source

To use DI Sample Clock with an internal source, specify the signal source and the polarity of the signal. The source can be any of the following signals:

• AI Sample Clock (ai/SampleClock)

• AI Convert Clock (ai/ConvertClock)

• AO Sample Clock (ao/SampleClock)

• Counter n Internal Output

•Frequency Output

• DI Change Detection Output

Several other internal signals can be routed to DI Sample Clock through RTS I. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

Using an External Source

You can route any of the following signals as DI Sample Clock:

• PFI <0..15>

•RTSI <0..7>

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•PXI_STAR

• Analog Comparison Event (an analog trigger)

You can sample data on the rising or falling edge of DI Sample Clock.

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock out to any PFI terminal. The PFI circuitry inverts the polarity of DI Sample Clock before driving the PFI terminal.

Digital Waveform Generation for Non-Isolated Devices

(NI 6124 Only) You can generate digital waveforms on the Port 0 DIO lines.

The DO waveform generation FIFO stores the digital samples. These S Series devices have a DMA controller dedicated to moving data from the system memory to the DO waveform generation FIFO. The DAQ device moves samples from the FIFO to the DIO terminals on each rising or falling edge of a clock signal, DO Sample Clock. You can configure each DIO signal to be an input, a static output, or a digital waveform generation output.

The FIFO supports a retransmit mode. In the retransmit mode, after all the samples in the FIFO have been clocked out, the FIFO begins outputting all of the samples again in the same order. For example, if the FIFO contains five samples, the pattern generated consists of sample #1, #2, #3, #4, #5, #1, #2, #3, #4, #5, #1, and so on.

Chapter 6 Digital I/O

DO Sample Clock Signal

(NI 6124 Only) Use the DO Sample Clock (do/SampleClock) signal to update

the DO terminals with the next sample from the DO waveform generation FIFO. These S Series devices do not have the ability to divide down a timebase to produce an internal DO Sample Clock for digital waveform generation. Therefore, you must route an external signal or one of many internal signals from another subsystem to be the DO Sample Clock. For example, you can correlate digital and analog samples in time by sharing your AI Sample Clock or AO Sample Clock as the source of your DO Sample Clock. To generate digital data independent of an AI, AO, or DI operation, you can configure a counter to generate the desired DO Sample Clock or use an external signal as the source of the clock.

If the DAQ device receives a DO Sample Clock when the FIFO is empty, the DAQ device reports an underflow error to the host software.

Chapter 6 Digital I/O

Using an Internal Source

To use DO Sample Clock with an internal source, specify the signal source and the polarity of the signal. The source can be any of the following signals:

• AI Sample Clock (ai/SampleClock)

• AI Convert Clock (ai/ConvertClock)

• AO Sample Clock (ao/SampleClock)

• Counter n Internal Output

•Frequency Output

• DI Change Detection Output

Several other internal signals can be routed to DO Sample Clock through RTS I. Refer to Device Routing in MAX in the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information.

Using an External Source

You can route any of the following signals as DO Sample Clock:

• PFI <0..15>

•RTSI <0..7>

•PXI_STAR

• Analog Comparison Event (an analog trigger)

You can generate samples on the rising or falling edge of DO Sample Clock.

You must ensure that the time between two active edges of DO Sample Clock is not too short. If the time is too short, the DO waveform generation FIFO is not able to read the next sample fast enough. The DAQ device reports an overrun error to the host software.

Routing DO Sample Clock to an Output Terminal

You can route DO Sample Clock out to any PFI terminal. The PFI circuitry inverts the polarity of DO Sample Clock before driving the PFI terminal.

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I/O Protection for Non-Isolated Devices

(NI 6124 Only) Each DIO and PFI signal is protected against overvoltage,

undervoltage, and overcurrent conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines:

• If you configure a PFI or DIO line as an output, do not connect it to any external signal source, ground, or power supply.

• If you configure a PFI or DIO line as an output, understand the current requirements of the load connected to these signals. Do not exceed the specified current output limits of the DAQ device. NI has several signal conditioning solutions for digital applications requiring high current drive.

• If you configure a PFI or DIO line as an input, do not drive the line with voltages outside of its normal operating range. The PFI or DIO lines have a smaller operating range than the AI signals.

• Treat the DAQ device as you would treat any static sensitive device. Always properly ground yourself and the equipment when handling the DAQ device or connecting to it.

Programmable Power-Up States for Non-Isolated Devices

(NI 6124 Only) At system startup and reset, the hardware sets all PFI and DIO

lines to high-impedance inputs by default. The DAQ device does not drive the signal high or low. Each line has a weak pull-down resistor connected to it, as described in the specifications document for your device.

Chapter 6 Digital I/O

NI-DAQmx supports programmable power-up states for PFI and DIO lines. Software can program any value at power up to the P0, P1, or P2 lines. The PFI and DIO lines can be set as:

• A high-impedance input with a weak pull-down resistor (default)

• An output driving a 0

• An output driving a 1

Refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later for more information about setting power-up states in NI-DAQmx or MAX.

Note When using your S Series device to control an SCXI chassis, DIO lines 0, 1, 2, and

4 are used as communication lines and must be left to power-up in the default high-impedance state to avoid potential damage to these signals.

Chapter 6 Digital I/O

DI Change Detection for Non-Isolated Devices

(NI 6124 Only) You can configure the DAQ device to detect changes in the

DIO signals. Figure 6-3 shows a block diagram of the DIO change detection circuitry.

P0.0

P0.7

Synch

Enable

Change Detection Event

Enable

Figure 6-3. DI Change Detection

You can enable the DIO change detection circuitry to detect rising edges, falling edges, or either edge individually on each DIO line. The DAQ devices synchronize each DI signal to 80MHzTimebase, and then sends the signal to the change detectors. The circuitry ORs the output of all enabled change detectors from every DI signal. The result of this OR is the Change Detection Event signal.

The Change Detection Event signal can do the following:

• Drive any RTSI <0..7>, PFI <0..15>, or PXI_STAR signal

• Drive the DO Sample Clock or DI Sample Clock

• Generate an interrupt

NI 6124/6154 User Manual 6-8 ni.com

The Change Detection Event signal also can be used to detect changes on digital output events.

DI Change Detection Applications for Non-Isolated Devices

(NI 6124 Only) The DIO change detection circuitry can interrupt a user

program when one of several DIO signals changes state.

You also can use the output of the DIO change detection circuitry to trigger a DI or counter acquisition on the logical OR of several digital signals. To trigger on a single digital signal, refer to the Triggering with a Digital

Source section of Chapter 11, Triggering. By routing the Change Detection

Event signal to a counter, you also can capture the relative time between samples.

You also can use the Change Detection Event signal to trigger DO or counter generations.

Connecting Digital I/O Signals on Non-Isolated Devices

(NI 6124 Only) The DIO signals, P0.<0..7>, PFI <0..7>/P1.<0..7>, and

PFI <8..15>/P2.<0..7> are referenced to D GND. You can individually program each line as an input or output. Figure 6-4 shows PFI <0..3>/P1.<0..3> configured for digital input and PFI <4..7>/P1.<4..7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states, such as the state of the switch shown in the figure. Digital output applications include sending TTL signals and driving external devices, such as the LED shown in the figure.

Chapter 6 Digital I/O

+5 V

LED

PFI <4..7>/

P1.<4..7>

PFI <0..3>/

P1.<0..3>

Caution

TTL Signal

+5 V

Switch

D GND

I/O Connector

Non-Isolated S Series Device

Figure 6-4. Digital I/O Connections

Exceeding the maximum input voltage ratings, which are listed in the specifications document for each non-isolated DAQ-STC2 S Series device, can damage the DAQ device and the computer. NI is not liable for any damage resulting from such signal connections.

Getting Started with DIO Applications in Software on Non-Isolated Devices

(NI 6124 Only) You can use non-isolated S Series devices in the following

digital I/O applications:

• Static digital input

• Static digital output

• Digital waveform generation

• Digital waveform acquisition

• DI change detection

Note For more information about programming digital I/O applications and triggers in

software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

NI 6124/6154 User Manual 6-10 ni.com

Digital I/O for Isolated Devices

(NI 6154 Only) S Series isolated devices contain ten lines of unidirectional

DIO signals. The digital I/O port is comprised of six digital inputs and four digital outputs, all bank-isolated. Each digital line has the functionality of a PFI line. Input PFI lines can be used to input trigger signals to the different function modules of the DAQ-STC2 ASIC. The PFI pins also can be used as static digital inputs when not used to input triggers. Output PFI lines can export internal signals generated in any internal function module, as well as signals present in the RTSI bus. The PFI pins also can be used as static digital outputs when not used as trigger lines.

The voltage input and output levels and the current drive levels of the DIO lines are listed in the NI 6154 Specifications.

Figure 6-5 shows the circuitry of one bank-isolated DIO line.

PFI/

Static DI

PFI/

Static DO

Chapter 6 Digital I/O

Isolation

Barrier

Digital

Isolators

I/O Connector

Figure 6-5. Isolated S Series Devices Digital I/O Block Diagram

Static DIO for Isolated Devices

(NI 6154 Only) Isolated devices have unidirectional digital lines that are

either static digital inputs (DI) or static digital outputs (DO). You can use DI and DO lines to monitor or control digital signals. All samples of static DI lines and updates of DO lines are software-timed. All DO lines are controlled by the same output enable. When a digital output line is enabled, all other digital output lines will also be enabled and driven to a default value of 0.

You can select the up/down control input of general-purpose counters 0 and 1 from any of the six digital input lines.

Chapter 6 Digital I/O

I/O Protection for Isolated Devices

(NI 6154 Only) Each DIO and PFI signal is protected against over-voltage,

under-voltage, and over-current conditions as well as ESD events. However, you should avoid these fault conditions by following these guidelines:

• Do not connect any DO line to any external signal source, ground signal, or power supply.

• Understand the current requirements of the load connected to DO signals. Do not exceed the specified current output limits of the DAQ device. NI has several signal conditioning solutions for digital applications requiring high-current drive.

• Do not drive any DI line with voltages outside of its normal operating range. The PFI or DIO lines have a smaller operating range than the AI signals.

• Treat the DAQ device as you would treat any static sensitive device. Always properly ground yourself and the equipment when handling the DAQ device or connecting to it.

Connecting Digital I/O Signals on Isolated Devices

(NI 6154 Only) The DIO signals, PFI <0..5>/P0.<0..5> and

PFI <6..9>/P1.<0..3>, are referenced to D GND. PFI <0..5>/P0.<0..5> are inputs and PFI <6..9>/P1.<0..3> are outputs. Figure 6-6 shows digital inputs PFI <0..5>/P0.<0..5> and digital outputs PFI <6..9>/P1.<0..3>. Digital input applications include receiving TTL signals and sensing external device states, such as the state of the switch shown in the figure. Digital output applications include sending TTL signals and driving external devices, such as the LED shown in Figure 6-6.

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+5 V

LED

Chapter 6 Digital I/O

+5 V

Isolation

Barrier

PFI <6..9>/P1.<0..3>

Digital

Isolators

TTL Signal

PFI <0..5>/P0.<0..5>

Switch

D GND

I/O Connector

Isolated S Series Device

Figure 6-6. Isolated S Series Device Digital I/O Signal Connections

Caution

Exceeding the maximum input voltage ratings, which are listed in the NI 6154

Specifications, can damage the DAQ device and the computer. NI is not liable for any

damage resulting from such signal connections.

Getting Started with DIO Applications in Software on Isolated Devices

(NI 6154 Only) You can use isolated S Series devices in the following digital

I/O applications:

• Static digital input

• Static digital output

Note For more information about programming digital I/O applications and triggers in

software, refer to the NI-DAQmx Help or the LabVIEW Help in version 8.0 or later.

Counters

S Series devices have two general-purpose 32-bit counter/timers and one frequency generator, as shown in Figure 7-1. The general-purpose counter/timers can be used for many measurement and pulse generation applications.

Input Selection Muxes

Counter 0

Counter 0 Source (Counter 0 Timebase)

Counter 0 Gate

Counter 0 Aux

Counter 0 HW Arm

Counter 0 A

Counter 0 B (Counter 0 Up_Down)

Counter 0 Z

Counter 1 Source (Counter 1 Timebase)

Counter 1 Gate

Counter 1 Aux

Counter 1 HW Arm

Counter 1 A

Counter 1 B (Counter 1 Up_Down)

Counter 1 Z

Counter 0 Internal Output

Counter 1

Counter 0 Internal Output

Counter 0 TC

Input Selection Muxes

Frequency Output Timebase Freq Out

Frequency Generator

Figure 7-1. S Series Counters

Chapter 7 Counters

The counters have seven input signals, although in most applications only a few inputs are used.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Counter Input Applications

Counting Edges

In edge counting applications, the counter counts edges on its Source after the counter is armed. You can configure the counter to count rising or falling edges on its Source input. You also can control the direction of counting (up or down).

The counter values can be read on demand or with a sample clock.

Single Point (On-Demand) Edge Counting

With single point (on-demand) edge counting, the counter counts the number of edges on the Source input after the counter is armed. On-demand refers to the fact that software can read the counter contents at any time without disturbing the counting process. Figure 7-2 shows an example of single point edge counting.

Counter Armed

SOURCE

Counter Value1 0 5 4 3 2

Figure 7-2. Single Point (On-Demand) Edge Counting

You also can use a pause trigger to pause (or gate) the counter. When the pause trigger is active, the counter ignores edges on its Source input. When the pause trigger is inactive, the counter counts edges normally.

You can route the pause trigger to the Gate input of the counter. You can configure the counter to pause counting when the pause trigger is high or when it is low. Figure 7-3 shows an example of on-demand edge counting with a pause trigger.

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Pause Trigger

(Pause When Low)

SOURCE

Chapter 7 Counters

Counter Armed

Counter Value

1 0 0 5 4 3 2

Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger

Buffered (Sample Clock) Edge Counting

With buffered edge counting (edge counting using a sample clock), the counter counts the number of edges on the Source input after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory.

The count values returned are the cumulative counts since the counter armed event. That is, the sample clock does not reset the counter.

You can route the counter sample clock to the Gate input of the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 7-4 shows an example of buffered edge counting. Notice that counting begins when the counter is armed, which occurs before the first active edge on Gate.

Counter Armed

(Sample on Rising Edge)

Sample Clock

SOURCE

Counter Value

Buffer

1 0 7 6 3 4 5 2

Figure 7-4. Buffered (Sample Clock) Edge Counting

Chapter 7 Counters

Controlling the Direction of Counting

In edge counting applications, the counter can count up or down. You can configure the counter to do the following:

• Always count up

• Always count down

• Count up when the Counter n B input is high; count down when it is low

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Pulse-Width Measurement

In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal. You can configure the counter to measure the width of high pulses or low pulses on the Gate signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges on the Source signal while the pulse on the Gate signal is active.

You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter.

A pulse-width measurement will be accurate even if the counter is armed while a pulse train is in progress. If a counter is armed while the pulse is in the active state, it will wait for the next transition to the active state to begin the measurement.

Single Pulse-Width Measurement

With single pulse-width measurement, the counter counts the number of edges on the Source input while the Gate input remains active. When the Gate input goes inactive, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then reads the stored count.

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Chapter 7 Counters

Figure 7-5 shows an example of a single pulse-width measurement.

GATE

SOURCE

1 0

Counter Value

GATE

SOURCE

Counter Value

Buffer

HW Save Register

Figure 7-5. Single Pulse-Width Measurement

Buffered Pulse-Width Measurement

Buffered pulse-width measurement is similar to single pulse-width measurement, but buffered pulse-width measurement takes measurements over multiple pulses.

The counter counts the number of edges on the Source input while the Gate input remains active. On each trailing edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

Figure 7-6 shows an example of a buffered pulse-width measurement.

10 3

212

Figure 7-6. Buffered Pulse-Width Measurement

Chapter 7 Counters

condition is not met, consider using duplicate count prevention, described in the Duplicate Count Prevention section.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Period Measurement

In period measurements, the counter measures a period on its Gate input signal after the counter is armed. You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal.

You can route an internal or external periodic clock signal (with a known period) to the Source input of the counter. The counter counts the number of rising (or falling) edges occurring on the Source input between the two active edges of the Gate signal.

You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Single Period Measurement

With single period measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between two active edges of the Gate input. On the second active edge of the Gate input, the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs. Software then reads the stored count.

Figure 7-7 shows an example of a single period measurement.

GATE

SOURCE

1 0 3 5 4

Counter Value

HW Save Re

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ister

Figure 7-7. Single Period Measurement

GATE

SOURCE

Chapter 7 Counters

Buffered Period Measurement

Buffered period measurement is similar to single period measurement, but buffered period measurement measures multiple periods.

The counter counts the number of rising (or falling) edges on the Source input between each pair of active edges on the Gate input. At the end of each period on the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins when it is armed. The arm usually occurs in the middle of a period of the Gate input. So the first value stored in the hardware save register does not reflect a full period of the Gate input. In most applications, this first point should be discarded.

Figure 7-8 shows an example of a buffered period measurement.

Counter Armed

Counter Value

Buffer

1 1 2 3

(Discard) (Discard) (Discard)

Figure 7-8. Buffered Period Measurement

3 2

3 1 1

3 3

Note that if you are using an external signal as the Source, at least one Source pulse should occur between each active edge of the Gate signal. This condition ensures that correct values are returned by the counter. If this condition is not met, consider using duplicate count prevention, described in the Duplicate Count Prevention section.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Semi-Period Measurement

In semi-period measurements, the counter measures a semi-period on its Gate input signal after the counter is armed. A semi-period is the time between any two consecutive edges on the Gate input.

Chapter 7 Counters

You can calculate the semi-period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter.

Single Semi-Period Measurement

Single semi-period measurement is equivalent to single pulse-width measurement.

Buffered Semi-Period Measurement

In buffered semi-period measurement, on each edge of the Gate signal, the counter stores the count in a hardware save register. A DMA controller transfers the stored values to host memory.

The counter begins counting when it is armed. The arm usually occurs between edges on the Gate input. So the first value stored in the hardware save register does not reflect a full semi-period of the Gate input. In most applications, this first point should be discarded.

Figure 7-9 shows an example of a buffered semi-period measurement.

ounter Armed

GATE

SOURCE

1 1

Counter Value

Buffer

1 3

1 2 1 0 2

Figure 7-9. Buffered Semi-Period Measurement

NI 6124/6154 User Manual 7-8 ni.com

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Frequency Measurement

You can use the counters to measure frequency in several different ways. You can choose one of the following methods depending on your application:

• Method 1: Measure Low Frequency with One Counter—In this

method, you measure one period of your signal using a known timebase. This method is good for low frequency signals.

You can route the signal to measure (F1) to the Gate of a counter. You can route a known timebase (Ft) to the Source of the counter. The known timebase can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase.

You can configure the counter to measure one period of the gate signal. The frequency of F1 is the inverse of the period. Figure 7-10 illustrates this method.

Chapter 7 Counters

Interval Measured

Gate

Source

Single Period

Measurement

123 … N

Period of F1 =

Frequency of F1 =

Figure 7-10. Method 1

…

• Method 1b: Measure Low Frequency with One Counter (Averaged)—In this method, you measure several periods of your

signal using a known timebase. This method is good for low to medium frequency signals.

Chapter 7 Counters

You can configure the counter to make K + 1 buffered period measurements. Recall that the first period measurement in the buffer should be discarded.

Average the remaining K period measurements to determine the average period of F1. The frequency of F1 is the inverse of the average period. Figure 7-11 illustrates this method.

ntervals Measured

… T

Gate

Source

Buffered Period

Measurement

2 ...N

1... ...N2 … 1... ...N

Average Period of F1 =

Frequency of F1 =

+ N2 + …N

K × Ft

+ N2 + …N

Figure 7-11. Method 1b

• Method 2: Measure High Frequency with Two Counters—In this

method, you measure one pulse of a known width using your signal and derive the frequency of your signal from the result. This method is good for high frequency signals.

In this method, you route a pulse of known duration (T) to the Gate of a counter. You can generate the pulse using a second counter. You also can generate the pulse externally and connect it to a PFI or RTSI terminal. You only need to use one counter if you generate the pulse externally.

Route the signal to measure (F1) to the Source of the counter. Configure the counter for a single pulse-width measurement. If you measure the width of pulse T to be N periods of F1, the frequency of F1 is N/T.

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Chapter 7 Counters

Figure 7-12 illustrates this method. Another option would be to measure the width of a known period instead of a known pulse.

Width of Pulse (T)

Pulse

Gate

1 2 … N

Source

Pulse-Width

Measurement

Width of

Pulse

Frequency of F1 =

T =

Figure 7-12. Method 2

• Method 3: Measure Large Range of Frequencies Using Two Counters—By using two counters, you can accurately measure

a signal that might be high or low frequency. This technique is called reciprocal frequency measurement. In this method, you generate a long pulse using the signal to measure. You then measure the long pulse with a known timebase. The S Series device can measure this long pulse more accurately than the faster input signal.

Chapter 7 Counters

_1_

You can route the signal to measure to the Source input of Counter 0, as shown in Figure 7-13. Assume this signal to measure has frequency F1. Configure Counter 0 to generate a single pulse that is the width of N periods of the source input signal.

Signal to

Measure (F1)

Signal of Known

Frequency (F2)

CTR_0_SOURCE

(Signal to Measure)

CTR_0_OUT

(CTR_1_GATE)

CTR

SOURCE

SOURCE OUT

COUNTER 0

SOURCE

COUNTER 1

GATE

0 1 2 3 … N

Interval

to Measure

OUT

Figure 7-13. Method 3

Then route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a signal of known frequency (F2) to the Counter 1 Source input. F2 can be 80MHzTimebase. For signals that might be slower than 0.02 Hz, use a slower known timebase. Configure Counter 1 to perform a single pulse-width measurement. Suppose the result is that the pulse width is J periods of the F2 clock.

From Counter 0, the length of the pulse is N/F1. From Counter 1, the length of the same pulse is J/F2. Therefore, the frequency of F1 is given by F1 = F2 * (N/J).

Choosing a Method for Measuring Frequency

The best method to measure frequency depends on several factors including the expected frequency of the signal to measure, the desired accuracy, how many counters are available, and how long the measurement can take.

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Chapter 7 Counters

• Method 1 uses only one counter. It is a good method for many applications. However, the accuracy of the measurement decreases as the frequency increases.

Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase. This frequency corresponds to 1600 cycles of the 80 MHz Timebase. Your measurement may return 1600 ± 1 cycles depending on the phase of the signal with respect to the timebase. As your frequency becomes larger, this error of ±1 cycle becomes more significant; Table 7-1 illustrates this point.

Table 7-1. Frequency Measurement Method 1

Ta sk Equation Example 1 Example 2

Actual Frequency to Measure F1 50 kHz 5MHz

Timebase Frequency Ft 80 MHz 80 MHz

Actual Number of Timebase

Ft/F1 1600 16

Periods

Worst Case Measured Number

(Ft/F1) – 1 1599 15

of Timebase Periods

Measured Frequency Ft F1/(Ft – F1) 50.031 kHz 5.33 MHz

Error [Ft F1/(Ft – F1)] – F1 31 Hz 333 kHz

Error % [Ft/(Ft – F1)] – 1 0.06% 6.67%

• Method 1b (measuring K periods of F1) improves the accuracy of the measurement. A disadvantage of Method 1b is that you have to take K + 1 measurements. These measurements take more time and consume some of the available PCI or PXI bandwidth.

• Method 2 is accurate for high frequency signals. However, the accuracy decreases as the frequency of the signal to measure decreases. At very low frequencies, Method 2 may be too inaccurate for your application. Another disadvantage of Method 2 is that it requires two counters (if you cannot provide an external signal of known width). An advantage of Method 2 is that the measurement completes in a known amount of time.

• Method 3 measures high and low frequency signals accurately. However, it requires two counters.

Chapter 7 Counters

Table 7-2 summarizes some of the differences in methods of measuring frequency.

Table 7-2. Frequency Measurement Method Comparison

Number of

Counters

Method

1 1 1 Poor Good

1b 1 Many Fair Good

2 1 or 2 1 Good Poor

3 2 1 Good Good

Used

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Position Measurement

You can use the counters to perform position measurements with quadrature encoders or two-pulse encoders. You can measure angular position with X1, X2, and X4 angular encoders. Linear position can be measured with two-pulse encoders. You can choose to do either a single point (on-demand) position measurement or a buffered (sample clock) position measurement. You must arm a counter to begin position measurements.

Number of

Measurements

Returned

Measures High

Frequency

Signals

Accurately

Measures Low

Frequency

Signals

Accurately

Measurements Using Quadrature Encoders

The counters can perform measurements of quadrature encoders that use X1, X2, or X4 encoding. A quadrature encoder can have up to three channels—channels A, B, and Z.

• X1 Encoding—When channel A leads channel B in a quadrature

cycle, the counter increments. When channel B leads channel A in a quadrature cycle, the counter decrements. The amount of increments and decrements per cycle depends on the type of encoding—X1, X2, or X4.

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Chapter 7 Counters

Figure 7-14 shows a quadrature cycle and the resulting increments and decrements for X1 encoding. When channel A leads channel B, the increment occurs on the rising edge of channel A. When channel B leads channel A, the decrement occurs on the falling edge of channel A.

Ch A Ch B

Ch A

Ch B

Counter Value

Figure 7-14. X1 Encoding

• X2 Encoding—The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A, depending on which channel leads the other. Each cycle results in two increments or decrements, as shown in Figure 7-15.

Ch A Ch B

Counter Value

5 6 8

Figure 7-15. X2 Encoding

• X4 Encoding—Similarly, the counter increments or decrements on each edge of channels A and B for X4 encoding. Whether the counter increments or decrements depends on which channel leads the other. Each cycle results in four increments or decrements, as shown in Figure 7-16.

Counter Value 5 6 8 9 10 10 11 11 12 12 13 13 7

5 6 8 7 9

Figure 7-16. X4 Encoding

Channel Z Behavior

Some quadrature encoders have a third channel, channel Z, which is also referred to as the index channel. A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle. You can program this reload to occur in any one of the four phases in a quadrature cycle.

Chapter 7 Counters

Channel Z behavior—when it goes high and how long it stays high—differs with quadrature encoder designs. You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B. You must then ensure that channel Z is high during at least a portion of the phase you specify for reload. For instance, in Figure 7-17, channel Z is never high when channel A is high and channel B is low. Thus, the reload must occur in some other phase.

In Figure 7-17, the reload phase is when both channel A and channel B are low. The reload occurs when this phase is true and channel Z is high. Incrementing and decrementing takes priority over reloading. Thus, when the channel B goes low to enter the reload phase, the increment occurs first. The reload occurs within one maximum timebase period after the reload phase becomes true. After the reload occurs, the counter continues to count as before. The figure illustrates channel Z reload with X4 decoding.

Ch A Ch B

Ch Z

Max Timebase

Counter Value

5 6

Figure 7-17. Channel Z Reload with X4 Decoding

8 9 0 2 1 7 4 3

A = 0 B = 0 Z = 1

Measurements Using Two Pulse Encoders

The counter supports two pulse encoders that have two channels—channels A and B.

The counter increments on each rising edge of channel A. The counter decrements on each rising edge of channel B, as shown in Figure 7-18.

Ch A

Ch B

Counter Value2 3 5 4 3 4 4

Figure 7-18. Measurements Using Two Pulse Encoders

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Chapter 7 Counters

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Buffered (Sample Clock) Position Measurement

With buffered position measurement (position measurement using a sample clock), the counter increments based on the encoding used after the counter is armed. The value of the counter is sampled on each active edge of a sample clock. A DMA controller transfers the sampled values to host memory. The count values returned are the cumulative counts since the counter armed event; that is, the sample clock does not reset the counter. You can route the counter sample clock to the Gate input of the counter. You can configure the counter to sample on the rising or falling edge of the sample clock.

Figure 7-19 shows an example of a buffered edge X1 position measurement.

(Sample on Rising Edge)

Sample Clock

Ch A

Ch B

Buffer

Counter Armed

Figure 7-19. Buffered Position Measurement

Two-Signal Edge-Separation Measurement

Two-signal edge-separation measurement is similar to pulse-width measurement, except that there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting. You must arm a counter to begin a two edge separation measurement.

After the counter has been armed and an active edge occurs on the Aux input, the counter counts the number of rising (or falling) edges on the Source. The counter ignores additional edges on the Aux input.

4102 5Count

1 4

The counter stops counting upon receiving an active edge on the Gate input. The counter stores the count in a hardware save register.

Chapter 7 Counters

You can configure the rising or falling edge of the Aux input to be the active edge. You can configure the rising or falling edge of the Gate input to be the active edge.

Use this type of measurement to count events or measure the time that occurs between edges on two signals. This type of measurement is sometimes referred to as start/stop trigger measurement, second gate measurement, or A-to-B measurement.

Single Two-Signal Edge-Separation Measurement

With single two-signal edge-separation measurement, the counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register and ignores other edges on its inputs. Software then reads the stored count.

Figure 7-20 shows an example of a single two-signal edge-separation measurement.

Counter

Armed

Measured Interval

AUX

GATE

SOURCE

Counter Value

HW Save Register

Figure 7-20. Single Two-Signal Edge-Separation Measurement

0 0 0 0 1 2 3 4 5 6 7 8 8 8

Buffered Two-Signal Edge-Separation Measurement

Buffered and single two-signal edge-separation measurements are similar, but buffered measurement measures multiple intervals.

The counter counts the number of rising (or falling) edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores the count in a hardware save register. On the next active edge of the Gate signal, the counter begins another measurement. A DMA controller transfers the stored values to host memory.

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Figure 7-21 shows an example of a buffered two-signal edge-separation measurement.

AUX

GATE

SOURCE

Counter Value

Buffer

Figure 7-21. Buffered Two-Signal Edge-Separation Measurement

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Counter Output Applications

Simple Pulse Generation

Chapter 7 Counters

1 2 3 1 2 3 1 2 3

3 3

3 3 3

Single Pulse Generation

The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

Chapter 7 Counters

Figure 7-22 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

Counter Armed

SOURCE

OUT

Figure 7-22. Single Pulse Generation

Single Pulse Generation with Start Trigger

The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal. The pulse appears on the Counter n Internal Output signal of the counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of the pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

After the Start Trigger signal pulses once, the counter ignores the Gate input.

Figure 7-23 shows a generation of a pulse with a pulse delay of four and a pulse width of three (using the rising edge of Source).

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-23. Single Pulse Generation with Start Trigger

Retriggerable Single Pulse Generation

The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal. The pulses appear on the Counter n Internal Output signal of the counter.

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Chapter 7 Counters

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The delay and pulse width are measured in terms of a number of active edges of the Source input.

The counter ignores the Gate input while a pulse generation is in progress. After the pulse generation is finished, the counter waits for another Start Trigger signal to begin another pulse generation.

Figure 7-24 shows a generation of two pulses with a pulse delay of five and a pulse width of three (using the rising edge of Source).

GATE

(Start Trigger)

SOURCE

OUT

Figure 7-24. Retriggerable Single Pulse Generation

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Pulse Train Generation

Continuous Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle. The pulses appear on the Counter n Internal Output signal of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse train. The delay is measured in terms of a number of active edges of the Source input.

You specify the high and low pulse widths of the output signal. The pulse widths are also measured in terms of a number of active edges of the Source input. You also can specify the active edge of the Source input (rising or falling).

The counter can begin the pulse train generation as soon as the counter is armed, or in response to a hardware Start Trigger. You can route the Start Trigger to the Gate input of the counter.

Chapter 7 Counters

You also can use the Gate input of the counter as a Pause Trigger (if it is not used as a Start Trigger). The counter pauses pulse generation when the Pause Trigger is active.

Figure 7-25 shows a continuous pulse train generation (using the rising edge of Source).

SOURCE

OUT

Counter Armed

Figure 7-25. Continuous Pulse Train Generation

Continuous pulse train generation is sometimes called frequency division. If the high and low pulse widths of the output signal are M and N periods, then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divided by M + N.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Finite Pulse Train Generation

This function generates a train of pulses of predetermined duration. This counter operation requires both counters. The first counter (for this example, Counter 0) generates a pulse of desired width. The second counter, Counter 1, generates the pulse train, which is gated by the pulse of the first counter. The routing is done internally. Figure 7-26 shows an example finite pulse train timing diagram.

Counter 0

(Paired Counter)

Counter 1

Generation

Complete

Figure 7-26. Finite Pulse Train Timing Diagram

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Frequency Generation

You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit.

Using the Frequency Generator

The frequency generator can output a square wave at many different frequencies. The frequency generator is independent of the two general-purpose 32-bit counter/timer modules on S Series devices.

Figure 7-27 shows a block diagram of the frequency generator.

20 MHz Timebase

100 kHz Timebase

÷ 2

Chapter 7 Counters

Frequency

Output

Timebase

Frequency Generator

Divisor (1–16)

Figure 7-27. Frequency Generator Block Diagram

FREQ OUT

The frequency generator generates the Frequency Output signal. The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16. The Frequency Output Timebase can be either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase.

The duty cycle of Frequency Output is 50% if the divider is either 1 or an even number. For an odd divider, suppose the divider is set to D. In this case, Frequency Output is low for (D + 1)/2 cycles and high for (D – 1)/2 cycles of the Frequency Output Timebase.

Figure 7-28 shows the output waveform of the frequency generator when the divider is set to 5.

Frequency

Output

Timebase

FREQ OUT

(Divisor = 5)

Figure 7-28. Frequency Generator Output Waveform

Chapter 7 Counters

Frequency Output can be routed out to any PFI <0..15> or RTSI <0..7> terminal. All PFI terminals are set to high-impedance at startup. The FREQ OUT signal also can be routed to DO Sample Clock and DI Sample Clock.

In software, program the frequency generator as you would program one of the counters for pulse train generation.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Frequency Division

The counters can generate a signal with a frequency that is a fraction of an input signal. This function is equivalent to continuous pulse train generation. Refer to the Continuous Pulse Train Generation section for detailed information.

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Pulse Generation for ETS

In the equivalent time sampling (ETS) application, the counter produces a pulse on the output a specified delay after an active edge on Gate. After each active edge on Gate, the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount. Thus, the delay between the Gate and the pulse produced successively increases.

The increase in the delay value can be between 0 and 255. For instance, if you specify the increment to be 10, the delay between the active Gate edge and the pulse on the output will increase by 10 every time a new pulse is generated.

Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger. Furthermore, suppose you specify the delay increment to be 10. On the first trigger, your pulse delay will be 100, on the second it will be 110, on the third it will be 120; the process will repeat in this manner until the counter is disarmed. The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress.

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The waveform thus produced at the counter’s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist frequency of the system. Figure 7-29 shows an example of pulse generation for ETS; the delay from the trigger to the pulse increases after each subsequent Gate active edge.

GATE

OUT

For information about connecting counter signals, refer to the Default

Counter/Timer Pinouts section.

Counter Timing Signals

Chapter 7 Counters

D1 D2 = D1 + ΔD D3 = D1 + 2ΔD

Figure 7-29. Pulse Generation for ETS

S Series devices feature the following counter timing signals:

• Counter n Source Signal

• Counter n Gate Signal

• Counter n Aux Signal

• Counter n A Signal

• Counter n B Signal

• Counter n Z Signal

• Counter n Up_Down Signal

• Counter n HW Arm Signal

• Counter n Internal Output Signal

• Counter n TC Signal

• Frequency Output Signal

In this section, n refers to either Counter 0 or 1. For example, Counter n Source refers to two signals—Counter 0 Source (the source input to Counter 0) and Counter 1 Source (the source input to Counter 1).

Chapter 7 Counters

Counter n Source Signal

The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing. Table 7-3 lists how this terminal is used in various applications.

One Counter Time Measurements Counter Timebase

Two Counter Time Measurements Input Terminal

Non-Buffered Edge Counting Input Terminal

Routing a Signal to Counter n Source

Each counter has independent input selectors for the Counter n Source signal. Any of the following signals can be routed to the Counter n Source input:

•80MHz Timebase

•20MHz Timebase

• 100 kHz Timebase

•RTSI<0..7>

• PFI <0..15>

•PXI_CLK10

•PXI_STAR

• Analog Comparison Event

Table 7-3. Counter Applications and Counter n Source

Application Purpose of Source Terminal

Pulse Generation Counter Timebase

Buffered Edge Counting Input Terminal

Two-Edge Separation Counter Timebase

In addition, Counter 1 TC or Counter 1 Gate can be routed to Counter 0 Source. Counter 0 TC or Counter 0 Gate can be routed to Counter 1 Source.

Some of these options may not be available in some driver software.

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Routing Counter n Source to an Output Terminal

You can route Counter n Source out to any PFI <0..15> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup.

Counter n Gate Signal

The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter, and saving the counter contents.

Routing a Signal to Counter n Gate

Each counter has independent input selectors for the Counter n Gate signal. Any of the following signals can be routed to the Counter n Gate input:

•RTSI<0..7>

• PFI <0..15>

• AI Reference Trigger (ai/ReferenceTrigger)

• AI Start Trigger (ai/StartTrigger)

• AI Sample Clock (ai/SampleClock)

• AI Convert Clock (ai/ConvertClock)

• AO Sample Clock (ao/SampleClock)

• DI Sample Clock (di/SampleClock)

• DO Sample Clock (do/SampleClock)

•PXI_STAR

• Change Detection Event

• Analog Comparison Event

Chapter 7 Counters

In addition, Counter 1 Internal Output or Counter 1 Source can be routed to Counter 0 Gate. Counter 0 Internal Output or Counter 0 Source can be routed to Counter 1 Gate.

Some of these options may not be available in some driver software.

Routing Counter n Gate to an Output Terminal

You can route Counter n Gate out to any PFI <0..15> or RTSI <0..7> terminal. All PFIs are set to high-impedance at startup.

Chapter 7 Counters

Counter n Aux Signal

The Counter n Aux signal indicates the first edge in a two-signal edge-separation measurement.

Routing a Signal to Counter n Aux

Each counter has independent input selectors for the Counter n Aux signal. Any of the following signals can be routed to the Counter n Aux input:

•RTSI<0..7>

• PFI <0..15>

• AI Reference Trigger (ai/ReferenceTrigger)

• AI Start Trigger (ai/StartTrigger)

•PXI_STAR

• Analog Comparison Event

In addition, Counter 1 Internal Output, Counter 1 Gate, Counter 1 Source, or Counter 0 Gate can be routed to Counter 0 Aux. Counter 0 Internal Output, Counter 0 Gate, Counter 0 Source, or Counter 1 Gate can be routed to Counter 1 Aux.

Some of these options may not be available in some driver software.

Counter n A, Counter n B, and Counter n Z Signals

Counter n B can control the direction of counting in edge counting applications. Use the A, B, and Z inputs to each counter when measuring quadrature encoders or measuring two pulse encoders.

Routing Signals to A, B, and Z Counter Inputs

Each counter has independent input selectors for each of the A, B, and Z inputs. Any of the following signals can be routed to each input:

•RTSI<0..7>

• PFI <0..15>

•PXI_STAR

• Analog Comparison Event

Routing Counter n Z Signal to an Output Terminal

You can route Counter n Z out to RTSI <0..7>.

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National Instruments DAQ S User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NI 6124/6154 User Manual

Support

Worldwide Technical Support and Product Information

National Instruments Corporate Headquarters

Worldwide Offices

Important Information

Warranty

Copyright

Trademarks

Patents

WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS

Compliance

Contents

About This Manual

Conventions

Related Documentation

Installing NI-DAQmx

Installing Other Software

Installing the Hardware

Device Self-Calibration

Device Pinouts

Device Specifications

Figure 2-1. Typical DAQ System

DAQ Hardware

Figure 2-2. General NI 6124 Block Diagram

Figure 2-3. General NI 6154 Block Diagram

DAQ-STC2

Calibration Circuitry

Internal or Self-Calibration

External Calibration

Signal Conditioning

Sensors and Transducers

Programming Devices in Software

NI 6124 I/O Connector Signal Descriptions

Table 3-1. NI 6124 Device Signal Descriptions

NI 6154 I/O Connector Signal Descriptions

Table 3-2. NI 6154 I/O Connector Signal Descriptions

+5 V Power Source

Figure 4-1. Non-Isolated S Series Analog Input Block Diagram

Figure 4-2. Isolated S Series Analog Input Block Diagram

Analog Input Terminal Configuration

Input Polarity and Range

Working Voltage Range

AI Data Acquisition Methods

Analog Input Triggering

Connecting Analog Input Signals

Table 4-1. S Series Analog Input Signal Configuration

Types of Signal Sources

Differential Connections for Ground-Referenced Signal Sources

Common-Mode Signal Rejection Considerations

Differential Connections for Non-Referenced or Floating Signal Sources

Figure 4-6. Differential Connection for Non-Referenced Signals on Isolated Devices

DC-Coupled

AC-Coupled

Field Wiring Considerations

Minimizing Drift in Differential Mode

Analog Input Timing Signals

Figure 4-7. Typical Posttriggered DAQ Sequence

Figure 4-8. Typical Pretriggered DAQ Sequence

AI Sample Clock Signal

Using an Internal Source

Using an External Source

Routing AI Sample Clock Signal to an Output Terminal

Other Timing Requirements

Figure 4-9. AI Sample Clock and AI Start Trigger

AI Sample Clock Timebase Signal

AI Convert Clock Signal

Using an Internal Source

Using an External Source

Routing AI Convert Clock Signal to an Output Terminal

AI Convert Clock Timebase Signal

AI Hold Complete Event Signal

AI Start Trigger Signal

Using a Digital Source

Using an Analog Source

Routing AI Start Trigger to an Output Terminal