National Instruments cDAQ-9138, cDAQ-9139 User Manual

National Instruments cDAQ-9138 Manual

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NI cDAQTM-9138/9139

User Manual

NI CompactDAQ Eight-Slot Controller

NI cDAQ-9138/9139 User Manual

March 2016
371042D-01

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Contents

Chapter 1
Getting Started with the cDAQ Controller

Safety Guidelines.............................................................................................................. 1-2

Electromagnetic Compatibility Guidelines ...................................................................... 1-3

Hardware Symbol Definitions .......................................................................................... 1-3

Unpacking......................................................................................................................... 1-4

Installing the NI cDAQ-9138/9139 for Windows ............................................................ 1-5

Installing the NI cDAQ-9138/9139 for LabVIEW Real-Time......................................... 1-8

Troubleshooting Network Communication in NI cDAQ-9138/9139 for

LabVIEW Real-Time Controller ........................................................................... 1-12

Wiring Power to the cDAQ Controller............................................................................. 1-12

Mounting the cDAQ Controller........................................................................................ 1-14

Using the cDAQ Controller on a Desktop ................................................................ 1-16

Mounting the cDAQ Controller on a Panel .............................................................. 1-17

Mounting the cDAQ Controller on a DIN Rail ........................................................ 1-19

Mounting the cDAQ Controller on a Rack............................................................... 1-20

Removing Modules from the cDAQ Controller ............................................................... 1-21

cDAQ Controller Features................................................................................................ 1-21

Video (VGA) Port .................................................................................................... 1-21

USB Ports ................................................................................................................. 1-22

Ethernet Ports ........................................................................................................... 1-22

Ethernet LEDs .................................................................................................. 1-23

Ethernet Cabling ............................................................................................... 1-24

RS-232 Serial Port .................................................................................................... 1-25

RS-485/422 Serial Port............................................................................................. 1-25

MXI-Express Port..................................................................................................... 1-26

DIP Switches ............................................................................................................ 1-26

Power Connector ...................................................................................................... 1-29

RESET Button .......................................................................................................... 1-29

Power Button ............................................................................................................ 1-29

LEDs......................................................................................................................... 1-30

CMOS Battery and CMOS Reset Button ................................................................. 1-32

Resetting the System CMOS and BIOS Settings ............................................. 1-32

Chassis Grounding Screw......................................................................................... 1-33

CPU eXpansion Module (CXM) Connector ............................................................ 1-34

CFast SSD Module ................................................................................................... 1-34

Cables and Accessories .................................................................................................... 1-34

Using the cDAQ Controller .............................................................................................. 1-35

C Series Module ....................................................................................................... 1-35

Parallel versus Serial DIO Modules ................................................................. 1-36

cDAQ Module Interface ........................................................................................... 1-36

STC3......................................................................................................................... 1-36

Processor and Ports................................................................................................... 1-37

© National Instruments | v

Contents

Chapter 2
Analog Input

Analog Input Triggering Signals ...................................................................................... 2-1

Analog Input Timing Signals............................................................................................ 2-1

AI Sample Clock Signal ........................................................................................... 2-2

Routing the Sample Clock to an Output Terminal ........................................... 2-2

AI Sample Clock Timebase Signal ........................................................................... 2-2

AI Convert Clock Signal Behavior For Analog Input Modules ............................... 2-2

Scanned Modules.............................................................................................. 2-3

Simultaneous Sample-and-Hold Modules ........................................................ 2-3

Sigma-Delta Modules .......................................................................................2-3

Slow Sample Rate Modules.............................................................................. 2-4

AI Start Trigger Signal ............................................................................................. 2-4

Using a Digital Source ...................................................................................... 2-5

Using an Analog Source ................................................................................... 2-5

Routing AI Start Trigger to an Output Terminal .............................................. 2-5

AI Reference Trigger Signal..................................................................................... 2-5

Using a Digital Source ...................................................................................... 2-6

Using an Analog Source ................................................................................... 2-6

Routing the Reference Trigger Signal to an Output Terminal.......................... 2-6

AI Pause Trigger Signal............................................................................................ 2-7

Using a Digital Source ...................................................................................... 2-7

Using an Analog Source ................................................................................... 2-7

Getting Started with AI Applications in Software ............................................................ 2-7

Chapter 3
Analog Output

Analog Output Data Generation Methods ........................................................................3-1

Software-Timed Generations ....................................................................................3-1

Hardware-Timed Generations................................................................................... 3-2

Buffered Analog Output ................................................................................... 3-2

Analog Output Triggering Signals.................................................................................... 3-3

Analog Output Timing Signals ......................................................................................... 3-3

AO Sample Clock Signal ..........................................................................................3-3

Routing AO Sample Clock to an Output Terminal........................................... 3-4

AO Sample Clock Timebase Signal ......................................................................... 3-4

AO Start Trigger Signal ............................................................................................3-4

Using a Digital Source ...................................................................................... 3-4

Using an Analog Source ................................................................................... 3-4

Routing AO Start Trigger Signal to an Output Terminal ................................. 3-5

AO Pause Trigger Signal .......................................................................................... 3-5

Using a Digital Source ...................................................................................... 3-5

Using an Analog Source ................................................................................... 3-5

Minimizing Glitches on the Output Signal ....................................................................... 3-6

Getting Started with AO Applications in Software .......................................................... 3-6

vi | ni.com

NI cDAQ-9138/9139 User Manual

Chapter 4
Digital Input/Output and PFI

Digital Input/Output ......................................................................................................... 4-1

Serial DIO versus Parallel DIO Modules ................................................................. 4-1

Static DIO ................................................................................................................. 4-2

Digital Input.............................................................................................................. 4-2

Digital Input Triggering Signals....................................................................... 4-2

Digital Input Timing Signals ............................................................................ 4-2

Digital Input Filters .......................................................................................... 4-6

Getting Started with DI Applications in Software............................................ 4-7

Change Detection Event ........................................................................................... 4-7

Routing Change Detection Event to an Output Terminal................................. 4-7

Change Detection Acquisition.......................................................................... 4-7

Digital Output ........................................................................................................... 4-8

Digital Output Data Generation Methods......................................................... 4-8

Digital Output Triggering Signals .................................................................... 4-9

Digital Output Timing Signals ......................................................................... 4-10

Getting Started with DO Applications in Software .......................................... 4-13

Digital Input/Output Configuration for NI 9401 ...................................................... 4-13

PFI .................................................................................................................................... 4-13

PFI Filters ................................................................................................................. 4-13

Chapter 5
Counters

Counter Timing Engine .................................................................................................... 5-2

Counter Input Applications .............................................................................................. 5-3

Counting Edges......................................................................................................... 5-3

Single Point (On-Demand) Edge Counting ...................................................... 5-3

Buffered (Sample Clock) Edge Counting......................................................... 5-4

Controlling the Direction of Counting.............................................................. 5-4

Pulse-Width Measurement ....................................................................................... 5-5

Single Pulse-Width Measurement .................................................................... 5-5

Implicit Buffered Pulse-Width Measurement................................................... 5-6

Sample Clocked Buffered Pulse-Width Measurement ..................................... 5-6

Pulse Measurement................................................................................................... 5-7

Single Pulse Measurement................................................................................ 5-7

Implicit Buffered Pulse Measurement .............................................................. 5-7

Sample Clocked Buffered Pulse Measurement ................................................ 5-8

Semi-Period Measurement ....................................................................................... 5-8

Single Semi-Period Measurement .................................................................... 5-9

Implicit Buffered Semi-Period Measurement................................................... 5-9

Pulse versus Semi-Period Measurements ......................................................... 5-10

Frequency Measurement........................................................................................... 5-10

Low Frequency with One Counter ................................................................... 5-11

© National Instruments | vii

Contents

High Frequency with Two Counters................................................................. 5-12

Large Range of Frequencies with Two Counters .............................................5-13

Sample Clocked Buffered Frequency Measurement ........................................ 5-14

Choosing a Method for Measuring Frequency ................................................. 5-15

Which Method Is Best?..................................................................................... 5-16

Period Measurement ................................................................................................. 5-18

Position Measurement............................................................................................... 5-19

Measurements Using Quadrature Encoders...................................................... 5-19

Channel Z Behavior .................................................................................................. 5-20

Measurements Using Two Pulse Encoders....................................................... 5-21

Buffered (Sample Clock) Position Measurement ............................................. 5-21

Two-Signal Edge-Separation Measurement ............................................................. 5-22

Single Two-Signal Edge-Separation Measurement .......................................... 5-22

Implicit Buffered Two-Signal Edge-Separation Measurement ........................5-23

Sample Clocked Buffered Two-Signal Separation Measurement .................... 5-23

Counter Output Applications ............................................................................................ 5-24

Simple Pulse Generation........................................................................................... 5-24

Single Pulse Generation .................................................................................... 5-24

Single Pulse Generation with Start Trigger ...................................................... 5-25

Pulse Train Generation ............................................................................................. 5-25

Finite Pulse Train Generation ...........................................................................5-26

Retriggerable Pulse or Pulse Train Generation................................................. 5-26

Continuous Pulse Train Generation .................................................................. 5-27

Buffered Pulse Train Generation ...................................................................... 5-28

Finite Implicit Buffered Pulse Train Generation .............................................. 5-28

Continuous Buffered Implicit Pulse Train Generation ..................................... 5-29

Finite Buffered Sample Clocked Pulse Train Generation ................................ 5-29

Continuous Buffered Sample Clocked Pulse Train Generation ....................... 5-30

Frequency Generation............................................................................................... 5-31

Using the Frequency Generator ........................................................................5-31

Frequency Division................................................................................................... 5-32

Pulse Generation for ETS ......................................................................................... 5-32

Counter Timing Signals .................................................................................................... 5-33

Counter n Source Signal ........................................................................................... 5-33

Routing a Signal to Counter n Source .............................................................. 5-34

Routing Counter n Source to an Output Terminal ............................................5-34

Counter n Gate Signal............................................................................................... 5-34

Routing a Signal to Counter n Gate .................................................................. 5-34

Routing Counter n Gate to an Output Terminal ............................................... 5-35

Counter n Aux Signal ............................................................................................... 5-35

Routing a Signal to Counter n Aux...................................................................5-35

Counter n A, Counter n B, and Counter n Z Signals ................................................5-35

Routing Signals to A, B, and Z Counter Inputs................................................ 5-35

Routing Counter n Z Signal to an Output Terminal .........................................5-36

Counter n Up_Down Signal...................................................................................... 5-36

viii | ni.com

NI cDAQ-9138/9139 User Manual

Counter n HW Arm Signal ....................................................................................... 5-36

Routing Signals to Counter n HW Arm Input .................................................. 5-36

Counter n Sample Clock Signal................................................................................ 5-36

Using an Internal Source .................................................................................. 5-37

Using an External Source ................................................................................. 5-37

Routing Counter n Sample Clock to an Output Terminal ................................ 5-37

Counter n Internal Output and Counter n TC Signals .............................................. 5-37

Routing Counter n Internal Output to an Output Terminal .............................. 5-37

Frequency Output Signal .......................................................................................... 5-37

Routing Frequency Output to a Terminal ......................................................... 5-38

Default Counter/Timer Routing........................................................................................ 5-38

Counter Triggering ........................................................................................................... 5-38

Other Counter Features..................................................................................................... 5-39

Cascading Counters .................................................................................................. 5-39

Prescaling.................................................................................................................. 5-39

Synchronization Modes ............................................................................................ 5-39

80 MHz Source Mode....................................................................................... 5-40

External or Internal Source Less than 20 MHz ................................................ 5-40

Chapter 6
Digital Routing and Clock Generation

Digital Routing .................................................................................................................6-1

Clock Routing...................................................................................................................6-1

80 MHz Timebase .................................................................................................... 6-2

20 MHz Timebase .................................................................................................... 6-2

100 kHz Timebase .................................................................................................... 6-2

Appendix A
Controller Operating System and Configuration

Appendix B
Where to Go from Here

Appendix C
NI Services

Index

© National Instruments | ix

1

Getting Started with the
cDAQ Controller

The National Instruments CompactDAQ cDAQ-9138 controller features the 1.06 GHz Celeron
processor. The National Instruments CompactDAQ cDAQ-9139 controller features the

1.33 GHz Intel Core i7 processor. The NI cDAQ-9138 and NI cDAQ-9139 are available as a
Windows Embedded Standard 7 (WES7) or a LabVIEW Real-Time system.

This chapter contains information about getting started with the cDAQ controller with Windows
and with LabVIEW Real-Time:

• For NI cDAQ-9138/9139 for Windows, refer to the Installing the NI cDAQ-9138/9139 for

Windows section

• For NI cDAQ-9138/9139 for LabVIEW Real-Time, refer to the Installing the

NI cDAQ-9138/9139 for LabVIEW Real-Time section

The eight-slot cDAQ controller has a number of standard interfaces and combines with C Series
modules to measure a broad range of analog and digital I/O signals that can be logged to the local
hard drive. For specifications, refer to the specifications document for your cDAQ controller.
For module specifications, refer to the documentation included with your C Series module(s) or

ni.com/manuals.

go to

Note Go to ni.com/info and enter Info Code exswh5 for up-to-date

information about supported NI devices for the cDAQ controller.

© National Instruments | 1-1

Chapter 1 Getting Started with the cDAQ Controller

NI

cDAQ-9139

NI CompactDAQ

Figure 1-1 shows the NI cDAQ-9138/9139 controller.

Figure 1-1. NI cDAQ-9138/9139 Controller

1 2

NI

cDAQ-9139

NI CompactDAQ

3 4

5 6

18

17

16 15 14 13 12 11 10

1 POWER, DRIVE, STATUS, and USER1 LEDs
2 Power Connector
3 RS-485/422 Serial Port
4 Chassis Grounding Screw
5 CFast SSD Module Housing
6 CMOS Reset Button
7 CPU eXpansion Module (CXM) Connector
8 Installed C Series Modules
9 Module Slots
10 USB Ports

Safety Guidelines

Caution Do not operate the NI cDAQ-9138/9139 controller in a manner not

specified in these operating instructions. Product misuse can result in a hazard. You
can compromise the safety protection built into the product if the product is damaged
in any way. If the product is damaged, return it to National Instruments for repair.

7

9

11 USB Retention Standoff
12 Ethernet Ports, ACT/LINK and 10/100/1000

Ethernet LEDs

13 MXI-Express Port and LINK LED
14 Video (VGA) Port
15 RS-232 Serial Port
16 Power Button
17 RESET Button
18 DISABLE RT, SAFE MODE, CONSOLE OUT,

IP RESET, NO APP, and USER1 DIP Switches

8

1-2 | ni.com

Note Because some C Series modules may have more stringent certification

standards than the NI cDAQ-9138/9139 controller, the combined system may be
limited by individual component restrictions. Refer to the specifications document
for your cDAQ controller for more details.

Hot Surface This icon denotes that the component may be hot. Touching this

component may result in bodily injury.

NI cDAQ-9138/9139 User Manual

Electromagnetic Compatibility Guidelines

This product was tested and complies with the regulatory requirements and limits for
electromagnetic compatibility (EMC) stated in the product specifications. These requirements
and limits provide reasonable protection against harmful interference when the product is
operated in the intended operational electromagnetic environment.

This product is intended for use in residential, commercial and industrial locations. However,
harmful interference may occur in some installations or when the product is connected to a
peripheral device or a test object. To minimize interference with radio and television reception
and prevent unacceptable performance degradation, install and use this product in strict
accordance with the instructions in the product documentation.

Furthermore, any modifications to the product not expressly approved by National Instruments
could void your authority to operate it under your local regulatory rules.

Caution To ensure the specified EMC performance, operate this product only with

shielded cables and accessories. Note that the input DC power cables may be
unshielded.

Caution To ensure the specified EMC performance, do not connect the power input

to a DC mains supply or to any supply requiring a connecting cable longer than 3 m
(10 ft). A DC mains supply is a local DC electricity supply network in the
infrastructure of a site or building.

Caution To ensure the specified EMC performance, the length of any cable

connected to the video port must be no longer than 3 m (10 ft). The length of any
cable connected to the RS-232, USB, and MXI-Express ports must be no longer than
30 m (100 ft).

Caution To ensure the specified EMC performance, install snap-on, ferrite bead

(National Instruments part number 711849-01, included in the shipping kit) in
accordance with the product installation instructions.

Hardware Symbol Definitions

The following symbols are marked on your cDAQ controller.

Caution When this symbol is marked on a product, refer to the Safety Guidelines

section for information about precautions to take.

© National Instruments | 1-3

Chapter 1 Getting Started with the cDAQ Controller

⬉ᄤֵᙃѻક∵ᶧ᥻ࠊㅵ⧚ࡲ⊩ ˄Ё೑ ˅

Ё೑ᅶ᠋

National Instruments

ヺড়Ё೑⬉ᄤֵᙃѻકЁ䰤ࠊՓ⫼ᶤѯ᳝ᆇ⠽䋼ᣛҸ

(RoHS)

DŽ݇Ѣ

National InstrumentsЁ೑RoHS

ড়㾘ᗻֵᙃˈ䇋ⱏᔩ

ni.com/

environment/rohs_china

DŽ

(For information about China RoHS compliance,

go to

ni.com/environment/rohs_china

.)

ESD When this symbol is marked on a product, the product could be damaged if

subjected to Electrostatic Discharge (ESD) on the connector pins of any I/O port.
To prevent damage, industry-standard ESD prevention measures must be employed
during installation, maintenance, and operation.

EU Customers At the end of the product life cycle, all products must be sent to

a WEEE recycling center. For more information about WEEE recycling centers,
National Instruments WEEE initiatives, and compliance with WEEE Directive
2002/96/EC on Waste and Electronic Equipment, visit

.

weee

Battery Directive This device contains a long-life coin cell battery. If you need

Cd/Hg/Pb

to replace it, use the Return Material Authorization (RMA) process or contact an
authorized National Instruments service representative. For more information
about compliance with the EU Battery Directive 2006/66/EC about Batteries
and Accumulators and Waste Batteries and Accumulators, visit

environment/batterydirective

Unpacking

ni.com/environment/

ni.com/

.

The cDAQ controller ships in an antistatic package to prevent electrostatic discharge (ESD).
ESD can damage several components on the device.

Caution Never touch the exposed pins of connectors.

To avoid ESD damage in handling the device, take the following precautions:

• Ground yourself with a grounding strap or by touching a grounded object.

• Touch the antistatic package to a metal part of your computer controller before removing
the device from the package.

Remove the device from the package and inspect it for loose components or any other signs of
damage. Notify NI if the device appears damaged in any way. Do not install a damaged device
in your computer or controller.

Store the device in the antistatic package when the device is not in use.

1-4 | ni.com

NI cDAQ-9138/9139 User Manual

Installing the NI cDAQ-9138/9139 for Windows

(NI cDAQ-9138/9139 for Windows) The NI cDAQ-9138/9139 for Windows is shipped with

preloaded Windows Embedded Standard 7 (WES7), LabVIEW (evaluation version), and
NI-DAQmx driver software. The cDAQ controller and C Series module(s) are packaged
separately. You will require a monitor, VGA cable, and computer mouse and keyboard to
complete this installation process. You will also require number 1 and number 2 Phillips
screwdrivers to install and set up the cDAQ controller.

You will need the following items to set up the NI cDAQ-9138/9139 for Windows controller:

• Power connector (packaged with the cDAQ controller)

• Ferrites (packaged with the cDAQ controller)

• Screwdriver (packaged with the cDAQ controller)

• Power supply

• Monitor

• Compatible VGA cable

• Computer mouse and keyboard

• Number 1 and number 2 Phillips screwdrivers

• C Series module(s)

Note Table 1-1 lists the earliest supported driver version for each cDAQ controller

for Windows.

Table 1-1. cDAQ Controller NI-DAQmx Software Support

cDAQ Controller Earliest NI-DAQmx Support

NI cDAQ-9138 for Windows NI-DAQmx 9.5.1

NI cDAQ-9139 for Windows NI-DAQmx 9.5.1

The NI-DAQmx driver software preloaded onto your cDAQ controller is available for download

ni.com/support. The documentation for NI-DAQmx is available from Start»All

at

Programs»National Instruments»NI-DAQ. Other NI documentation is available from

ni.com/manuals.

Refer to Figure 1-1 while completing the following assembly steps.

1. Mount the cDAQ controller to a panel, wall, or DIN rail, or attach the desktop mounting

kit, as described in the Mounting the cDAQ Controller section.

2. Connect a monitor to the cDAQ controller video port with a compatible VGA cable. Refer

to the Video (VGA) Port section for more information about this connector.

3. Power on the monitor.

© National Instruments | 1-5

Chapter 1 Getting Started with the cDAQ Controller

4. Connect a computer keyboard and mouse to the bottom two USB ports on the cDAQ
controller.

5. Attach a ring lug to a 1.31 mm2 (16 AWG) or larger wire. Remove the ground screw from
the ground terminal on the front panel. Attach the ring lug to the ground terminal and
tighten the grounding screw to 0.5 N · m (4.4 lb · in.) of torque. Attach the other end of the
wire to chassis safety ground using a method appropriate for the application, as shown in
Figure 1-2. Refer to the Chassis Grounding Screw section for more information about earth
ground.

Note If you use shielded cabling to connect to a C Series module with a plastic

connector, you must attach the cable shield to the chassis grounding terminal using

2

1.31 mm

(16 AWG) or larger wire. Use shorter wire for better EMC performance.

Figure 1-2. Ring Lug Attached to Ground Terminal

38

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NI cD

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Co

NI

Note Make sure that no I/O-side power is connected to the module. If the controller

is in a nonhazardous location, the controller power can be on when you install
modules.

6. Align the module with a cDAQ controller slot. The module slots are labeled 1 to 8, left to
right.

7. Squeeze the latches and insert the module into the module slot, and press firmly on the
connector side of the module until the latches lock the module into place.

Repeat these steps to install additional modules.

1-6 | ni.com

NI cDAQ-9138/9139 User Manual

8. Verify that the DISABLE RT DIP switch is in the ON position so that the controller boots

into the Windows operating system. Refer to the DIP Switches section for more information
about the DISABLE RT DIP switch.

Figure 1-3. DISABLE RT DIP Switch in ON Position

DISABLE RT
SAFE MODE
CONSOLE OUT
IP RESET
NO APP
USER1

ON OFF

9. Wire your external power source as outlined in the Wiring Power to the cDAQ Controller

section. The cDAQ controller requires an external power supply that meets the
specifications listed in the specifications document for your cDAQ controller.

10. Turn on the external power supply.

11. Press the power button on the front panel of the cDAQ controller.

When the cDAQ controller powers on, the Power LED lights and the controller runs a
power-on self test (POST). When the POST is complete, the operating system is loaded.

12. Go through the steps on the Set Up Windows screen that opens on your monitor. Windows
prepares your desktop.

13. Wire the C Series module as indicated in the C Series module documentation, available
from

ni.com/manuals.

14. Self-test your controller in Measurement & Automation Explorer (MAX) by

double-clicking the MAX icon on the desktop to open MAX. Expand Devices and
Interfaces, right-click NI cDAQ-<model number>, and select Self-Test. Self-test

performs a brief test to determine successful controller installation.

15. Run a Test Panel in MAX by expanding Devices and Interfaces»NI cDAQ-<model
number>, right-clicking your C Series module, and selecting Test Panels to open a test

panel for the selected module.
If the test panel displays an error message, refer to ni.com/support.

New users can view and use the Voltage - Continuous Input VI, available in the
LabVIEW Example Finder. Experienced users can use the LabVIEW Sample Projects, Finite
Measurement (NI-DAQmx) and Continuous Measurement and Logging (NI-DAQmx).

Note When in use, the cDAQ controller may become warm to the touch. This is

normal.

Note The network behavior is determined by the Windows network drivers. Refer

to the Windows documentation for information about configuring IP settings.

© National Instruments | 1-7

Chapter 1 Getting Started with the cDAQ Controller

Note You can use the cDAQ controller BIOS setup utility to configure the cDAQ

controller to start immediately when power is applied or to respond to the front-panel
power button. Refer to the Power/Wake Configuration Submenu section of
Appendix A, Controller Operating System and Configuration , for information about
the different powerup behaviors you can configure. The power button is enabled by
default so that the cDAQ controller does not power on until the power button is
pressed.

Installing the NI cDAQ-9138/9139 for LabVIEW Real-Time

The NI cDAQ-9138/9139 for LabVIEW Real-Time features a hard drive formatted for
LabVIEW Real-Time. The cDAQ controller and C Series module(s) are packaged separately.
You will need a host computer running Windows 10/8.1/8/7/Vista/XP (check your driver and
ADE readme files for specific version compatibility). You will also require number 1 and
number 2 Phillips screwdrivers to install and set up the cDAQ controller.

You will need the following items to set up the NI cDAQ-9138/9139 for LabVIEW Real-Time
controller:

• Power connector (packaged with the cDAQ controller)

• USB cable (packaged with the cDAQ controller)

• Ferrites (packaged with the cDAQ controller)

• Screwdriver (packaged with the cDAQ controller)

• Host computer running Windows (check your driver and ADE readme files for specific
version compatibility)

• LabVIEW software

• LabVIEW Real-Time software

• NI-DAQmx driver (packaged with the cDAQ controller)

• Power supply

• Number 1 and number 2 Phillips screwdrivers

• C Series module(s)

Refer to Figure 1-1 while completing the following assembly steps.

1. Install LabVIEW on your host computer, as described in the LabVIEW Installation Guide.

2. Install LabVIEW Real-Time on your host computer, as described in the
LabVIEW Real-Time Module Release and Upgrade Notes.

3. Install NI-DAQmx on your host computer, as described in the Read Me First: NI-DAQmx
and DAQ Device Installation Guide.

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NI cDAQ-9138/9139 User Manual

Note Table 1-2 lists the earliest supported driver version for each cDAQ controller

for LabVIEW for Real-Time.

Table 1-2. cDAQ Controller NI-DAQmx Software Support

cDAQ Controller Earliest NI-DAQmx Support

NI cDAQ-9138 for LabVIEW Real-Time NI-DAQmx 9.6

NI cDAQ-9139 for LabVIEW Real-Time NI-DAQmx 9.6

The NI-DAQmx driver software is included on the disk shipped with your kit and is available
for download at

ni.com/support. The documentation for NI-DAQmx is available after

installation from Start»All Programs»National Instruments»NI-DAQ. Other NI

documentation is available from

ni.com/manuals.

4. Power on the host computer and connect it to an Ethernet network.

5. Mount the cDAQ controller to a panel, wall, or DIN rail, or attach the desktop mounting

kit, as described in the Mounting the cDAQ Controller section.

6. Attach a ring lug to a 1.31 mm

2

(16 AWG) or larger wire. Remove the ground screw from
the ground terminal on the front panel. Attach the ring lug to the ground terminal and
tighten the grounding screw to 0.5 N · m (4.4 lb · in.) of torque. Attach the other end of the
wire to chassis safety ground using a method appropriate for the application, as shown in
Figure 1-2. Refer to the Chassis Grounding Screw section for more information about earth
ground.

Note If you use shielded cabling to connect to a C Series module with a plastic

connector, you must attach the cable shield to the chassis grounding terminal using

2

1.31 mm

Note Make sure that no I/O-side power is connected to the module. If the controller

(16 AWG) or larger wire. Use shorter wire for better EMC performance.

is in a nonhazardous location, the controller power can be on when you install
modules.

7. Align the module with a cDAQ controller slot. The module slots are labeled 1 to 8, left to
right.

8. Squeeze the latches and insert the module into the module slot, and press firmly on the
connector side of the module until the latches lock the module into place.

Repeat these steps to install additional modules.

© National Instruments | 1-9

Chapter 1 Getting Started with the cDAQ Controller

9. Verify that the DISABLE RT DIP switch is in the OFF position so that the controller will

boot into LabVIEW Real-Time. Refer to the DIP Switches section for more information
about the DISABLE RT DIP switch.

Figure 1-4. DISABLE RT DIP Switch in OFF Position

DISABLE RT
SAFE MODE
CONSOLE OUT
IP RESET
NO APP
USER1

ON OFF

10. Wire your external power source as outlined in the Wiring Power to the cDAQ Controller

section. The cDAQ controller requires an external power supply that meets the
specifications listed in the specifications document for your cDAQ controller.

11. Turn on the external power supply.

12. Connect RJ-45 Ethernet port 1 on the cDAQ controller to the same Ethernet network as the
host computer with a shielded straight through Category 5 (CAT-5) or better shielded,
twisted-pair Ethernet cable.

Caution To prevent data loss and to maintain the integrity of your Ethernet

installation, do not use a cable longer than 100 m.

If you need to build your own cable, refer to the Ethernet Cabling section for information
about Ethernet cable wiring connections.

13. Press the power button on the front panel of the cDAQ controller.

When the cDAQ controller powers on, the Power LED lights and the controller runs a
power-on self test (POST). When the POST is complete, the operating system is loaded.

The cDAQ controller attempts to initiate a DHCP network connection at powerup. If the
cDAQ controller is unable to obtain an IP address, it connects to the network with a
link-local IP address with the form

169.254.x.x. The host computer communicates with

the cDAQ controller over a standard Ethernet connection.

Note You can use the cDAQ controller BIOS setup utility to configure the cDAQ

controller to start immediately when power is applied or to respond to the front-panel
power button. Refer to the Power/Wake Configuration Submenu section of
Appendix A, Controller Operating System and Configuration , for information about
the different powerup behaviors you can configure. The power button is enabled by
default so that the cDAQ controller does not power on until the power button is
pressed.

Note You can configure the cDAQ controller to launch an embedded stand-alone

LabVIEW RT application each time you boot the controller. Refer to the Running a

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NI cDAQ-9138/9139 User Manual

Stand-Alone Real-Time Application (RT Module) topic of the LabVIEW Help for
more information about startup applications.

Note After powerup, you can install software on the cDAQ controller. For RT

systems, you can also change the network settings using Measurement & Automation
Explorer (MAX) on a host computer.

14. Wire the C Series module as indicated in the C Series module documentation.

15. Launch Measurement & Automation Explorer (MAX) by double-clicking the MAX icon

on the host computer desktop. Expand Remote Systems and select NI-cDAQ<model

number>-<serial number>1. Click the System Settings tab and verify that the controller

has an Ethernet IP address and that System State reads Connected - No software

installed

.

16. Expand NI-cDAQ<model number>-<serial number>. Right-click Software and select
Add/Remove Software.

17. In the window that opens, select NI-DAQmx, and then select Install the feature. Other

required dependencies will be selected automatically.

18. Click Next to confirm the requested software features.

19. Click Next to install the software. After the installation completes, the cDAQ controller

reboots.

20. Click Finish.

21. In MAX, expand Remote Systems and select NI-cDAQ<model number>-<serial number>.
Click the System Settings tab and verify that the System State reads

Running

.

Connected -

22. Self-test your controller in MAX by expanding NI-cDAQ<model number>-<serial
number>»Devices and Interfaces. Right-click NI cDAQ-<model number> and select

Self-Test. Self-test performs a brief test to determine successful controller installation.

23. Run a Test Panel in MAX by expanding NI-cDAQ<model number>-<serial number>»
Devices and Interfaces»NI cDAQ-<model number>, right-clicking your C Series
module, and selecting Test Panels to open a test panel for the selected module.

If the test panel displays an error message, refer to ni.com/support.

New users can view and use the Voltage - Continuous Input VI, available in the
LabVIEW Example Finder. Experienced users can use the LabVIEW Sample Projects,
LabVIEW Real-Time Control (NI-DAQmx) and LabVIEW Waveform Acquisition and Logging
(NI-DAQmx).

Note For information about configuring network settings, refer to the Configure

Network Settings book of the MAX Remote Systems Help. In MAX, click Help»Help

1

The serial number listed in MAX is the last eight digits of the cDAQ controller primary MAC address.

© National Instruments | 1-11

Chapter 1 Getting Started with the cDAQ Controller

IP RESET

ON OFF

IP RESET

ON OFF

Topics»Remote Systems. On the Contents tab, browse to LabVIEW Real-Time
Target Configuration»Configure Network Settings.

For information about configuring the controller to launch an embedded stand-alone application
at startup, refer to the LabVIEW Help. For more information about setting up the controller as
an RT target, refer to the LabVIEW Help. For more information about configuring the controller
in MAX, refer to the MAX Help.

You can also change the network settings using Measurement & Automation Explorer (MAX)
on a host computer.

Troubleshooting Network Communication in NI cDAQ-9138/9139 for LabVIEW Real-Time Controller

If the controller cannot communicate with the network, you can use the IP RESET DIP switch
to manually restore the controller to the default network settings. When you reboot the controller
with the IP RESET DIP switch in the ON position, the controller attempts to connect to the
network using DHCP. If the controller is unable to obtain an IP address, it connects to the
network with a link-local IP address with the form

Complete the following steps to restore the controller to the default network settings.

1. Move the IP RESET DIP switch to the ON position.

Figure 1-5. IP RESET DIP Switch in ON Position

169.254.x.x.

2. Push the RESET button to cycle power to the cDAQ controller.

3. Configure the IP and other network settings in MAX from the host computer.

4. Move the IP RESET DIP switch to the OFF position.

Figure 1-6. IP RESET DIP Switch in OFF Position

For more information about troubleshooting network communication, refer to the MAX Remote
Systems Help topic in the Measurement & Automation Explorer Help.

Wiring Power to the cDAQ Controller

The cDAQ controller requires an external power source as described in the Power Requirements
section of the specifications document for your cDAQ controller. Some suggested NI power
supplies are listed in Table 1-10. The cDAQ controller filters and regulates the supplied power
and provides power to all of the modules. The cDAQ controller has a primary power input, V1,
and a secondary power input, V2. The POWER LED on the front panel identifies the power input
in use. When the LED is lit green, V1 is in use; when the LED is lit yellow, V2 is in use.

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NI cDAQ-9138/9139 User Manual

Caution Do not connect V2 to a DC mains supply or to any supply requiring a

connecting cable longer than 3 m (10 ft). A DC mains supply is a local DC electricity
supply network in the infrastructure of a site or building.

Complete the following steps to connect a power source to the cDAQ controller.

1. Make sure the power source is turned off.

2. Install the ferrite shipped with the cDAQ controller across the negative and positive leads
of the power source, approximately 50 to 75 mm (2 to 3 in.) from the ends of the leads near
the cDAQ controller, as shown in Figure 1-7.

Figure 1-7. Installing the Ferrite on the Power Leads

3. Loosen the connector screw flanges and remove the power screw terminal connector plug
from the cDAQ controller. Figure 1-8 shows the terminal screws, which secure the wires in
the screw terminals, and the connector screw flanges, which secure the connector plug on
the front panel.

Figure 1-8. Power Screw Terminal Connector Plug

1

2

1

1 Terminal Screw 2 Connector Screw Flanges

Caution Do not tighten or loosen the terminal screws on the power connector while

the power is on.

4. Connect the positive lead of the primary power source to the V1 terminal of the power
connector plug and tighten the terminal screw.

5. Connect the negative lead of the primary power source to one of the C terminals of the
power screw terminal connector plug and tighten the terminal screw.

6. Optionally, you can connect the positive lead of a secondary power source to the V2
terminal and the negative lead to the other C terminal.

© National Instruments | 1-13

Chapter 1 Getting Started with the cDAQ Controller

7. Install the power connector plug on the front panel of the cDAQ controller and tighten the
connector screw flanges.

8. Turn on the external power source(s).

The cDAQ controller uses V1 if the voltage across V1 and C is 9 V or greater. If the V1-to-C
voltage drops below 9 V, the cDAQ controller switches to V2. If the V2-to-C voltage is less than
9 V, operation may be interrupted.

Note If the cDAQ controller is using V1 and a secondary power source is

connected to V2, there is a small leakage current on V2. The leakage current depends
on the V2-to-C voltage. Refer to the Power Requirements section of the
specifications document for your cDAQ controller for nominal values of this leakage
current.

If the power source is connected to the power connector using long wiring with high DC
resistance, the voltage at the power connector may be significantly lower than the specified
voltage of the power source.

The C terminals are internally connected to each other but are not connected to chassis ground.
You can connect the C terminals to chassis ground externally. Refer to the Power Requirements
section of the specifications document for your cDAQ controller for information about the
power supply input range. Refer to the Safety Voltages section of the specifications document
for your cDAQ controller for information about the maximum voltage from terminal to chassis
ground.

Mounting the cDAQ Controller

You can use the cDAQ controller on a desktop or mount it to a panel, wall, DIN rail, or rack. For
accessory ordering information, refer to the pricing section of the NI cDAQ-9138/9139 product
page at ni.com.

Note The cDAQ controller was designed and tested in multiple mounting

configurations. The varied mounting orientations or configurations can reduce the
maximum allowable ambient temperature and can affect the accuracy of C Series
modules in the controller. Visit

cdaqmounting for more information about mounting and accuracy.

The following sections contain instructions for the mounting methods. Before using any of these
mounting methods, record the serial number from the side of the controller. You may be unable
to read the serial number after you have mounted the controller.

Caution You must mount the controller horizontally on a flat, vertical, metallic

surface using the NI panel mount kit, part number 781919-01, to achieve an allowable
operating ambient temperature of 45 to 55 °C. Mounting the controller in a different
orientation or on a nonmetallic surface reduces the maximum allowable ambient

1-14 | ni.com

ni.com/info and enter the Info Code

NI cDAQ-9138/9139 User Manual

Up

NI NI cDAQ-9139cDAQ-9139

NI CompactDAQNI CompactDAQ

Cabling Clearance

50.8 mm (2.00 in.)

Measure Ambient
Temperature Here

50.8 mm
(2.00 in.)

63.5 mm

(2.50 in.)

63.5 mm
(2.50 in.)

50.8 mm
(2.00 in.)

50.8 mm
(2.00 in.)

29.2 mm
(1.15 in.)

Measure Ambient
Tem p e rature Here

Cooling Outline

50.8 mm (2.00 in.)

Cooling Outline

50.8 mm (2.00 in.)

88.1 mm
(3.47 in.)

NI NI cDAQ-9139cDAQ-9139

NI CompactDAQNI CompactDAQ

temperature and can affect the measurement accuracy of modules in the controller.
Figure 1-9 shows the controller mounted horizontally. Refer to the Mounting the cDAQ

Controller on a Panel section for complete panel mounting instructions.

Measure the ambient temperature at each side of the controller, 63.5 mm (2.5 in.) from
the side and 50.8 mm (2 in.) forward from the rear of the controller, as shown in
Figure 1-10.

For more information about how different mounting configurations can cause
temperature derating, go to

ni.com/info and enter the Info Code cdaqmounting.

Figure 1-9. NI cDAQ-9138/9139 Mounted Horizontally with Panel Mount Kit

Figure 1-10. NI cDAQ-9138/9139 Temperature, Cooling, and Cabling Dimensions

© National Instruments | 1-15

Chapter 1 Getting Started with the cDAQ Controller

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Caution Your installation must meet the following requirements for space and

cabling clearance, as shown in Figure 1-10:

• Allow 50.8 mm (2 in.) on the top and the bottom of the controller for air
circulation.

• Allow 50.8 mm (2 in.) in front of modules for cabling clearance for common
connectors, such as the 10-terminal, detachable screw terminal connector.

Using the cDAQ Controller on a Desktop

Complete the following steps to install the NI desktop mount kit, part number 781988-01, on the
cDAQ controller.

9. Align one of the end brackets with the mounting hole at one of the ends of the controller,
as shown in Figure 1-11.

Figure 1-11. Connecting the End Brackets to the Controller

-9139
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1 Mounting Holes 2 Captive Screw

10. Use a number 2 Phillips screwdriver to tighten the captive screw on the end bracket.

11. Repeat steps 9 and 10 to attach the other end bracket to the other end of the controller.

Note To achieve the highest accuracy when mounting the controller in the desktop

kit, NI recommends that you operate the controller with the modules rotated forward,
as shown in Figure 1-11. Visit

cdaqmounting for more information about mounting and accuracy.

1-16 | ni.com

ni.com/info and enter the Info Code

NI cDAQ-9138/9139 User Manual

NI NI cDAQ-9139cDAQ-9139

NI CompactDAQNI CompactDAQ

39.6 mm
(1.56 in.)

28.2 mm
(1.11 in.)

28.1 mm

(1.11 in.)

127.2 mm
(5.01 in.)

136.2 mm
(5.36 in.)

Figure 1-12 shows the dimensions of a controller after the desktop mounting kit is installed.

Figure 1-12. Dimensions of the cDAQ Controller with Desktop Mounting Kit Installed

Mounting the cDAQ Controller on a Panel

Panel or wall mounting is the best method for applications that are subject to high shock and
vibration. You can use the NI panel mount kit, part number 781919-01, to mount the cDAQ
controller on a flat surface. Complete the following steps.

1. Fasten the mounting plate to the controller using a number 2 Phillips screwdriver and
six M4 × 10 screws. National Instruments provides these screws with the panel mount kit.
Tighten the screws to a maximum torque of 1.3 N ·

m (11.5 lb · in.).

© National Instruments | 1-17

Chapter 1 Getting Started with the cDAQ Controller

NI

cDAQ-9139

NI CompactDAQ

Figure 1-13. Installing the Mounting Plate on the cDAQ Controller

Figure 1-14. Dimensions of the cDAQ Controller with Mounting Plate Installed

406.4 mm
(16.00 in.)

387.4 mm

9.5 mm

(0.38 in.)

2.5 mm

(0.10 in.)

25.4 mm
(1.00 in.)

1-18 | ni.com

NI

cDAQ-9139

NI CompactDAQ

108.9 mm
(4.29 in.)

193.7 mm
(7.63 in.)

58.2 mm
(2.29 in.)

(15.25 in.)

188.6 mm
(7.43 in.)

193.7 mm
(7.63 in.)

108.9 mm
(4.29 in.)

22.2 mm
(0.88 in.)

7.2 mm
(0.29 in.)

114.3 mm
(4.50 in.)

138.9 mm
(5.47 in.)

NI cDAQ-9138/9139 User Manual

NI

cDAQ-9139

NI CompactDAQ

2. Fasten the mounting plate to the surface using the screwdriver and screws that are
appropriate for the surface. The maximum screw size is M4 or number 8.

3. Optionally, you can use two additional screws to attach the mounting plate to the panel or
wall permanently, preventing the controller from being removed.

Figure 1-15. Permanently Attaching the Mounting Plate to the Panel or Wall

NI

cDAQ-9139

NI CompactDAQ

Mounting the cDAQ Controller on a DIN Rail

Use the DIN rail mounting method if you already have a DIN rail configuration or if you need
to be able to remove the controller quickly. You can order the NI DIN rail mount kit, part number
781987-01, to mount the controller on a DIN rail. You need one clip for mounting the controller
on a standard 35 mm DIN rail. Complete the following steps to mount the controller on a DIN
rail.

1. Fasten the DIN rail clip to the controller using a number 2 Phillips screwdriver and
three M4 × 10 screws. National Instruments provides these screws with the DIN rail mount
kit. Tighten the screws to a maximum torque of 1.3 N ·
rail kit is installed as shown in Figure 1-16, with the larger lip of the DIN clip positioned
up. When the DIN rail kit is properly installed, the cDAQ controller is centered on the DIN
rail.

m (11.5 lb · in.). Make sure the DIN

© National Instruments | 1-19

Chapter 1 Getting Started with the cDAQ Controller

Figure 1-16. Installing the DIN Rail Clip on the cDAQ Controller

2. Insert one edge of the DIN rail into the deeper opening of the DIN rail clip, as shown in
Figure 1-17, and press down firmly on the controller to compress the spring until the clip
locks in place on the DIN rail.

Figure 1-17. DIN Rail Clip Parts Locator Diagram

1

2

3

1 DIN Rail Clip 2 DIN Rail Spring 3 DIN Rail

Caution Remove the modules before removing the controller from the DIN rail.

Mounting the cDAQ Controller on a Rack

NI offers two rack mount kits, part numbers 779102-01 and 781989-01, that you can use to
mount the cDAQ controller and other DIN rail–mountable equipment on a standard 19-inch
rack. You must order the NI DIN rail mount kit, part number 781987-01, in addition to these kits.

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NI cDAQ-9138/9139 User Manual

Removing Modules from the cDAQ Controller

Complete the following steps to remove a C Series module from the cDAQ controller.

1. Make sure that no I/O-side power is connected to the module. If the controller is in a
nonhazardous location, the controller power can be on when you remove modules.

2. Squeeze the latches on both sides of the module and pull the module out of the controller.

cDAQ Controller Features

The cDAQ controller features many ports, DIP switches, LEDs, a RESET button, and a power
button. Refer to Figure 1-1 for the locations of these features on the cDAQ controller.

Video (VGA) Port

The cDAQ controller video (VGA) port, shown in Figure 1-1, outputs graphics using VESA
standard VGA analog signaling. Use this port to connect a monitor to program the
NI cDAQ-9138/9139 for Windows. Table 1-3 lists the video port pin locations and VGA
signals.

Table 1-3. Video Port Pin Locations

Pinout Pin Signal Name Signal Description

1 RED Red analog video signal

2 GREEN Green analog video signal

3 BLUE Blue analog video signal

4 No Connect —

5 GND Ground reference

6 RED RETURN Ground reference

15

5

10

14

4

9

13

3

8

12

2

7

11

1

6

7 GREEN RETURN Ground reference

8 BLUE RETURN Ground reference

9 PWR 5 V power for DDC

10 GND Ground return for power

11 No Connect —

12 DDC_D Data signal of serial communication

13 HSYNC Horizontal synchronization signal

14 VSYNC Vertical synchronization signal

15 DDC_C Clock signal of serial communication

© National Instruments | 1-21

Chapter 1 Getting Started with the cDAQ Controller

Caution Do not hot-swap VGA devices while the cDAQ controller is in a

hazardous location or connected to high voltages.

USB Ports

The cDAQ controller supports common USB mass-storage devices such as USB Flash drives
and USB-to-IDE adapters formatted with FAT16 and FAT32 file systems. LabVIEW usually
maps USB devices to the
You can also use these ports to connect a computer keyboard and mouse for cDAQ-9138/9139
for Windows programming. Go to ni.com/info and enter Info Code exswh5 for up-to-date
information about supported NI devices for the cDAQ controller.

Note For optimal performance, NI recommends that you use the upper two USB

ports for high-throughput USB peripherals, such as mass storage devices or
expansion I/O controller.

Go to ni.com/info and enter Info Code exyerk for information about best practices for data
logging performance with the NI cDAQ-9138/9139.

Refer to Figure 1-1 for the location of the four USB ports on the cDAQ controller. Refer to
Table 1-4 for USB pin locations and signal descriptions.

Pinout Pin Signal Name Signal Description

U:, V:, W:, or X: drive, starting with the U: drive if it is available.

Table 1-4. USB Port Pin Locations

1 VCC Cable power (+5 V)

2 D- USB data-

Pin 4

Pin 1

Caution Do not hot-swap USB devices while the cDAQ controller is in a

3 D+ USB data+

4 GND Ground

hazardous location or connected to high voltages.

Ethernet Ports

The cDAQ controller has two tri-speed RJ-45 Ethernet ports, shown in Figure 1-1.

Refer to Figure 1-18 for Ethernet pin locations and signal descriptions. The Ethernet signal
names are listed as Fast Ethernet signal name, RX/TX +/-, and then Gigabit Ethernet signal
name, (RX/TX_x+/-).

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NI cDAQ-9138/9139 User Manual

Figure 1-18. Ethernet Port Pin Locations: Fast Ethernet Signals (Gigabit Ethernet Signals)

1 TX+ (TX_A+)
2 TX– (TX_A–)
3 RX+ (RX_B+)
4 No Connect (TX_C+)
5 No Connect (TX_C–)
6 RX– (RX_B–)
7 No Connect (RX_D+)
8 No Connect (RX_D–)

Note Both Ethernet ports perform automatic crossover configuration so you do not

need to use a crossover cable to connect to a host computer.

(NI cDAQ-9138/9139 for Windows) Both Ethernet ports are enabled and configured as DHCP,

to “obtain an IP address automatically,” by default. The Ethernet ports can be configured in the
Windows Control Panel, under the Network and Internet category.

Ethernet port 1 provides Wake-on-LAN functionality and AMT support. Ethernet port 1 remains
powered when the controller is in sleep mode.

(NI cDAQ-9138/9139 for LabVIEW Real-Time) You must use Ethernet port 1 to configure the

NI cDAQ-9138/9139 for LabVIEW Real-Time; you cannot configure the controller through
Ethernet port 2. To use Ethernet port 2, you must assign a static IP address to the port using
MAX. The IP address must be on a different subnet than the IP address of Ethernet port 1. You
cannot use DHCP with Ethernet port 2. For more information about using Ethernet port 2, go to

ni.com/info and enter the Info Code dualenet.

Ethernet LEDs

Each Ethernet port has two LEDs—ACT/LINK and 10/100/1000. Refer to Table 1-5 for
information about the Ethernet ACT/LINK and 10/100/1000 LAN connector LEDs.

Table 1-5. Ethernet LED Indications

LED LED Color LED State Indication

ACT/
LINK

— Off LAN link not established

Green Solid LAN link established

Flashing Activity on LAN

© National Instruments | 1-23

Chapter 1 Getting Started with the cDAQ Controller

Table 1-5. Ethernet LED Indications (Continued)

LED LED Color LED State Indication

10/100/
1000

Ye ll o w Solid 1,000 Mbit/s data rate selected

Green Solid 100 Mbit/s data rate selected

— Off 10 Mbit/s data rate selected

Ethernet Cabling

Table 1-6 shows the shielded Ethernet cable wiring connections for both straight through and
crossover cables.

Table 1-6. Ethernet Cable Wiring Connections

Connector 2

Pin Connector 1

1 white/orange white/orange white/green

2 orange orange green

3 white/green white/green white/orange

4 blue blue blue

5 white/blue white/blue white/blue

6 green green orange

7 white/brown white/brown white/brown

8 brown brown brown

Straight Through Crossover

Pin 1

1-24 | ni.com

Connector 1 Connector 2

Pin 1 Pin 8Pin 8

NI cDAQ-9138/9139 User Manual

RS-232 Serial Port

The cDAQ controller has an RS-232 serial port, shown in Figure 1-1, to which you can connect
devices such as displays or input devices. Use the Serial VIs to read from and write to the serial
port. Refer to the LabVIEW Help for information about the Serial VIs. Refer to Figure 1-19 for
pin locations and signal descriptions.

Figure 1-19. RS-232 Serial Port Pin Locations

DSR

RTS

CTS

RI/WAKE

RXD

2

7

3

TXD

8

4

DTR

9

5

GND

DCD

1

6

You can use the Ring Indicator (RI/WAKE) on pin 9 to wake the controller from a low power
state. You can drive RI/WAKE with logic-level signals where a high level greater than 2.4 V
signals a wake event.

RS-485/422 Serial Port

The cDAQ controller has an RS-485/422 serial port, COM 2, accessible through a 10-position
RJ-50 modular jack. The shield of the RJ-50 connector is isolated from the controller, enabling
you to use shielded cables while maintaining isolation. The RS-485/422 serial port is shown in
Figure 1-1. Refer to Figure 1-20 for pin locations and signal descriptions.

Figure 1-20. RS-485/422 Serial Port Pin Locations

1 No Connect
2 TXD–
3 TXD+
4 No Connect
5 No Connect
6 RXD–
7 RXD+
8 No Connect
9 No Connect
10 Isolated GND

COM 2 is designed to operate in four-wire (RS-422) or two-wire mode.

NI offers a DIN rail-mountable screw terminal adapter (NI part number 778674-01) that you can
use to connect termination resistors to COM 2.

© National Instruments | 1-25

Chapter 1 Getting Started with the cDAQ Controller

Cable adapters for the 10-position modular jacks are available from NI. Part numbers
182845-01, -02, and -03 are 1, 2, and 3 m cable adapters for connecting the 10-position modular
jack to a 9-position D-SUB plug.

ni.com/info and enter Info Code exswh5 for up-to-date information about supported

Go to
NI devices for the NI cDAQ-9138/9139 controller.

MXI-Express Port

You can use the cDAQ controller MXI-Express port, shown in Figure 1-1, to connect to a
MXI-Express controller. The NI cDAQ-9138/9139 for Windows controller support all
NI MXI-Express controller. Currently, the NI cDAQ-9138/9139 for LabVIEW Real-Time
controller support the RIO expansion controller. Go to

exswh5 for up-to-date information about supported NI devices for the NI cDAQ-9138/9139

controller.

Complete the following steps to connect one or more cDAQ controller to a MXI-Express device.

1. Make sure the MXI-Express device is configured and powered off.

2. Make sure the cDAQ controller is powered off.

3. Connect the cDAQ controller to the MXI-Express device using a x1 cable. Refer to
Table 1-10 for MXI-Express cable lengths and part numbers.

4. Power on the MXI-Express device.

5. Power on the cDAQ controller.

The MXI-Express port has one LINK LED. Refer to Table 1-8 for information about the
MXI-Express LINK LED behavior.

ni.com/info and enter Info Code

Note Do not connect MXI-Express devices to the cDAQ controller while the

controller is powered on. The MXI-Express device may not be detected by the cDAQ
controller.

DIP Switches

The cDAQ controller features six DIP switches, shown in Figure 1-1.

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NI cDAQ-9138/9139 User Manual

Table 1-7. DIP Switches

Switch Description

DISABLE RT (NI cDAQ-9138/9139 for LabVIEW Real-Time) The position of the

DISABLE RT determines the operating system the cDAQ controller
boots into. If the switch is in the OFF position, the controller boots into
LabVIEW RT. Move the switch to the ON position to boot the cDAQ
controller from an external drive.

(NI cDAQ-9138/9139 for Windows) The position of the DISABLE RT

determines the operating system the cDAQ controller boots into. If the
switch is the ON position, the controller boots into Windows Embedded
Standard 7 (WES7).

If the switch is in the OFF position, the controller does not boot into
Windows.

SAFE MODE (NI cDAQ-9138/9139 for LabVIEW Real-Time) The position of the

SAFE MODE switch determines whether the embedded LabVIEW
Real-Time engine launches at startup. If the switch is in the OFF
position, the LabVIEW Real-Time engine launches. If the switch is in the
ON position at startup, the cDAQ controller launches only the essential
services required for updating its configuration and installing software.
The LabVIEW Real-Time engine does not launch.

If the software on the controller is corrupted, you must put the controller
into safe mode and reformat the controller drive. You can put the
controller into safe mode by powering it up either with the SAFE MODE
switch in the ON position or with no software installed on the drive.
Refer to the Measurement & Automation Explorer Help for more
information about installing software on the controller and reformatting
the drive on the controller.

Keep the SAFE MODE switch in the OFF position during normal
operation.

(NI cDAQ-9138/9139 for Windows) NI recommends that you keep the

SAFE MODE switch in the OFF position at all times.

© National Instruments | 1-27

Chapter 1 Getting Started with the cDAQ Controller

Table 1-7. DIP Switches (Continued)

Switch Description

CONSOLE OUT (NI cDAQ-9138/9139 for LabVIEW Real-Time) The position of the

CONSOLE OUT switch determines whether console input and output are
redirected to the RS-232 serial port. If the switch is in the ON position, console
input and output are redirected to the RS-232 serial port. If the switch is in the OFF
position, the RS-232 serial port functions normally.

With a serial-port terminal program, you can use console output to read the POST
results, BIOS revision, IP addresses, and software installed on the cDAQ
controller. Use a null-modem cable to connect the RS-232 serial port on the
controller to a computer. Push the CONSOLE OUT switch to the ON position.
Make sure that the serial-port terminal program is configured with the same
settings as the RS-232 serial port. The RS-232 serial port in CONSOLE OUT
mode has the following default configuration settings:

9,600 bits per second

Eight data bits

No parity

One stop bit

No flow control

You can use the BIOS setup menu to modify the CONSOLE OUT configuration
settings for the RS-232 serial port.

Keep the CONSOLE OUT switch in the OFF position during normal operation.

(NI cDAQ-9138/9139 for Windows) NI recommends that you keep the

CONSOLE OUT switch in the OFF position at all times.

IP RESET (NI cDAQ-9138/9139 for LabVIEW Real-Time) Push the IP RESET

switch to the ON position and reboot the controller to reset the IP address and
other TCP/IP settings of the controller to the factory defaults. Refer to the Using

the BIOS Setup Utility to Change Configuration Settings section of Appendix A,
Controller Operating System and Configuration, for more information about

resetting the IP address. You can also push this switch to the ON position to
unlock a controller that was previously locked in MAX.

1-28 | ni.com

(NI cDAQ-9138/9139 for Windows) NI recommends that you keep the IP

RESET switch in the OFF position at all times.

NI cDAQ-9138/9139 User Manual

Table 1-7. DIP Switches (Continued)

Switch Description

NO APP (NI cDAQ-9138/9139 for LabVIEW Real-Time) Push the NO APP switch

to the ON position to prevent a LabVIEW RT startup application from running at
startup. If you want to permanently disable a LabVIEW RT application from
running at startup, you must disable it in LabVIEW.

To run an application at startup, push the NO APP switch to the OFF position,
create an application using the LabVIEW Application Builder, and configure the
application in LabVIEW to launch at startup.

If you already have an application configured to launch at startup and you push
the NO APP switch from ON to OFF, the startup application is automatically
enabled. For more information about automatically launching VIs at startup and
disabling VIs from launching at startup, refer to the Running a Stand-Alone
Real-Time Application (RT Module) topic of the LabVIEW Help.

(NI cDAQ-9138/9139 for Windows) NI recommends that you keep the NO

APP switch in the OFF position at all times.

USER1 (NI cDAQ-9138/9139 for LabVIEW Real-Time) You can define the

USER1 switch for your application. To define the purpose of this switch in your
embedded application, use the RT Read Switch VI in your LabVIEW RT
embedded VI. For more information about the RT Read Switch VI, refer to the
LabVIEW Help.

(NI cDAQ-9138/9139 for Windows) NI recommends that you keep the

USER1 switch in the OFF position at all times.

Power Connector

Refer to the Wiring Power to the cDAQ Controller section and the specifications document for
your cDAQ controller for more information about the power connector

RESET Button

Pressing the RESET button, shown in Figure 1-1, resets the processor in the same manner as
cycling power.

Power Button

Pressing the power button, shown in Figure 1-1, powers the cDAQ controller on and off. If the
cDAQ controller becomes unresponsive, you can power it off by holding the power button down
for 4 seconds. Refer to the Power/Wake Configuration Submenu section of Appendix A,

Controller Operating System and Configuration, for information about configuring how the

controller responds to the power button.

© National Instruments | 1-29

Chapter 1 Getting Started with the cDAQ Controller

LEDs

The cDAQ controller features four LEDs—POWER, DRIVE, STATUS, and USER1—on its
front panel, two LEDs—ACT/LINK and 10/100/1000—near each Ethernet connector, and one
LINK LED near the MXI-Express port. Refer to Figure 1-1 for the locations of the LEDs.
Table 1-8 lists the LEDs and status indications.

Table 1-8. LED Indications

LED

LINK Green Solid MXI-Express communication established

POWER Green Solid The cDAQ controller is powered from the V1 input

DRIVE Yellow Solid An internal drive is being accessed.

LED

Color LED State Indication

Yellow Solid MXI-Express communication broken or no cable is

connected

Yellow Solid The cDAQ controller is powered from the V2 input

— Off The controller is not powered.

1-30 | ni.com

NI cDAQ-9138/9139 User Manual

Table 1-8. LED Indications (Continued)

LED

LED

Color LED State Indication

STATUS Yellow 1 flash every

few seconds

2 flashes every
few seconds

3 flashes every
few seconds

4 flashes every
few seconds

Continuously
flashing

Continuously
flashing or
solid

Software error—The controller is unconfigured. Use
MAX to configure the controller. Refer to the
Measurement & Automation Explorer Help for
information about configuring the controller.

Software error—The controller has detected an error in its
software. This usually occurs when an attempt to upgrade
the software is interrupted. Reinstall software on the
controller. Refer to the Measurement & Automation
Explorer Help for information about installing software on
the controller.

Software error—The controller is in safe mode because
the SAFE MODE DIP switch is in the ON position or there
is no software installed on the controller. Refer to the DIP

Switches section for information about the SAFE MODE

DIP switch.

Software error—The software has crashed twice without
rebooting or cycling power between crashes. This usually
occurs when the controller runs out of memory. Review
your RT VI and check the memory usage. Modify the VI
as necessary to solve the memory usage issue.

Software error—The controller has detected an
unrecoverable error. Contact National Instruments.

Software error—The device may be configured for DHCP
but unable to get an IP address because of a problem with
the DHCP server. Check the network connection and try
again. If the problem persists, contact National
Instruments.

© National Instruments | 1-31

Chapter 1 Getting Started with the cDAQ Controller

Table 1-8. LED Indications (Continued)

LED

STATUS Red Continuously

USER1 Green/

LED

Color LED State Indication

flashing

Solid Hardware error—The cDAQ controller internal

— Off Normal operation.

— This LED is controlled directly from your LabVIEW RT

yellow

Hardware error—An internal power supply has failed.
Check front-panel I/O, CXM, and C Series module
connections for shorts. Remove any shorts and power
cycle the controller. If the problem persists, contact
National Instruments.

temperature has exceeded a critical threshold. Ensure that
the ambient operating temperature does not exceed the
range specified in the Environmental section of the
specifications document for your cDAQ controller. If the
problem persists, contact National Instruments.

application You can define the USER1 LED to meet the
needs of your application. To define the LED, use the RT
LEDs VI in LabVIEW. For more information about the RT
LEDs VI, refer to the LabVIEW Help.

CMOS Battery and CMOS Reset Button

The cDAQ controller contains a CMOS battery, a lithium cell battery that stores the system
clock information when the controller is powered off. There is only a slight drain on the CMOS
battery when power is applied to the cDAQ controller power connector. The rate at which the
CMOS battery drains when power is disconnected depends on the ambient storage temperature.
For longer battery life, store the cDAQ controller at a cooler temperature. Refer to the CMOS
Battery section of the specifications document for your cDAQ controller for the expected battery
lifetime.

CMOS Battery Is Dead warning appears onscreen during the power-on self test if the

The
battery is dead. The controller still starts, but the system clock is reset to the date and time of the
BIOS release. The battery is not user replaceable. If you need to replace the CMOS battery,
contact National Instruments.

Resetting the System CMOS and BIOS Settings

The cDAQ controller BIOS configuration information is stored in a nonvolatile memory
location that does not require a battery to preserve the settings. Additionally, the BIOS optimizes
boot time by saving specific system information to memory backed up by a battery (CMOS).

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NI cDAQ-9138/9139 User Manual

Complete the following steps to reset the CMOS and reset the BIOS settings to factory default
values:

1. Disconnect power from the cDAQ controller.

2. Press the CMOS reset button, shown in Figure 1-1, NI cDAQ-9138/9139 Controller, and

hold it for 1 second.

3. Reconnect power to the cDAQ controller.

The

BIOS Reset Detected warning message appears onscreen.

If the CMOS battery is dead, the CMOS reset button does not work. You must complete the
following alternative steps to reset the CMOS and reset the BIOS settings to factory default
values:

1. Disconnect power from the cDAQ controller.

2. Configure the front-panel DIP switches as shown in Table 1-9.

Table 1-9. DIP Switch Settings to Reset CMOS and BIOS Settings

Configuration Switch Position

DISABLE RT ON

DISABLE RT
SAFE MODE
CONSOLE OUT
IP RESET
NO APP
USER1

ON OFF

SAFE MODE ON

CONSOLE OUT OFF

IP RESET OFF

NO APP ON

USER1 ON

Note These DIP switch settings are only applicable when the CMOS battery is

dead.

3. Reconnect power to the cDAQ controller. The BIOS Reset Detected warning message

appears onscreen.

4. Reset the DIP switches to their normal positions.

Chassis Grounding Screw

For EMC compliance, the cDAQ controller must be connected to earth ground through the
controller ground, shown in Figure 1-1.

2

The wire should be 1.31 mm
(5 ft). Attach the wire to the earth ground of the facility’s power system. For more information
about earth ground connections, refer to the KnowledgeBase document, Grounding for Test and
Measurement Devices, by going to

(16 AWG) solid copper wire with a maximum length of 1.5 m

ni.com/info and entering the Info Code emcground.

© National Instruments | 1-33

Chapter 1 Getting Started with the cDAQ Controller

Note If you use shielded cabling to connect to a C Series module with a plastic

connector, you must attach the cable shield to the chassis grounding terminal using

2

1.31 mm

(16 AWG) or larger wire. Use shorter wire for better EMC performance.

CPU eXpansion Module (CXM) Connector

In the future, the CXM connector will enable you to connect additional industry-standard I/O to
the cDAQ controller.

CFast SSD Module

The CFast SSD module is the solid state hard drive of the cDAQ controller.

Cables and Accessories

Table 1-10 contains information about cables and accessories available for the cDAQ controller.
For a complete list of cDAQ controller accessories and ordering information, refer to the pricing
section of the NI cDAQ-913x product page at ni.com.

Table 1-10. Cables and Accessories

Accessory Part Number

NI PS-15 power supply (24 VDC, 5 A, 100-120/200-240 VAC input) 781093-01

NI PS-10 desktop DC power supply
(24 VDC, 5 A, 100-120/200-240 VAC input)

NI desktop mount kit 781988-01

NI panel mount kit 781919-01

782698-01

NI DIN rail mount kit 781987-01

NI rack mount kit with DIN rail 781989-01

NI 9910 sliding rack mount kit with DIN rail 779102-01

CAT-5E Ethernet cable, shielded (2, 5, and 10 m lengths) 151733-02, 151733-05,

151733-10

Industrial USB extension with retention cable (0.5 and 2 m lengths) 152166-xx

DIN rail-mountable screw terminal adapter
(COM 2 termination resistor connection)

Cable adapters for 10-position modular jacks (1, 2, and 3 m lengths) 182845-01, 182845-02,

MXI-Express cables (1, 3, and 7 m lengths) 779500-01, 779500-03,

1-34 | ni.com

778674-01

182845-03

779500-07

NI cDAQ-9138/9139 User Manual

C Series

I/O Module

C Series

I/O Module

cDAQ Module

Interface

STC3

Processor

RS-232

RS-485/422

MXI Express

USB

VGA

Ethernet

Table 1-10. Cables and Accessories (Continued)

Accessory Part Number

Keyboard and mouse 779660-01

USB CD/DVD drive 778492-01

Flat panel touch screen 779560-01

Flat panel monitors 779559-01, 781002-01

Caution To ensure the specified EMC performance, operate this product only with

shielded cables and accessories.

Go to

ni.com/info and enter Info Code exswh5 for up-to-date information about supported

NI devices for the cDAQ controller.

Using the cDAQ Controller

The cDAQ controller consists of four parts—C Series module(s), the cDAQ module interface,
the STC3, and the processor board—as shown in Figure 1-21. These components digitize
signals, perform D/A conversions to generate analog output signals, measure and control digital
I/O signals, and provide signal conditioning.

Figure 1-21. Block Diagram

C Series Module

National Instruments C Series modules provide built-in signal conditioning and screw terminal,
spring terminal, BNC, D-SUB, or RJ-50 connectors. A wide variety of I/O types are available,
allowing you to customize the cDAQ controller to meet your application needs.

C Series modules are hot-swappable and automatically detected by the cDAQ controller.
I/O channels are accessible using the NI-DAQmx driver software.

Because the modules contain built-in signal conditioning for extended voltage ranges or
industrial signal types, you can usually make your wiring connections directly from the C Series

© National Instruments | 1-35

Chapter 1 Getting Started with the cDAQ Controller

modules to your sensors/actuators. C Series modules can sometimes provide isolation from
channel-to-earth ground and channel-to-channel.

For more information about which C Series modules are compatible with the cDAQ controller,
refer to the C Series Support in NI-DAQmx document by going to
the Info Code rdcdaq.

ni.com/info and entering

Parallel versus Serial DIO Modules

Digital I/O module capabilities are determined by the type of digital signals that the module is
capable of measuring or generating.

• Serial digital I/O modules are designed for signals that change slowly and are accessed by
either software-timed or hardware-timed reads and writes.

• Parallel digital I/O modules are for signals that change rapidly and are updated by either
software-timed or hardware-timed reads and writes.

For more information about digital I/O modules, refer to Chapter 4, Digital Input/Output

and PFI.

cDAQ Module Interface

The cDAQ module interface manages data transfers between the STC3 and the C Series
I/O modules. The interface also handles autodetection, signal routing, and synchronization.

STC3

The STC3 features independent high-speed data streams; flexible AI, AO, and DIO sample
timing; triggering; PFI signals for multi-device synchronization; flexible counter/timers with
hardware gating; digital waveform acquisition and generation; and static DIO.

• AI, AO, and DIO Sample Timing—The STC3 contains advanced AI, AO, and DIO

timing engines. A wide range of timing and synchronization signals are available through
the PFI lines. Refer to the following sections for more information about the configuration
of these signals:

– The Analog Input Timing Signals section of Chapter 2, Analog Input
– The Analog Output Timing Signals section of Chapter 3, Analog Output
– The Digital Input Timing Signals section of Chapter 4, Digital Input/Output and PFI
– The Digital Output Timing Signals section of Chapter 4, Digital Input/Output and PFI

• Triggering Modes—The cDAQ controller supports different trigger modes, such as start

trigger, reference trigger, and pause trigger with analog, digital, or software sources. Refer
to the following sections for more information:

– The Analog Input Triggering Signals section of Chapter 2, Analog Input
– The Analog Output Triggering Signals section of Chapter 3, Analog Output

1-36 | ni.com

NI cDAQ-9138/9139 User Manual

– The Digital Input Triggering Signals section of Chapter 4, Digital Input/Output

and PFI

– The Digital Output Triggering Signals section of Chapter 4, Digital Input/Output

and PFI

• Independent Data Streams—The cDAQ controller supports seven independent

high-speed data streams, which allow for up to seven simultaneous hardware-timed tasks,
such as analog input, analog output, buffered counter/timers, and hardware-timed digital
input/output.

• PFI Signals—The PFI signals provide access to advanced features such as triggering,

synchronization, and counter/timers. You can also enable a programmable debouncing
filter on each PFI signal that, when enabled, samples the input on each rising edge of a filter
clock. PFI signals are available through parallel digital input and output modules installed
in up to two controller slots. Refer to the PFI section of Chapter 4, Digital Input/Output

and PFI, for more information.

• Flexible Counter/Timers—The cDAQ controller includes four general-purpose 32-bit

counter/timers that can be used to count edges, measure pulse-widths, measure periods and
frequencies, and perform position measurements (encoding). In addition, the
counter/timers can generate pulses, pulse trains, and square waves with adjustable
frequencies. You can access the counter inputs and outputs using parallel digital I/O
modules installed in up to two slots. Refer to Chapter 5, Counters, for more information.

Processor and Ports

Refer to the specifications document for your cDAQ controller for information about the
processors on the cDAQ controller. Refer to the cDAQ Controller Features section for
information about using the various ports on the cDAQ controller.

© National Instruments | 1-37

2

Analog Input

To perform analog input measurements, insert a supported analog input C Series module into
any slot on the cDAQ controller. The measurement specifications, such as number of channels,
channel configuration, sample rate, and gain, are determined by the type of C Series module
used. For more information and wiring diagrams, refer to the documentation included with your
C Series modules.

The cDAQ controller has three AI timing engines, which means that three analog input tasks can
be running at a time on a controller. An analog input task can include channels from multiple
analog input modules. However, channels from a single module cannot be used in multiple tasks.

Multiple timing engines allow the cDAQ controller to run up to three analog input tasks
simultaneously, each using independent timing and triggering configurations. The three AI
timing engines are ai, te0, and te1.

Analog Input Triggering Signals

A trigger is a signal that causes an action, such as starting or stopping the acquisition of data.
When you configure a trigger, you must decide how you want to produce the trigger and the
action you want the trigger to cause. The cDAQ controller supports internal software triggering,
external digital triggering, and analog triggering.

Three triggers are available: Start Trigger, Reference Trigger, and Pause Trigger. An analog or
digital trigger can initiate these three trigger actions. Up to two C Series parallel digital input
modules can be used in any controller slot to supply a digital trigger. To find your module
triggering options, refer to the documentation included with your C Series modules. For more
information about using digital modules for triggering, refer to Chapter 4, Digital Input/Output

and PFI.

Refer to the AI Start Trigger Signal, AI Reference Trigger Signal, and AI Pause Trigger Signal
sections for more information about the analog input trigger signals.

Analog Input Timing Signals

The cDAQ controller features the following analog input timing signals:

• AI Sample Clock Signal*

• AI Sample Clock Timebase Signal

• AI Start Trigger Signal*

© National Instruments | 2-1

NI cDAQ-9138/9139 User Manual

k

• AI Reference Trigger Signal*

• AI Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital

Input/Output and PFI, for more information.

Refer to the AI Convert Clock Signal Behavior For Analog Input Modules section for AI Convert
Clock signals and the cDAQ controller.

AI Sample Clock Signal

A sample consists of one reading from each channel in the AI task. Sample Clock signals the
start of a sample of all analog input channels in the task. Sample Clock can be generated from
external or internal sources as shown in Figure 2-1.

Figure 2-1. AI Sample Clock Timing Options

PFI

Analog Comparison Event

PFI

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

100 kHz Timebase

Ctr n Internal Output

Sigma-Delta Module Internal Output

AI Sample Clock

Timebase

Programmable

Clock

Divider

AI Sample Cloc

Routing the Sample Clock to an Output Terminal

You can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulse
by default.

AI Sample Clock Timebase Signal

The AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.
AI Sample Clock Timebase can be generated from external or internal sources. AI Sample Clock
Timebase is not available as an output from the controller.

AI Convert Clock Signal Behavior For Analog Input Modules

Refer to the Scanned Modules, Simultaneous Sample-and-Hold Modules, Sigma-Delta Modules,
and Slow Sample Rate Modules sections for information about the AI Convert Clock signal and
C Series analog input modules.

© National Instruments | 2-2

Chapter 2 Analog Input

Scanned Modules

Scanned C Series analog input modules contain a single A/D converter and a multiplexer to
select between multiple input channels. When the cDAQ Module Interface receives a Sample
Clock pulse, it begins generating a Convert Clock for each scanned module in the current task.
Each Convert Clock signals the acquisition of a single channel from that module. The Convert
Clock rate depends on the module being used, the number of channels used on that module, and
the system Sample Clock rate.

The driver chooses the fastest conversion rate possible based on the speed of the A/D converter
for each module and adds 10 µs of padding between each channel to allow for adequate settling
time. This scheme enables the channels to approximate simultaneous sampling. If the AI Sample
Clock rate is too fast to allow for 10 µs of padding, NI-DAQmx selects a conversion rate that
spaces the AI Convert Clock pulses evenly throughout the sample. NI-DAQmx uses the same
amount of padding for all the modules in the task. To explicitly specify the conversion rate, use

the ActiveDevs and AI Convert Clock Rate properties using the DAQmx Timing property

node or functions.

Simultaneous Sample-and-Hold Modules

Simultaneous sample-and-hold (SSH) C Series analog input modules contain multiple A/D
converters or circuitry that allows all the input channels to be sampled at the same time. These
modules sample their inputs on every Sample Clock pulse.

Sigma-Delta Modules

Sigma-delta C Series analog input modules function much like SSH modules, but use A/D
converters that require a high-frequency oversample clock to produce accurate, synchronized
data. Some sigma-delta modules in the cDAQ controller automatically share a single oversample
clock to synchronize data from all the modules that support an external oversample clock
timebase when they all share the same task. (DSA modules are an example). The cDAQ
controller supports a maximum of two synchronization pulse signals configured for your system.
This limits the system to two tasks with different oversample clock timebases.

The oversample clock is used as the AI Sample Clock Timebase. While most modules supply a
common oversample clock frequency (12.8 MHz), some modules, such as the NI 9234, supply
a different frequency. When sigma-delta modules with different oversample clock frequencies
are used in an analog input task, the AI Sample Clock Timebase can use any of the available
frequencies; by default, the fastest available is used. The sampling rate of all modules in the
system is an integer divisor of the frequency of the AI Sample Clock Timebase.

When one or more sigma-delta modules are in an analog input task, the sigma-delta modules also
provide the signal used as the AI Sample Clock. This signal is used to cause A/D conversion for
other modules in the system, just as the AI Sample Clock does when a sigma-delta module is not
being used.

When sigma-delta modules are in an AI task, the controller automatically issues a
synchronization pulse to each sigma-delta modules that resets their ADCs at the same time.

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NI cDAQ-9138/9139 User Manual

Because of the filtering used in sigma-delta A/D converters, these modules usually exhibit a
fixed input delay relative to non-sigma-delta modules in the system. This input delay is specified
in the C Series module documentation.

Slow Sample Rate Modules

Some C Series analog input modules are specifically designed for measuring signals that vary
slowly, such as temperature. Because of their slow rate, it is not appropriate for these modules
to constrain the AI Sample Clock to operate at or slower than their maximum rate. When using
such a module in the cDAQ controller, the maximum Sample Clock rate can run faster than the
maximum rate for the module. When operating at a rate faster than these slow rate modules can
support, the slow rate module returns the same point repeatedly, until a new conversion
completes. In a hardware-timed task, the first point is acquired when the task is committed. The
second point is acquired after the start trigger as shown in Figure 2-2.

Figure 2-2. Sample Clock Timing Example

StartTrigger

1st A/D Conversion 2nd A/D Conversion 3rd A/D Conversion

Data from

A/D Conversion

(Slow Module)

SampleClock

A

BC

Data Returned

to AI Task

AA ABB BC

For example, if running an AI task at 1 kHz using a module with a maximum rate of 10 Hz, the
slow module returns 100 samples of the first point, followed by 100 samples of the second point,
etc. Other modules in the task will return 1,000 new data points per second, which is normal.
When performing a single-point acquisition, no points are repeated. To avoid this behavior, use
multiple AI timing engines, and assign slow sample rate modules to a task with a rate at or slower
than their maximum rate.

Refer to the C Series Support in NI-DAQmx document by going to
the Info Code

rdcdaq.

ni.com/info and entering

AI Start Trigger Signal

Use the Start Trigger signal to begin a measurement acquisition. A measurement acquisition
consists of one or more samples. If you do not use triggers, begin a measurement with a software
command. Once the acquisition begins, configure the acquisition to stop in one of the following
ways:

• When a certain number of points has been sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

© National Instruments | 2-4

Chapter 2 Analog Input

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a
posttriggered acquisition. That is, samples are measured only after the trigger.

When you are using an internal sample clock, you can specify a default delay from the start
trigger to the first sample.

Using a Digital Source

To use the Start Trigger signal with a digital source, specify a source and a rising or falling edge.
Use the following signals as the source:

• Any PFI terminal

• Counter n Internal Output

The source also can be one of several other internal signals on your cDAQ controller. Refer to
the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event. When you use an analog trigger source for Start Trigger,
the acquisition begins on the first rising edge of the Analog Comparison Event signal.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing AI Start Trigger to an Output Terminal

You can route the Start Trigger signal to any output PFI terminal. The output is an active high
pulse.

AI Reference Trigger Signal

Use Reference Trigger to stop a measurement acquisition. To use a reference trigger, specify a
buffer of finite size and a number of pretrigger samples (samples that occur before the reference
trigger). The number of posttrigger samples (samples that occur after the reference trigger)
desired is the buffer size minus the number of pretrigger samples.

Once the acquisition begins, the cDAQ controller writes samples to the buffer. After the cDAQ
controller captures the specified number of pretrigger samples, the cDAQ controller begins to
look for the reference trigger condition. If the reference trigger condition occurs before the
cDAQ controller captures the specified number of pretrigger samples, the controller ignores the
condition.

If the buffer becomes full, the cDAQ controller continuously discards the oldest samples in the
buffer to make space for the next sample. This data can be accessed (with some limitations)
before the cDAQ controller discards it. Refer to the KnowledgeBase document, Can a

2-5 | ni.com

NI cDAQ-9138/9139 User Manual

Pretriggered Acqu isition be Continuous?, for more information. To access this KnowledgeBase,

ni.com/info and enter the Info Code rdcanq.

go to

When the reference trigger occurs, the cDAQ controller continues to write samples to the buffer
until the buffer contains the number of posttrigger samples desired. Figure 2-3 shows the final
buffer.

Figure 2-3. Reference Trigger Final Buffer

Reference Trigger

Pretrigger Samples

Complete Buffer

Posttrigger Samples

Using a Digital Source

To use Reference Trigger with a digital source, specify a source and a rising or falling edge.
Either PFI or one of several internal signals on the cDAQ controller can provide the source.
Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event.

When you use an analog trigger source, the acquisition stops on the first rising or falling edge of
the Analog Comparison Event signal, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing the Reference Trigger Signal to an Output Terminal

You can route Reference Trigger to any output PFI terminal. Reference Trigger is active high by
default.

© National Instruments | 2-6

Chapter 2 Analog Input

AI Pause Trigger Signal

You can use the Pause Trigger to pause and resume a measurement acquisition. The internal
sample clock pauses while the external trigger signal is active and resumes when the signal is
inactive. You can program the active level of the pause trigger to be high or low.

Using a Digital Source

To use the Pause Trigger, specify a source and a polarity. The source can be either from PFI or
one of several other internal signals on your cDAQ controller. Refer to the Device Routing in
MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event.

When you use an analog trigger source, the internal sample clock pauses when the Analog
Comparison Event signal is low and resumes when the signal goes high (or vice versa).

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Getting Started with AI Applications in Software

You can use the cDAQ controller in the following analog input applications:

• Single-point acquisition

• Finite acquisition

• Continuous acquisition

For more information about programming analog input applications and triggers in software,
refer to the NI-DAQmx Help or the LabVIEW Help for more information.

2-7 | ni.com

3

Analog Output

To generate analog output, insert an analog output C Series module in any slot on the cDAQ
controller. The generation specifications, such as the number of channels, channel configuration,
update rate, and output range, are determined by the type of C Series module used. For more
information, refer to the documentation included with your C Series module(s).

On a single analog output C Series module, you can assign any number of channels to either a
hardware-timed task or a software-timed (single-point) task. However, you cannot assign some
channels to a hardware-timed task and other channels (on the same module) to a software-timed
task.

Any hardware-timed task or software-timed task can have channels from multiple modules in
the same controller.

Analog Output Data Generation Methods

When performing an analog output operation, you either can perform software-timed or
hardware-timed generations. Hardware-timed generations must be buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software
sends a separate command to the hardware to initiate each DAC conversion. In NI-DAQmx,
software-timed generations are referred to as on-demand timing. Software-timed generations are
also referred to as immediate or static operations. They are typically used for writing out a single
value, such as a constant DC voltage.

The following considerations apply to software-timed generations:

• If any AO channel on a module is used in a hardware-timed (waveform) task, no channels
on that module can be used in a software-timed task

• You can configure software-timed generations to simultaneously update

• Only one simultaneous update task can run at a time

• A hardware-timed AO task and a simultaneous update AO task cannot run at the same time

© National Instruments | 3-1

Chapter 3 Analog Output

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation.
This signal can be generated internally on the controller or provided externally.

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter

• The timing between samples is deterministic

• Hardware-timed acquisitions can use hardware triggering

Hardware-timed AO operations on the cDAQ controller must be buffered.

Buffered Analog Output

A buffer is a temporary storage in computer memory for generated samples. In a buffered
generation, data is moved from a host buffer to the cDAQ controller onboard FIFO before it is
written to the C Series modules.

One property of buffered I/O operations is sample mode. The sample mode can be either finite
or continuous:

• Finite—Finite sample mode generation refers to the generation of a specific,

predetermined number of data samples. After the specified number of samples is written
out, the generation stops.

• Continuous—Continuous generation refers to the generation of an unspecified number of

samples. Instead of generating a set number of data samples and stopping, a continuous
generation continues until you stop the operation. There are three different continuous
generation modes that control how the data is written. These modes are regeneration,
onboard regeneration, and non-regeneration:

– In regeneration mode, you define a buffer in host memory. The data from the buffer is

continually downloaded to the FIFO to be written out. New data can be written to the
host buffer at any time without disrupting the output. There is no limitation on the
number of waveform channels supported by regeneration mode.

– With onboard regeneration, the entire buffer is downloaded to the FIFO and

regenerated from there. After the data is downloaded, new data cannot be written to
the FIFO. To use onboard regeneration, the entire buffer must fit within the FIFO size.
The advantage of using onboard regeneration is that it does not require communication
with the main host memory once the operation is started, which prevents problems that
may occur due to excessive bus traffic or operating system latency. There is a limit of
16 waveform channels for onboard regeneration.

– With non-regeneration, old data is not repeated. New data must continually be written

to the buffer. If the program does not write new data to the buffer at a fast enough rate
to keep up with the generation, the buffer underflows and causes an error. There is no
limitation on the number of waveform channels supported by non-regeneration.

3-2 | ni.com

NI cDAQ-9138/9139 User Manual

Programmable

Clock

Divider

AO Sample Clock

Timebase

PFI

Analog Comparison Event

Ctr

n

Internal Output

AO Sample Clock

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

PFI

100 kHz Timebase

Analog Output Triggering Signals

Analog output supports two different triggering actions: AO Start Trigger and AO Pause
Trigger.

An analog or digital trigger can initiate these actions. Up to two C Series parallel digital input
modules can be used in any controller slot to supply a digital trigger. An analog trigger can be
supplied by some C Series analog modules.

Refer to the AO Start Trigger Signal and AO Pause Trigger Signal sections for more information
about the analog output trigger signals.

Analog Output Timing Signals

The cDAQ controller features the following AO (waveform generation) timing signals:

• AO Sample Clock Signal*

• AO Sample Clock Timebase Signal

• AO Start Trigger Signal*

• AO Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, Digital

Input/Output and PFI, for more information.

AO Sample Clock Signal

The AO sample clock (ao/SampleClock) signals when all the analog output channels in the task
update. AO Sample Clock can be generated from external or internal sources as shown in
Figure 3-1.

Figure 3-1. Analog Output Timing Options

© National Instruments | 3-3

Chapter 3 Analog Output

Routing AO Sample Clock to an Output Terminal

You can route AO Sample Clock to any output PFI terminal. AO Sample Clock is active high
by default.

AO Sample Clock Timebase Signal

The AO Sample Clock Timebase (ao/SampleClockTimebase) signal is divided down to provide
a source for AO Sample Clock. AO Sample Clock Timebase can be generated from external or
internal sources, and is not available as an output from the controller.

AO Start Trigger Signal

Use the AO Start Trigger (ao/StartTrigger) signal to initiate a waveform generation. If you do
not use triggers, you can begin a generation with a software command. If you are using an
internal sample clock, you can specify a delay from the start trigger to the first sample. For more
information, refer to the NI-DAQmx Help.

Using a Digital Source

To use AO Start Trigger, specify a source and a rising or falling edge. The source can be one of
the following signals:

• A pulse initiated by host software

• Any PFI terminal

• AI Reference Trigger

• AI Start Trigger

The source also can be one of several internal signals on the cDAQ controller. Refer to the
Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

You also can specify whether the waveform generation begins on the rising edge or falling edge
of AO Start Trigger.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event, depending on the trigger properties.

When you use an analog trigger source, the waveform generation begins on the first rising or
falling edge of the Analog Comparison Event signal, depending on the trigger properties. The
analog trigger circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

3-4 | ni.com

NI cDAQ-9138/9139 User Manual

Pause Trigger

Sample Clock

Routing AO Start Trigger Signal to an Output Terminal

You can route AO Start Trigger to any output PFI terminal. The output is an active high pulse.

AO Pause Trigger Signal

Use the AO Pause Trigger signal (ao/PauseTrigger) to mask off samples in a DAQ sequence.
When AO Pause Trigger is active, no samples occur, but AO Pause Trigger does not stop a
sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate analog output signals, the generation pauses as soon as the pause trigger is
asserted. If the source of the sample clock is the onboard clock, the generation resumes as soon
as the pause trigger is deasserted, as shown in Figure 3-2.

Figure 3-2. AO Pause Trigger with the Onboard Clock Source

Pause Trigger

Sample Clock

If you are using any signal other than the onboard clock as the source of the sample clock, the
generation resumes as soon as the pause trigger is deasserted and another edge of the sample
clock is received, as shown in Figure 3-3.

Figure 3-3. AO Pause Trigger with Other Signal Source

Using a Digital Source

To use AO Pause Trigger, specify a source and a polarity. The source can be a PFI signal or one
of several other internal signals on the cDAQ controller.

You also can specify whether the samples are paused when AO Pause Trigger is at a logic high
or low level. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW
Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event, depending on the trigger properties.

© National Instruments | 3-5

Chapter 3 Analog Output

When you use an analog trigger source, the samples are paused when the Analog Comparison
Event signal is at a high or low level, depending on the trigger properties. The analog trigger
circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Minimizing Glitches on the Output Signal

When you use a DAC to generate a waveform, you may observe glitches on the output signal.
These glitches are normal; when a DAC switches from one voltage to another, it produces
glitches due to released charges. The largest glitches occur when the most significant bit of the
DAC code changes. You can build a lowpass deglitching filter to remove some of these glitches,
depending on the frequency and nature of the output signal. Go to
information about minimizing glitches.

ni.com/support for more

Getting Started with AO Applications in Software

You can use the cDAQ controller in the following analog output applications:

• Single-point (on-demand) generation

• Finite generation

• Continuous generation

• Waveform generation

For more information about programming analog output applications and triggers in software,
refer the LabVIEW Help or to the NI-DAQmx Help.

3-6 | ni.com

4

Digital Input/Output and PFI

This chapter describes the digital input/output (DIO) and Programmable Function Interface
(PFI) functionality available on the cDAQ controller. Refer to the Digital Input/Output and PFI
sections.

Digital Input/Output

To use digital I/O, insert a digital I/O C Series module into any slot on the cDAQ controller. The
I/O specifications, such as number of lines, logic levels, update rate, and line direction, are
determined by the type of C Series module used. For more information, refer to the
documentation included with your C Series module(s).

Serial DIO versus Parallel DIO Modules

Serial digital I/O modules have more than eight lines of digital input/output. They can be used
in any controller slot and can perform the following tasks:

• Software-timed and hardware-timed digital input/output tasks

Parallel digital I/O modules can be used in any controller slot and can perform the following
tasks:

• Software-timed and hardware-timed digital input/output tasks

• Counter/timer tasks (can be used in up to two slots)

• Accessing PFI signal tasks (can be used in up to two slots)

• Filter digital input signals

Software-timed and hardware-timed digital input/output tasks have the following restrictions:

• You cannot use parallel and serial modules together on the same hardware-timed task.

• You cannot use serial modules for triggering.

• You cannot do both static and timed tasks at the same time on a single serial module.

• You can only do hardware timing in one direction at a time on a serial bidirectional module.

To determine the capability of digital I/O modules supported by the cDAQ controller, refer to
the C Series Support in NI-DAQmx document by going to
Code rdcdaq.

ni.com/info and entering the Info

© National Instruments | 4-1

Chapter 4 Digital Input/Output and PFI

Static DIO

Each of the DIO lines can be used as a static DI or DO line. You can use static DIO lines to
monitor or control digital signals on some C Series modules. Each DIO line can be individually
configured as a digital input (DI) or digital output (DO), if the C Series module being used
allows such configuration.

All samples of static DI lines and updates of static DO lines are software-timed.

Digital Input

You can acquire digital waveforms using either parallel or serial digital modules.
The DI waveform acquisition FIFO stores the digital samples. The cDAQ controller samples the
DIO lines on each rising or falling edge of the DI Sample Clock signal.

Digital Input Triggering Signals

A trigger is a signal that causes an action, such as starting or stopping the acquisition of data.
When you configure a trigger, you must decide how you want to produce the trigger and the
action you want the trigger to cause. The cDAQ controller supports three types of digital
triggering: internal software digital triggering, external digital triggering, and internal digital
triggering.

Three triggers are available: Start Trigger, Reference Trigger, and Pause Trigger. An analog or
digital trigger can initiate these three trigger actions. Up to two C Series parallel digital input
modules can be used in any controller slot to supply a digital trigger. To find your module
triggering options, refer to the documentation included with your C Series modules. For more
information about using analog modules for triggering, refer to the Analog Input Triggering

Signals section of Chapter 2, Analog Input, and the Analog Output Triggering Signals section of

Chapter 3, Analog Output.

Refer to the DI Start Trigger Signal, DI Reference Trigger Signal, and DI Pause Trigger Signal
sections for more information about the digital input trigger signals.

Digital Input Timing Signals

The cDAQ controller features the following digital input timing signals:

• DI Sample Clock Signal*

• DI Sample Clock Timebase Signal

• DI Start Trigger Signal*

• DI Reference Trigger Signal*

• DI Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section for more information.

4-2 | ni.com

NI cDAQ-9138/9139 User Manual

Programmable

Clock

Divider

DI Sample Clock

Timebase

PFI

Analog Comparison Event

Ctr

n

Internal Output

DI Sample Clock

Sigma-Delta Module Internal Output

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

PFI

100 kHz Timebase

DI Sample Clock Signal

Use the DI Sample Clock (di/SampleClock) signal to sample digital I/O on any slot using
parallel digital modules, and store the result in the DI waveform acquisition FIFO. If the cDAQ
controller receives a DI Sample Clock signal when the FIFO is full, it reports an overflow error
to the host software.

A sample consists of one reading from each channel in the DI task. DI Sample Clock signals the
start of a sample of all digital input channels in the task. DI Sample Clock can be generated from
external or internal sources as shown in Figure 4-1.

Figure 4-1. DI Sample Clock Timing Options

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal.

DI Sample Clock Timebase Signal

The DI Sample Clock Timebase (di/SampleClockTimebase) signal is divided down to provide
a source for DI Sample Clock. DI Sample Clock Timebase can be generated from external or
internal sources. DI Sample Clock Timebase is not available as an output from the controller.

Using an Internal Source

To use DI Sample Clock with an internal source, specify the signal source and the polarity of the
signal. Use the following signals as the source:

• AI Sample Clock

• AO Sample Clock

• Counter n Internal Output

• Frequency Output

• DI Change Detection Output

Several other internal signals can be routed to DI Sample Clock. Refer to the Device Routing in
MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

© National Instruments | 4-3

Chapter 4 Digital Input/Output and PFI

Using an External Source

You can route the following signals as DI Sample Clock:

• Any PFI terminal

• Analog Comparison Event (an analog trigger)

You can sample data on the rising or falling edge of DI Sample Clock.

Routing DI Sample Clock to an Output Terminal

You can route DI Sample Clock to any output PFI terminal. The PFI circuitry inverts the polarity
of DI Sample Clock before driving the PFI terminal.

DI Start Trigger Signal

Use the DI Start Trigger (di/StartTrigger) signal to begin a measurement acquisition. A
measurement acquisition consists of one or more samples. If you do not use triggers, begin a
measurement with a software command. Once the acquisition begins, configure the acquisition
to stop in one of the following ways:

• When a certain number of points has been sampled (in finite mode)

• After a hardware reference trigger (in finite mode)

• With a software command (in continuous mode)

An acquisition that uses a start trigger (but not a reference trigger) is sometimes referred to as a
posttriggered acquisition. That is, samples are measured only after the trigger.

When you are using an internal sample clock, you can specify a delay from the start trigger to
the first sample.

Using a Digital Source

To use DI Start Trigger with a digital source, specify a source and a rising or falling edge. Use
the following signals as the source:

• Any PFI terminal

• Counter n Internal Output

The source also can be one of several other internal signals on the cDAQ controller. Refer to the
Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event. When you use an analog trigger source for DI Start
Trigger, the acquisition begins on the first rising edge of the Analog Comparison Event signal.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

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NI cDAQ-9138/9139 User Manual

Routing DI Start Trigger to an Output Terminal

You can route DI Start Trigger to any output PFI terminal. The output is an active high pulse.

DI Reference Trigger Signal

Use a reference trigger (di/ReferenceTrigger) signal to stop a measurement acquisition. To use
a reference trigger, specify a buffer of finite size and a number of pretrigger samples (samples
that occur before the reference trigger). The number of posttrigger samples (samples that occur
after the reference trigger) desired is the buffer size minus the number of pretrigger samples.

Once the acquisition begins, the cDAQ controller writes samples to the buffer. After the cDAQ
controller captures the specified number of pretrigger samples, the controller begins to look for
the reference trigger condition. If the reference trigger condition occurs before the cDAQ
controller captures the specified number of pretrigger samples, the controller ignores the
condition.

If the buffer becomes full, the cDAQ controller continuously discards the oldest samples in the
buffer to make space for the next sample. This data can be accessed (with some limitations)
before the cDAQ controller discards it. Refer to the KnowledgeBase document, Can a
Pretriggered Acqu isition be Continuous?, for more information. To access this KnowledgeBase,

ni.com/info and enter the Info Code rdcanq.

go to

When the reference trigger occurs, the cDAQ controller continues to write samples to the buffer
until the buffer contains the number of posttrigger samples desired. Figure 4-2 shows the final
buffer.

Figure 4-2. Reference Trigger Final Buffer

Reference Trigger

Pretrigger Samples

Complete Buffer

Posttrigger Samples

Using a Digital Source

To use DI Reference Trigger with a digital source, specify a source and a rising or falling edge.
Either PFI or one of several internal signals on the cDAQ controller can provide the source.
Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event.

© National Instruments | 4-5

Chapter 4 Digital Input/Output and PFI

When you use an analog trigger source, the acquisition stops on the first rising or falling edge of
the Analog Comparison Event signal, depending on the trigger properties.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing DI Reference Trigger Signal to an Output Terminal

You can route DI Reference Trigger to any output PFI terminal. Reference Trigger is active high
by default.

DI Pause Trigger Signal

You can use the DI Pause Trigger (di/PauseTrigger) signal to pause and resume a measurement
acquisition. The internal sample clock pauses while the external trigger signal is active and
resumes when the signal is inactive. You can program the active level of the pause trigger to be
high or low.

Using a Digital Source

To use DI Pause Trigger, specify a source and a polarity. The source can be either from PFI or
one of several other internal signals on your cDAQ controller. Refer to the Device Routing in
MAX topic in the NI-DAQmx Help or the LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event.

When you use an analog trigger source, the internal sample clock pauses when the Analog
Comparison Event signal is low and resumes when the signal goes high (or vice versa).

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Note Pause triggers are only sensitive to the level of the source, not the edge.

Digital Input Filters

When performing a hardware timed task, you can enable a programmable debouncing filter on
the digital input lines of a parallel DIO module. All lines on a module must share the same filter
configuration. When the filter is enabled, the controller samples the inputs with a
user-configured Filter Clock derived from the controller timebase. This is used to determine
whether a pulse is propagated to the rest of the system. However, the filter also introduces jitter
onto the input signal.

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NI cDAQ-9138/9139 User Manual

In NI-DAQmx, the filter is programmed by setting the minimum pulse width, Tp

1

, that will pass

the filter, and is selectable in 25 ns increments. The appropriate Filter Clock is selected by the
driver. Pulses of length less than 1/2 Tp will be rejected, and the filtering behavior of lengths
between 1/2 Tp and 1 Tp are not defined because they depend on the phase of the Filter Clock
relative to the input signal.

Figure 4-3 shows an example of low-to-high transitions of the input signal. High-to-low
transitions work similarly.

Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the filter clock has sampled the signal high
on consecutive rising edges, the low-to-high transition is propagated to the rest of the circuit.

Figure 4-3. Filter Example

Digital Input P0.x

Filter Clock

Filtered Input

11 211 21

Getting Started with DI Applications in Software

You can use the cDAQ controller in the following digital input applications:

• Single-point acquisition

• Finite acquisition

• Continuous acquisition

For more information about programming digital input applications and triggers in software,
refer to the NI-DAQmx Help or the LabVIEW Help for more information.

Change Detection Event

The Change Detection Event is the signal generated when a change on the rising or falling edge
lines is detected by the change detection task.

Routing Change Detection Event to an Output Terminal

You can route ChangeDetectionEvent to any output PFI terminal.

Change Detection Acquisition

You can configure lines on parallel digital modules to detect rising or falling edges. When one
or more of these lines sees the edge specified for that line, the cDAQ controller samples all the
lines in the task. The rising and falling edge lines do not necessarily have to be in the task.

1

Tp is a nominal value; the accuracy of the controller timebase and I/O distortion will affect this value.

© National Instruments | 4-7

Chapter 4 Digital Input/Output and PFI

Change detection acquisitions can be buffered or nonbuffered:

• Nonbuffered Change Detection Acquisition—In a nonbuffered acquisition, data is

transferred from the cDAQ controller directly to a PC buffer.

• Buffered Change Detection Acquisition—A buffer is a temporary storage in computer

memory for acquired samples. In a buffered acquisition, data is stored in the cDAQ
controller onboard FIFO then transferred to a PC buffer. Buffered acquisitions typically
allow for much faster transfer rates than nonbuffered acquisitions because data accumulates
and is transferred in blocks, rather than one sample at a time.

Digital Output

To generate digital output, insert a digital output C Series module in any slot on the cDAQ
controller. The generation specifications, such as the number of channels, channel configuration,
update rate, and output range, are determined by the type of C Series module used. For more
information, refer to the documentation included with your C Series module(s).

With parallel digital output modules (formerly known as hardware-timed modules), you can do
multiple software-timed tasks on a single module, as well as mix hardware-timed and
software-timed digital output tasks on a single module. On serial digital output modules,
(formerly known as static digital output modules), you cannot mix hardware-timed and
software-timed tasks, but you can run multiple software-timed tasks.

You may have a hardware-timed task or a software-timed task include channels from multiple
modules, but a hardware-timed task may not include a mix of channels from both parallel and
serial modules.

Digital Output Data Generation Methods

When performing a digital output operation, you either can perform software-timed or
hardware-timed generations. Hardware-timed generations must be buffered.

Software-Timed Generations

With a software-timed generation, software controls the rate at which data is generated. Software
sends a separate command to the hardware to initiate each digital generation. In NI-DAQmx,
software-timed generations are referred to as on-demand timing. Software-timed generations are
also referred to as immediate or static operations. They are typically used for writing out a single
value.

For software-timed generations, if any DO channel on a serial digital module is used in a
hardware-timed task, no channels on that module can be used in a software-timed task.

Hardware-Timed Generations

With a hardware-timed generation, a digital hardware signal controls the rate of the generation.
This signal can be generated internally on the controller or provided externally.

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NI cDAQ-9138/9139 User Manual

Hardware-timed generations have several advantages over software-timed acquisitions:

• The time between samples can be much shorter.

• The timing between samples is deterministic.

• Hardware-timed acquisitions can use hardware triggering.

Hardware-timed DO operations on the cDAQ controller must be buffered.

Buffered Digital Output

A buffer is a temporary storage in computer memory for generated samples. In a buffered
generation, data is moved from a host buffer to the cDAQ controller onboard FIFO before it is
written to the C Series module(s).

One property of buffered I/O operations is sample mode. The sample mode can be either finite
or continuous:

• Finite—Finite sample mode generation refers to the generation of a specific,

predetermined number of data samples. After the specified number of samples is written
out, the generation stops.

• Continuous—Continuous generation refers to the generation of an unspecified number of

samples. Instead of generating a set number of data samples and stopping, a continuous
generation continues until you stop the operation. There are three different continuous
generation modes that control how the data is written. These modes are regeneration,
onboard regeneration, and non-regeneration:

– In regeneration mode, you define a buffer in host memory. The data from the buffer is

continually downloaded to the FIFO to be written out. New data can be written to the
host buffer at any time without disrupting the output.

– With onboard regeneration, the entire buffer is downloaded to the FIFO and

regenerated from there. After the data is downloaded, new data cannot be written to
the FIFO. To use onboard regeneration, the entire buffer must fit within the FIFO size.
The advantage of using onboard regeneration is that it does not require communication
with the main host memory once the operation is started, which prevents problems that
may occur due to excessive bus traffic or operating system latency.

Note Install parallel DO modules in slots 1 through 4 to maximize accessible FIFO

size because using a module in slots 5 through 8 will reduce the accessible FIFO size.

– With non-regeneration, old data is not repeated. New data must continually be written

to the buffer. If the program does not write new data to the buffer at a fast enough rate
to keep up with the generation, the buffer underflows and causes an error.

Digital Output Triggering Signals

Digital output supports two different triggering actions: DO Start Trigger and DO Pause Trigger.

© National Instruments | 4-9

Chapter 4 Digital Input/Output and PFI

A digital or analog trigger can initiate these actions. Any PFI terminal can supply a digital
trigger, and some C Series analog modules can supply an analog trigger. For more information,
refer to the documentation included with your C Series module(s).

Refer to the DO Start Trigger Signal and DO Pause Trigger Signal sections for more
information about the digital output trigger signals.

Digital Output Timing Signals

The cDAQ controller features the following DO timing signals:

• DO Sample Clock Signal*

• DO Sample Clock Timebase Signal

• DO Start Trigger Signal*

• DO Pause Trigger Signal*

Signals with an * support digital filtering. Refer to the PFI Filters section for more information.

DO Sample Clock Signal

The DO Sample Clock (do/SampleClock) signals when all the digital output channels in the task
update. DO Sample Clock can be generated from external or internal sources as shown in
Figure 4-4.

Figure 4-4. Digital Output Timing Options

PFI

PFI

Analog Comparison

Event

20 MHz Timebase

80 MHz Timebase

100 kHz Timebase

DO Sample Clock

Timebase

Analog Comparison Event

Ctr

n

Internal Output

Programmable

Clock

Divider

DO Sample Clock

Routing DO Sample Clock to an Output Terminal

You can route DO Sample Clock to any output PFI terminal. DO Sample Clock is active high
by default.

DO Sample Clock Timebase Signal

The DO Sample Clock Timebase (do/SampleClockTimebase) signal is divided down to provide
a source for DO Sample Clock. DO Sample Clock Timebase can be generated from external or
internal sources, and is not available as an output from the controller.

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NI cDAQ-9138/9139 User Manual

DO Start Trigger Signal

Use the DO Start Trigger (do/StartTrigger) signal to initiate a waveform generation. If you do
not use triggers, you can begin a generation with a software command. If you are using an
internal sample clock, you can specify a delay from the start trigger to the first sample. For more
information, refer to the NI-DAQmx Help.

Using a Digital Source

To use DO Start Trigger, specify a source and a rising or falling edge. The source can be one of
the following signals:

• A pulse initiated by host software

• Any PFI terminal

• AI Reference Trigger

• AI Start Trigger

The source also can be one of several internal signals on the cDAQ controller. Refer to the
Device Routing in MAX topic in the NI-DAQmx Help or the LabVIEW Help for more
information.

You also can specify whether the waveform generation begins on the rising edge or falling edge
of DO Start Trigger.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event, depending on the trigger properties.

When you use an analog trigger source, the waveform generation begins on the first rising or
falling edge of the Analog Comparison Event signal, depending on the trigger properties. The
analog trigger circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

Routing DO Start Trigger Signal to an Output Terminal

You can route DO Start Trigger to any output PFI terminal. The output is an active high pulse.

DO Pause Trigger Signal

Use the DO Pause Trigger signal (do/PauseTrigger) to mask off samples in a DAQ sequence.
When DO Pause Trigger is active, no samples occur, but DO Pause Trigger does not stop a
sample that is in progress. The pause does not take effect until the beginning of the next sample.

When you generate digital output signals, the generation pauses as soon as the pause trigger is
asserted. If the source of the sample clock is the onboard clock, the generation resumes as soon
as the pause trigger is deasserted, as shown in Figure 4-5.

© National Instruments | 4-11

Chapter 4 Digital Input/Output and PFI

Pause Trigger

Sample Clock

Figure 4-5. DO Pause Trigger with the Onboard Clock Source

Pause Trigger

Sample Clock

If you are using any signal other than the onboard clock as the source of the sample clock, the
generation resumes as soon as the pause trigger is deasserted and another edge of the sample
clock is received, as shown in Figure 4-6.

Figure 4-6. DO Pause Trigger with Other Signal Source

Using a Digital Source

To use DO Pause Trigger, specify a source and a polarity. The source can be a PFI signal or one
of several other internal signals on the cDAQ controller.

You also can specify whether the samples are paused when DO Pause Trigger is at a logic high
or low level. Refer to the Device Routing in MAX topic in the NI-DAQmx Help or the
LabVIEW Help for more information.

Using an Analog Source

Some C Series modules can generate a trigger based on an analog signal. In NI-DAQmx, this is
called the Analog Comparison Event, depending on the trigger properties.

When you use an analog trigger source, the samples are paused when the Analog Comparison
Event signal is at a high or low level, depending on the trigger properties. The analog trigger
circuit must be configured by a simultaneously running analog input task.

Note Depending on the C Series module capabilities, you may need two modules

to utilize analog triggering.

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NI cDAQ-9138/9139 User Manual

Getting Started with DO Applications in Software

You can use the cDAQ controller in the following digital output applications:

• Single-point (on-demand) generation

• Finite generation

• Continuous generation

For more information about programming digital output applications and triggers in software,
refer the LabVIEW Help or to the NI-DAQmx Help.

Digital Input/Output Configuration for NI 9401

When you change the configuration of lines on a NI 9401 digital I/O module between input and
output, NI-DAQmx temporarily reserves all of the lines on the module for communication to
send the module a line configuration command. For this reason, you must reserve the task in
advance through the DAQmx Control Task before any task has started. If another task or route
is actively using the module, to avoid interfering with the other task, NI-DAQmx generates an
error instead of sending the line configuration command. During the line configuration
command, the output lines are maintained without glitching.

PFI

You can configure channels of a parallel digital module as Programmable Function Interface
(PFI) terminals. Up to two digital modules can be used to access PFI terminals in a single
controller.

You can configure each PFI individually as the following:

• Timing input signal for AI, AO, DI, DO, or counter/timer functions

• Timing output signal from AI, AO, DI, DO, or counter/timer functions

PFI Filters

You can enable a programmable debouncing filter on each PFI signal. When the filter is enabled,
the controller samples the inputs with a user-configured Filter Clock derived from the controller
timebase. This is used to determine whether a pulse is propagated to the rest of the circuit.
However, the filter also introduces jitter onto the PFI signal.

The following is an example of low-to-high transitions of the input signal. High-to-low
transitions work similarly.

Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the Filter Clock has sampled the signal high

© National Instruments | 4-13

Chapter 4 Digital Input/Output and PFI

on N consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The
value of N depends on the filter setting, as shown in Table 4-1.

Table 4-1. Selectable PFI Filter Settings

Min Pulse

*

Filter

Setting

Filter Clock Jitter

Width

Pass

to

Max Pulse Width*

to Not Pass

112.5 ns

80 MHz 12.5 ns 112.5 ns 100 ns

(short)

6.4 μs

80 MHz 12.5 ns 6.4 μs 6.3875 μs

(medium)

2.56 ms

100 kHz 10 μs 2.56 ms 2.55 ms

(high)

Custom User-configurable 1 Filter

Clock

T

user

T

- (1 Filter Clock

user

period)

period

*

Pulse widths are nominal values; the accuracy of the controller timebase and I/O distortion will affect

these values.

On powerup, the filters are disabled. Figure 4-7 shows an example of a low-to-high transition on
an input that has a custom filter set to N = 5.

Figure 4-7. PFI Filter Example

PFI Terminal

Filter Clock

Filtered Input

12314123 45

Filtered input goes
high when terminal
is sampled high on
five consecutive filter
clocks.

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5

Counter 0

Counter 0 Source (Counter 0 Timebase)

Counter 0 Aux

Counter 0 HW Arm

Counter 0 A

Counter 0 B (Counter 0 Up_Down)

Counter 0 Z

Counter 0 Gate

Counter 0 Internal Output

Counter 0 TC

Input Selection Muxes

Frequency Generator

Frequency Output Timebase

Freq Out

Input Selection Muxes

Embedded Ctr0

FIFO

Counter 0 Sample Clock

Counters

The cDAQ controller has four general-purpose 32-bit counter/timers and one frequency
generator. The general-purpose counter/timers can be used for many measurement and pulse
generation applications. Figure 5-1 shows the cDAQ controller Counter 0 and the frequency
generator. All four counters on the cDAQ controller are identical.

Figure 5-1. Controller Counter 0 and Frequency Generator

Counters have eight input signals, although in most applications only a few inputs are used.

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Each counter has a FIFO that can be used for buffered acquisition and generation. Each counter
also contains an embedded counter (Embedded Ctrn) for use in what are traditionally
two-counter measurements and generations. The embedded counters cannot be programmed
independent of the main counter; signals from the embedded counters are not routable.

© National Instruments | 5-1

Chapter 5 Counters

Counter Timing Engine

Unlike analog input, analog output, digital input, and digital output, the cDAQ controller
counters do not have the ability to divide down a timebase to produce an internal counter sample
clock. For sample clocked operations, an external signal must be provided to supply a clock
source. The source can be any of the following signals:

• AI Sample Clock

• AI Start Trigger

• AI Reference Trigger

• AO Sample Clock

• DI Sample Clock

• DI Start Trigger

• DO Sample Clock

•CTR n Internal Output

• Freq Out

• PFI

• Change Detection Event

• Analog Comparison Event

Not all timed counter operations require a sample clock. For example, a simple buffered pulse
width measurement latches in data on each edge of a pulse. For this measurement, the measured
signal determines when data is latched in. These operations are referred to as implicit timed
operations. However, many of the same measurements can be clocked at an interval with a
sample clock. These are referred to as sample clocked operations. Table 5-1 shows the different
options for the different measurements.

Table 5-1. Counter Timing Measurements

Measurement

Implicit

Timing Support

Sample Clocked

Timing Support

Buffered Edge Count No Ye s

Buffered Pulse Width Ye s Ye s

Buffered Pulse Ye s Ye s

Buffered Semi-Period Ye s No

Buffered Frequency Ye s Ye s

Buffered Period Ye s Ye s

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NI cDAQ-9138/9139 User Manual

Counter Armed

SOURCE

Counter Value105432

Table 5-1. Counter Timing Measurements (Continued)

Implicit

Measurement

Buffered Position No Ye s

Buffered Two-Signal Edge Separation Ye s Ye s

Timing Support

Sample Clocked

Timing Support

Counter Input Applications

The following sections list the various counter input applications available on the cDAQ
controller:

• Counting Edges

• Pulse-Width Measurement

• Pulse Measurement

• Semi-Period Measurement

• Frequency Measurement

• Period Measurement

• Position Measurement

Counting Edges

In edge counting applications, the counter counts edges on its Source after the counter is armed.
You can configure the counter to count rising or falling edges on its Source input. You also can
control the direction of counting (up or down), as described in the Controlling the Direction of

Counting section. The counter values can be read on demand or with a sample clock.

Refer to the following sections for more information about edge counting options:

• Single Point (On-Demand) Edge Counting

• Buffered (Sample Clock) Edge Counting

Single Point (On-Demand) Edge Counting

With single point (on-demand) edge counting, the counter counts the number of edges on the
Source input after the counter is armed. On-demand refers to the fact that software can read the
counter contents at any time without disturbing the counting process. Figure 5-2 shows an
example of single point edge counting.

Figure 5-2. Single Point (On-Demand) Edge Counting

© National Instruments | 5-3

Chapter 5 Counters

Counter Armed

SOURCE

Pause Trigger

(Pause When Low)

Counter Value

100 5432

You also can use a pause trigger to pause (or gate) the counter. When the pause trigger is active,
the counter ignores edges on its Source input. When the pause trigger is inactive, the counter
counts edges normally.

You can route the pause trigger to the Gate input of the counter. You can configure the counter
to pause counting when the pause trigger is high or when it is low. Figure 5-3 shows an example
of on-demand edge counting with a pause trigger.

Figure 5-3. Single Point (On-Demand) Edge Counting with Pause Trigger

Buffered (Sample Clock) Edge Counting

With buffered edge counting (edge counting using a sample clock), the counter counts the
number of edges on the Source input after the counter is armed. The value of the counter is
sampled on each active edge of a sample clock and stored in the FIFO. The STC3 transfers the
sampled values to host memory using a high-speed data stream.

The count values returned are the cumulative counts since the counter armed event. That is, the
sample clock does not reset the counter. You can configure the counter to sample on the rising
or falling edge of the sample clock.

Figure 5-4 shows an example of buffered edge counting. Notice that counting begins when the
counter is armed, which occurs before the first active edge on Sample Clock.

Controlling the Direction of Counting

In edge counting applications, the counter can count up or down. You can configure the counter
to do the following:

• Always count up

• Always count down

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(Sample on Rising Edge)

Figure 5-4. Buffered (Sample Clock) Edge Counting

Counter Armed

Sample Clock

SOURCE

Counter Value

Buffer

10763 452

3

3

6

NI cDAQ-9138/9139 User Manual

SOURCE

GATE

Counter Value

Latched Value

10

2

2

• Count up when the Counter 0 B input is high; count down when it is low

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Pulse-Width Measurement

In pulse-width measurements, the counter measures the width of a pulse on its Gate input signal.
You can configure the counter to measure the width of high pulses or low pulses on the Gate
signal.

You can route an internal or external periodic clock signal (with a known period) to the Source
input of the counter. The counter counts the number of rising (or falling) edges on the Source
signal while the pulse on the Gate signal is active.

You can calculate the pulse width by multiplying the period of the Source signal by the number
of edges returned by the counter.

A pulse-width measurement will be accurate even if the counter is armed while a pulse train is
in progress. If a counter is armed while the pulse is in the active state, it will wait for the next
transition to the active state to begin the measurement.

Refer to the following sections for more information about cDAQ controller pulse-width
measurement options:

• Single Pulse-Width Measurement

• Implicit Buffered Pulse-Width Measurement

• Sample Clocked Buffered Pulse-Width Measurement

Single Pulse-Width Measurement

With single pulse-width measurement, the counter counts the number of edges on the Source
input while the Gate input remains active. When the Gate input goes inactive, the counter stores
the count in the FIFO and ignores other edges on the Gate and Source inputs. Software then reads
the stored count.

Figure 5-5 shows an example of a single pulse-width measurement.

Figure 5-5. Single Pulse-Width Measurement

© National Instruments | 5-5

Chapter 5 Counters

Pulse

Source

Sample Clock

2

3

42

4

3

2

2

4

Buffer

Implicit Buffered Pulse-Width Measurement

An implicit buffered pulse-width measurement is similar to single pulse-width measurement, but
buffered pulse-width measurement takes measurements over multiple pulses.

The counter counts the number of edges on the Source input while the Gate input remains active.
On each trailing edge of the Gate signal, the counter stores the count in the counter FIFO. The
STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-6 shows an example of an implicit buffered pulse-width measurement.

Figure 5-6. Implicit Buffered Pulse-Width Measurement

GATE

SOURCE

Counter Value

Buffer

10 3

3

3

212

3

2

2

Sample Clocked Buffered Pulse-Width Measurement

A sample clocked buffered pulse-width measurement is similar to single pulse-width
measurement, but buffered pulse-width measurement takes measurements over multiple pulses
correlated to a sample clock.

The counter counts the number of edges on the Source input while the Gate input remains active.
On each sample clock edge, the counter stores the count in the FIFO of the last pulse width to
complete. The STC3 transfers the sampled values to host memory using a high-speed data
stream.

Figure 5-7 shows an example of a sample clocked buffered pulse-width measurement.

Figure 5-7. Sample Clocked Buffered Pulse-Width Measurement

Note If a pulse does not occur between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

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NI cDAQ-9138/9139 User Manual

Counter Armed

Gate

Source

HL

710

7

10

Latched

Value

987654321564321

Pulse Measurement

In pulse measurements, the counter measures the high and low time of a pulse on its Gate input
signal after the counter is armed. A pulse is defined in terms of its high and low time, high and
low ticks or frequency and duty cycle. This is similar to the pulse-width measurement, except
that the inactive pulse is measured as well.

You can route an internal or external periodic clock signal (with a known period) to the Source
input of the counter. The counter counts the number of rising (or falling) edges occurring on the
Source input between two edges of the Gate signal.

You can calculate the high and low time of the Gate input by multiplying the period of the Source
signal by the number of edges returned by the counter.

Refer to the following sections for more information about cDAQ controller pulse measurement
options:

• Single Pulse Measurement

• Implicit Buffered Pulse Measurement

• Sample Clocked Buffered Pulse Measurement

Single Pulse Measurement

Single (on-demand) pulse measurement is equivalent to two single pulse-width measurements
on the high (H) and low (L) ticks of a pulse, as shown in Figure 5-8.

Figure 5-8. Single (On-Demand) Pulse Measurement

Implicit Buffered Pulse Measurement

In an implicit buffered pulse measurement, on each edge of the Gate signal, the counter stores
the count in the FIFO. The STC3 transfers the sampled values to host memory using a
high-speed data stream.

The counter begins counting when it is armed. The arm usually occurs between edges on the
Gate input but the counting does not start until the desired edge. You can select whether to read

the high pulse or low pulse first using the StartingEdge property in NI-DAQmx.

© National Instruments | 5-7

Chapter 5 Counters

Counter

Armed

Gate

Source

HL
2

2

HL

22

3

3

Sample

Clock

S1

S2

Buffer

2

2

3

3

Figure 5-9 shows an example of an implicit buffered pulse measurement.

Figure 5-9. Implicit Buffered Pulse Measurement

Counter Armed

Gate

Source

Buffer

HL

42

HL

42
4

HL

2

4
4

4

4
2

6

HL

4
44
6
2

2

2
2

Sample Clocked Buffered Pulse Measurement

A sample clocked buffered pulse measurement is similar to single pulse measurement, but a
buffered pulse measurement takes measurements over multiple pulses correlated to a sample
clock.

The counter performs a pulse measurement on the Gate. On each sample clock edge, the counter
stores the high and low ticks in the FIFO of the last pulse to complete. The STC3 transfers the
sampled values to host memory using a high-speed data stream.

Figure 5-10 shows an example of a sample clocked buffered pulse measurement.

Figure 5-10. Sample Clocked Buffered Pulse Measurement

Note If a pulse does not occur between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Semi-Period Measurement

In semi-period measurements, the counter measures a semi-period on its Gate input signal after
the counter is armed. A semi-period is the time between any two consecutive edges on the Gate
input.

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NI cDAQ-9138/9139 User Manual

1
2

3

1

3

3

SOURCE

GATE

Counter Value

Buffer

1 3

2

2

11

13

12

0

Counter

Armed

Starting

Edge

You can route an internal or external periodic clock signal (with a known period) to the Source
input of the counter. The counter counts the number of rising (or falling) edges occurring on the
Source input between two edges of the Gate signal.

You can calculate the semi-period of the Gate input by multiplying the period of the Source
signal by the number of edges returned by the counter.

Refer to the following sections for more information about semi-period measurement options:

• Single Semi-Period Measurement

• Implicit Buffered Semi-Period Measurement

Refer to the Pulse versus Semi-Period Measurements section for information about the
differences between semi-period measurement and pulse measurement.

Single Semi-Period Measurement

Single semi-period measurement is equivalent to single pulse-width measurement.

Implicit Buffered Semi-Period Measurement

In implicit buffered semi-period measurements, on each edge of the Gate signal, the counter
stores the count in the FIFO. The STC3 transfers the sampled values to host memory using a
high-speed data stream.

The counter begins counting when it is armed. The arm usually occurs between edges on the
Gate input. You can select whether to read the first active low or active high semi period using

the CI.SemiPeriod.StartingEdge property in NI-DAQmx.

Figure 5-11 shows an example of an implicit buffered semi-period measurement.

Figure 5-11. Implicit Buffered Semi-Period Measurement

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

© National Instruments | 5-9

Chapter 5 Counters

Pulse versus Semi-Period Measurements

In hardware, pulse measurement and semi-period are the same measurement. Both measure the
high and low times of a pulse. The functional difference between the two measurements is how
the data is returned. In a semi-period measurement, each high or low time is considered one point
of data and returned in units of seconds or ticks. In a pulse measurement, each pair of high and
low times is considered one point of data and returned as a paired sample in units of frequency
and duty cycle, high and low time or high and low ticks. When reading data, 10 points in a
semi-period measurement will get an array of five high times and five low times. When you read
10 points in a pulse measurement, you get an array of 10 pairs of high and low times.

Also, pulse measurements support sample clock timing while semi-period measurements do not.

Frequency Measurement

You can use the counters to measure frequency in several different ways. Refer to the following
sections for information about cDAQ controller frequency measurement options:

• Low Frequency with One Counter

• High Frequency with Two Counters

• Large Range of Frequencies with Two Counters

• Sample Clocked Buffered Frequency Measurement

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NI cDAQ-9138/9139 User Manual

fx

fk

Gate

Source

123 … N

Single Period

Measurement

…

Period of fx =

N

Frequency of fx =

N

Interval Measured

fk

fk

fk

fx

Low Frequency with One Counter

For low frequency measurements with one counter, you measure one period of your signal using
a known timebase.

You can route the signal to measure (fx) to the Gate of a counter. You can route a known timebase
(fk) to the Source of the counter. The known timebase can be an onboard timebase, such as
80 MHz Timebase, 20 MHz Timebase, or 100 kHz Timebase, or any other signal with a known
rate.

You can configure the counter to measure one period of the gate signal. The frequency of fx is
the inverse of the period. Figure 5-12 illustrates this method.

Figure 5-12. Low Frequency with One Counter

© National Instruments | 5-11

Chapter 5 Counters

High Frequency with Two Counters

For high frequency measurements with two counters, you measure one pulse of a known width
using your signal and derive the frequency of your signal from the result.

Note Counter 0 is always paired with Counter 1. Counter 2 is always paired with

Counter 3.

In this method, you route a pulse of known duration (T) to the Gate of a counter. You can
generate the pulse using a second counter. You also can generate the pulse externally and connect
it to a PFI terminal. You only need to use one counter if you generate the pulse externally.

Route the signal to measure (fx) to the Source of the counter. Configure the counter for a single
pulse-width measurement. If you measure the width of pulse T to be N periods of fx, the
frequency of fx is N/T.

Figure 5-13 illustrates this method. Another option is to measure the width of a known period
instead of a known pulse.

Figure 5-13. High Frequency with Two Counters

Width of Pulse (T )

Pulse

fx

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Gate

Source

Pulse-Width

Measurement

Pulse

12… N

fx

Width of

Frequency of fx =

Pulse

T =

N

fx

N

T

NI cDAQ-9138/9139 User Manual

Source Out

Counter 0

Source

Gate

Out

Counter 1

Signal to

Measure (fx)

Signal of Known

Frequency (fk)

CTR_0_SOURCE

(Signal to Measure)

CTR_0_OUT

(CTR_1_GATE)

CTR_1_SOURCE

Interval

to Measure

0123 … N

Large Range of Frequencies with Two Counters

By using two counters, you can accurately measure a signal that might be high or low frequency.
This technique is called reciprocal frequency measurement. When measuring a large range of
frequencies with two counters, you generate a long pulse using the signal to measure. You then
measure the long pulse with a known timebase. The cDAQ controller can measure this long
pulse more accurately than the faster input signal.

Note Counter 0 is always paired with Counter 1. Counter 2 is always paired with

Counter 3.

You can route the signal to measure to the Source input of Counter 0, as shown in Figure 5-14.
Assume this signal to measure has frequency fx. NI-DAQmx automatically configures Counter 0
to generate a single pulse that is the width of N periods of the source input signal.

Figure 5-14. Large Range of Frequencies with Two Counters

Next, route the Counter 0 Internal Output signal to the Gate input of Counter 1. You can route a
signal of known frequency (fk) to the Counter 1 Source input. Configure Counter 1 to perform
a single pulse-width measurement. Suppose the result is that the pulse width is J periods of the
fk clock.

From Counter 0, the length of the pulse is N/fx. From Counter 1, the length of the same pulse is
J/fk. Therefore, the frequency of fx is given by fx = fk *(N/J).

© National Instruments | 5-13

Chapter 5 Counters

Sample Clocked Buffered Frequency Measurement

Sample clocked buffered point frequency measurements can either be a single frequency

measurement or an average between sample clocks. Use CI.Freq.EnableAveraging to set the

behavior. For buffered frequency, the default is True.

A sample clocked buffered frequency measurement with CI.Freq.EnableAveraging set to True

uses the embedded counter and a sample clock to perform a frequency measurement. For each
sample clock period, the embedded counter counts the signal to measure (fx) and the primary
counter counts the internal time-base of a known frequency (fk). Suppose T1 is the number of
ticks of the unknown signal counted between sample clocks and T2 is the number of ticks
counted of the known timebase as shown in Figure 5-15. The frequency measured is:

fx = fk * (T1/T2)

Figure 5-15. Sample Clocked Buffered Frequency Measurement (Averaging)

Counter Armed

S1 S2 S3

Gate

(fx)

Source

(fk)

Sample

Clock

Buffer

121

6106

T1 T2

1

6

T1 T2

17
210

T1 T2

1
2
1

10

7

6

When CI.Freq.EnableAveraging is set to false, the frequency measurement returns the

frequency of the pulse just before the sample clock. This single measurement is a single
frequency measurement and is not an average between clocks as shown in Figure 5-16.

Figure 5-16. Sample Clocked Buffered Frequency Measurement (Non-Averaging)

Counter Armed

Gate

Source

Sample

Clock

Latched

Values

646

6

6
4

6
4
6

With sample clocked frequency measurements, ensure that the frequency to measure is twice as
fast as the sample clock to prevent a measurement overflow.

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NI cDAQ-9138/9139 User Manual

Choosing a Method for Measuring Frequency

The best method to measure frequency depends on several factors including the expected
frequency of the signal to measure, the desired accuracy, how many counters are available, and
how long the measurement can take. For all frequency measurement methods, assume the
following:

fx is the frequency to be measured if no error

fk is the known source or gate frequency

measurement time (T) is the time it takes to measure a single sample

Divide down (N) is the integer to divide down measured frequency, only used in

large range two counters

fs is the sample clock rate, only used in sample clocked frequency

measurements

Here is how these variables apply to each method, summarized in Table 5-2.

• One counter—With one counter measurements, a known timebase is used for the source
frequency (fk). The measurement time is the period of the frequency to be measured, or
1/fx.

• Two counter high frequency—With the two counter high frequency method, the second
counter provides a known measurement time. The gate frequency equals 1/measurement
time.

• Two counter large range—The two counter larger range measurement is the same as a

one counter measurement, but now the user has an integer divide down of the signal. An
internal timebase is still used for the source frequency (fk), but the divide down means that
the measurement time is the period of the divided down signal, or N/fx where N is the divide
down.

• Sample clocked—For sample clocked frequency measurements, a known timebase is
counted for the source frequency (fk). The measurement time is the period of the sample
clock (fs).

© National Instruments | 5-15

Chapter 5 Counters

1

gating period

-------------------------------

1

fs

--- -

1

fx

----

N
fx

----

fx

fx

fk

fx
fs

---- 1–

------------------------------ -

fx

fx

fk fx–

-------------- -

fx

fx

Nfkfx–

-------------------------

fx

fk

fx
fs

---- 1–

------------------------------ -

fx

fk fx–

-------------- -

fk
fx

----

fx

Nfkfx–

-------------------------

Table 5-2. Frequency Measurement Methods

Variab le Sample Clocked One Counter

Two Counter

High

Frequency

Large Range

fk Known timebase Known

Known timebase

timebase

Measurement

gating period

time

Max.

fk

frequency
error

Max. error %

Note: Accuracy equations do not take clock stability into account. Refer to the specifications document
for your cDAQ controller for information about clock stability.

Which Method Is Best?

This depends on the frequency to be measured, the rate at which you want to monitor the
frequency and the accuracy you desire. Take for example, measuring a 50 kHz signal. Assuming
that the measurement times for the sample clocked (with averaging) and two counter frequency
measurements are configured the same, Table 5-3 summarizes the results.

Table 5-3. 50 kHz Frequency Measurement Methods

5-16 | ni.com

Two Counter

Var iab le

Sample

Clocked

One Counter

High

Frequency

Large Range

fx 50,000 50,000 50,000 50,000
fk 80 M 80 M 1,000 80 M
Measurement

1 .02 1 1

time (mS)
N — — — 50

NI cDAQ-9138/9139 User Manual

Table 5-3. 50 kHz Frequency Measurement Methods (Continued)

Two Counter

Var iab le

Max. frequency

Sample

Clocked

One Counter

.638 31.27 1,000 .625

High

Frequency

Large Range

error (Hz)

Max. error % .00128 .0625 2 .00125

From this, you can see that while the measurement time for one counter is shorter, the accuracy
is best in the sample clocked and two counter large range measurements. For another example,
Table 5-4 shows the results for 5 MHz.

Table 5-4. 5 MHz Frequency Measurement Methods

Two Counter

Var iab le

Sample

Clocked

One Counter

High

Frequency

Large Range

fx 5 M 5 M 5 M 5 M
fk 80 M 80 M 1,000 80 M
Measurement

1 .0002 1 1

time (mS)
N — — — 5,000

Max.

62.51 333 k 1,000 62.50
Frequency
error (Hz)

Max. Error % .00125 6.67 .02 .00125

Again the measurement time for the one counter measurement is lowest but the accuracy is
lower. Note that the accuracy and measurement time of the sample clocked and two counter large
range are almost the same. The advantage of the sample clocked method is that even when the
frequency to measure changes, the measurement time does not and error percentage varies little.
For example, if you configured a large range two counter measurement to use a divide down of
50 for a 50 k signal, then you would get the accuracy measurement time and accuracy listed in
Table 5-3. But if your signal ramped up to 5 M, then with a divide down of 50, your measurement
time is 0.01 ms, but your error is now 0.125%. The error with a sample clocked frequency
measurement is not as dependent on the measured frequency so at 50 k and 5 M with a
measurement time of 1 ms the error percentage is still close to 0.00125%. One of the
disadvantages of a sample clocked frequency measurement is that the frequency to be measured

© National Instruments | 5-17

Chapter 5 Counters

must be at least twice the sample clock rate to ensure that a full period of the frequency to be
measured occurs between sample clocks.

• Low frequency measurements with one counter is a good method for many applications.
However, the accuracy of the measurement decreases as the frequency increases.

• High frequency measurements with two counters is accurate for high frequency signals.
However, the accuracy decreases as the frequency of the signal to measure decreases. At
very low frequencies, this method may be too inaccurate for your application. Another
disadvantage of this method is that it requires two counters (if you cannot provide an
external signal of known width). An advantage of high frequency measurements with
two counters is that the measurement completes in a known amount of time.

• Measuring a large range of frequencies with two counters measures high and low frequency
signals accurately. However, it requires two counters, and it has a variable sample time and
variable error % dependent on the input signal.

Table 5-5 summarizes some of the differences in methods of measuring frequency.

Table 5-5. Frequency Measurement Method Comparison

Measures

High

Frequency

Signals

Accurately

Measures Low

Frequency

Signals

Accurately

Method

Number

of

Counters

Used

Number of

Measurements

Returned

Low frequency

1 1 Poor Good

with one counter

High frequency

1 or 2 1 Good Poor
with two
counters

Large range of

2 1 Good Good
frequencies with
two counters

Sample clocked

1 1 Good Good
(averaged)

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Period Measurement

In period measurements, the counter measures a period on its Gate input signal after the counter
is armed. You can configure the counter to measure the period between two rising edges or
two falling edges of the Gate input signal.

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NI cDAQ-9138/9139 User Manual

You can route an internal or external periodic clock signal (with a known period) to the Source
input of the counter. The counter counts the number of rising (or falling) edges occurring on the
Source input between the two active edges of the Gate signal.

You can calculate the period of the Gate input by multiplying the period of the Source signal by
the number of edges returned by the counter.

Period measurements return the inverse results of frequency measurements. Refer to the

Frequency Measurement section for more information.

Position Measurement

You can use the counters to perform position measurements with quadrature encoders or
two-pulse encoders. You can measure angular position with X1, X2, and X4 angular encoders.
Linear position can be measured with two-pulse encoders. You can choose to do either a single
point (on-demand) position measurement or a buffered (sample clock) position measurement.
You must arm a counter to begin position measurements.

Refer to the following sections for more information about the cDAQ controller position
measurement options:

• Measurements Using Quadrature Encoders

• Measurements Using Two Pulse Encoders

• Buffered (Sample Clock) Position Measurement

Measurements Using Quadrature Encoders

The counters can perform measurements of quadrature encoders that use X1, X2, or X4
encoding. A quadrature encoder can have up to three channels—channels A, B, and Z.

• X1 Encoding—When channel A leads channel B in a quadrature cycle, the counter

increments. When channel B leads channel A in a quadrature cycle, the counter
decrements. The amount of increments and decrements per cycle depends on the type of
encoding—X1, X2, or X4.

Figure 5-17 shows a quadrature cycle and the resulting increments and decrements for X1
encoding. When channel A leads channel B, the increment occurs on the rising edge of
channel A. When channel B leads channel A, the decrement occurs on the falling edge of
channel A.

Figure 5-17. X1 Encoding

Ch A
Ch B

Counter Value

6

5

7

7

5

6

• X2 Encoding—The same behavior holds for X2 encoding except the counter increments

or decrements on each edge of channel A, depending on which channel leads the other.
Each cycle results in two increments or decrements, as shown in Figure 5-18.

© National Instruments | 5-19

Chapter 5 Counters

Ch A

Ch B

Counter Value5 6 8 910 1011 1112 1213 137

568 79

Figure 5-18. X2 Encoding

Ch A

Ch B

Counter Value

56 8

7

9

9

8

6

7

5

• X4 Encoding—Similarly, the counter increments or decrements on each edge of

channels A and B for X4 encoding. Whether the counter increments or decrements depends
on which channel leads the other. Each cycle results in four increments or decrements, as
shown in Figure 5-19.

Figure 5-19. X4 Encoding

Channel Z Behavior

Some quadrature encoders have a third channel, channel Z, which is also referred to as the index
channel. A high level on channel Z causes the counter to be reloaded with a specified value in a
specified phase of the quadrature cycle. You can program this reload to occur in any one of the
four phases in a quadrature cycle.

Channel Z behavior—when it goes high and how long it stays high—differs with quadrature
encoder designs. You must refer to the documentation for your quadrature encoder to obtain
timing of channel Z with respect to channels A and B. You must then ensure that channel Z is
high during at least a portion of the phase you specify for reload. For instance, in Figure 5-20,
channel Z is never high when channel A is high and channel B is low. Thus, the reload must
occur in some other phase.

In Figure 5-20, the reload phase is when both channel A and channel B are low. The reload
occurs when this phase is true and channel Z is high. Incrementing and decrementing takes
priority over reloading. Thus, when the channel B goes low to enter the reload phase, the
increment occurs first. The reload occurs within one maximum timebase period after the reload
phase becomes true. After the reload occurs, the counter continues to count as before. The figure
illustrates channel Z reload with X4 decoding.

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NI cDAQ-9138/9139 User Manual

Ch A

Ch B

Counter Value

5

6

A = 0
B = 0
Z = 1

Ch Z

Max Timebase

8

9

021743

Figure 5-20. Channel Z Reload with X4 Decoding

Measurements Using Two Pulse Encoders

The counter supports two pulse encoders that have two channels—channels A and B.

The counter increments on each rising edge of channel A. The counter decrements on each rising
edge of channel B, as shown in Figure 5-21.

Figure 5-21. Measurements Using Two Pulse Encoders

Ch A

Ch B

Counter Value

2 3 54 344

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Buffered (Sample Clock) Position Measurement

With buffered position measurement (position measurement using a sample clock), the counter
increments based on the encoding used after the counter is armed. The value of the counter is
sampled on each active edge of a sample clock. The STC3 transfers the sampled values to host
memory using a high-speed data stream. The count values returned are the cumulative counts
since the counter armed event; that is, the sample clock does not reset the counter. You can route
the counter sample clock to the Gate input of the counter. You can configure the counter to
sample on the rising or falling edge of the sample clock.

Figure 5-22 shows an example of a buffered X1 position measurement.

© National Instruments | 5-21

Chapter 5 Counters

1

3

1

Ch A

Ch B

3102 4

Count

Buffer

Sample Clock

(Sample on Rising Edge)

Counter
Armed

Figure 5-22. Buffered Position Measurement

Two-Signal Edge-Separation Measurement

Two-signal edge-separation measurement is similar to pulse-width measurement, except that
there are two measurement signals—Aux and Gate. An active edge on the Aux input starts the
counting and an active edge on the Gate input stops the counting. You must arm a counter to
begin a two edge separation measurement.

After the counter has been armed and an active edge occurs on the Aux input, the counter counts
the number of rising (or falling) edges on the Source. The counter ignores additional edges on
the Aux input.

The counter stops counting upon receiving an active edge on the Gate input. The counter stores
the count in the FIFO.

You can configure the rising or falling edge of the Aux input to be the active edge. You can
configure the rising or falling edge of the Gate input to be the active edge.

Use this type of measurement to count events or measure the time that occurs between edges on
two signals. This type of measurement is sometimes referred to as start/stop trigger
measurement, second gate measurement, or A-to-B measurement.

Refer to the following sections for more information about the cDAQ controller edge-separation
measurement options:

• Single Two-Signal Edge-Separation Measurement

• Implicit Buffered Two-Signal Edge-Separation Measurement

• Sample Clocked Buffered Two-Signal Separation Measurement

Single Two-Signal Edge-Separation Measurement

With single two-signal edge-separation measurement, the counter counts the number of rising
(or falling) edges on the Source input occurring between an active edge of the Gate signal and
an active edge of the Aux signal. The counter then stores the count in the FIFO and ignores other
edges on its inputs. Software then reads the stored count.

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NI cDAQ-9138/9139 User Manual

AUX

Counter

Armed

8

000123 4567880 8

Measured Interval

GATE

SOURCE

Counter Value

Latched Value

Figure 5-23 shows an example of a single two-signal edge-separation measurement.

Figure 5-23. Single Two-Signal Edge-Separation Measurement

Implicit Buffered Two-Signal Edge-Separation Measurement

Implicit buffered and single two-signal edge-separation measurements are similar, but implicit
buffered measurement measures multiple intervals.

The counter counts the number of rising (or falling) edges on the Source input occurring between
an active edge of the Gate signal and an active edge of the Aux signal. The counter then stores
the count in the FIFO. On the next active edge of the Gate signal, the counter begins another
measurement. The STC3 transfers the sampled values to host memory using a high-speed data
stream.

Figure 5-24 shows an example of an implicit buffered two-signal edge-separation measurement.

Figure 5-24. Implicit Buffered Two-Signal Edge-Separation Measurement

AUX

GATE

SOURCE

Counter Value

Buffer

123 123 123

3

3
3

3
3
3

Sample Clocked Buffered Two-Signal Separation Measurement

A sample clocked buffered two-signal separation measurement is similar to single two-signal
separation measurement, but buffered two-signal separation measurement takes measurements
over multiple intervals correlated to a sample clock. The counter counts the number of rising (or
falling) edges on the Source input occurring between an active edge of the Gate signal and an
active edge of the Aux signal. The counter then stores the count in the FIFO on a sample clock
edge. On the next active edge of the Gate signal, the counter begins another measurement. The
STC3 transfers the sampled values to host memory using a high-speed data stream.

Figure 5-25 shows an example of a sample clocked buffered two-signal separation
measurement.

© National Instruments | 5-23

Chapter 5 Counters

Figure 5-25. Sample Clocked Buffered Two-Signal Separation Measurement

Sample

Clock

AUX

GATE

SOURCE

Counter Value

Buffer

Note If an active edge on the Gate and an active edge on the Aux does not occur

123 12 3 123

3 3

3

between sample clocks, an overrun error occurs.

For information about connecting counter signals, refer to the Default Counter/Timer Routing
section.

Counter Output Applications

The following sections list the various counter output applications available on the cDAQ
controller:

• Simple Pulse Generation

• Pulse Train Generation

• Frequency Generation

• Frequency Division

• Pulse Generation for ETS

Simple Pulse Generation

Refer to the following sections for more information about the cDAQ controller simple pulse
generation options:

• Single Pulse Generation

• Single Pulse Generation with Start Trigger

Single Pulse Generation

The counter can output a single pulse. The pulse appears on the Counter n Internal Output signal
of the counter.

You can specify a delay from when the counter is armed to the beginning of the pulse. The delay
is measured in terms of a number of active edges of the Source input.

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NI cDAQ-9138/9139 User Manual

SOURCE

OUT

Counter Armed

You can specify a pulse width. The pulse width is also measured in terms of a number of active
edges of the Source input. You also can specify the active edge of the Source input (rising or
falling).

Figure 5-26 shows a generation of a pulse with a pulse delay of four and a pulse width of three
(using the rising edge of Source).

Figure 5-26. Single Pulse Generation

Single Pulse Generation with Start Trigger

The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal.
The pulse appears on the Counter n Internal Output signal of the counter.

You can specify a delay from the Start Trigger to the beginning of the pulse. You also can specify
the pulse width. The delay is measured in terms of a number of active edges of the Source input.

You can specify a pulse width. The pulse width is also measured in terms of a number of active
edges of the Source input. You can also specify the active edge of the Source input (rising and
falling).

Figure 5-27 shows a generation of a pulse with a pulse delay of four and a pulse width of three
(using the rising edge of Source).

Figure 5-27. Single Pulse Generation with Start Trigger

GATE

(Start Trigger)

SOURCE

OUT

Pulse Train Generation

Refer to the following sections for more information about the cDAQ controller pulse train
generation options:

• Finite Pulse Train Generation

• Retriggerable Pulse or Pulse Train Generation

• Continuous Pulse Train Generation

• Buffered Pulse Train Generation

• Finite Implicit Buffered Pulse Train Generation

© National Instruments | 5-25

Chapter 5 Counters

Enablex

Source

Ctrx

Counter Armed

• Continuous Buffered Implicit Pulse Train Generation

• Finite Buffered Sample Clocked Pulse Train Generation

• Continuous Buffered Sample Clocked Pulse Train Generation

Finite Pulse Train Generation

This function generates a train of pulses with programmable frequency and duty cycle for a
predetermined number of pulses. With cDAQ controller counters, the primary counter generates
the specified pulse train and the embedded counter counts the pulses generated by the primary
counter. When the embedded counter reaches the specified tick count, it generates a trigger that
stops the primary counter generation.

Figure 5-28. Finite Pulse Train Generation: Four Ticks Initial Delay, Four Pulses

Retriggerable Pulse or Pulse Train Generation

The counter can output a single pulse or multiple pulses in response to each pulse on a hardware
Start Trigger signal. The generated pulses appear on the Counter n Internal Output signal of the
counter.

You can route the Start Trigger signal to the Gate input of the counter. You can specify a delay
from the Start Trigger to the beginning of each pulse. You also can specify the pulse width. The
delay and pulse width are measured in terms of a number of active edges of the Source input.
The initial delay can be applied to only the first trigger or to all triggers using the

CO.EnableInitialDelayOnRetrigger property. The default for a single pulse is True, while the

default for finite pulse trains is False.

The counter ignores the Gate input while a pulse generation is in progress. After the pulse
generation is finished, the counter waits for another Start Trigger signal to begin another pulse
generation. For retriggered pulse generation, pause triggers are not allowed since the pause
trigger also uses the gate input.

Figure 5-29 shows a generation of two pulses with a pulse delay of five and a pulse width of

three (using the rising edge of Source) with CO.EnableInitialDelayOnRetrigger set to the

default True.

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