National Instruments AT-MIO-64F-5 Owners Manual

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AT-MIO-64F-5

User Manual

Multifunction I/O Board for the PC AT/EISA

July 1994 Edition

Part Number 320487-01

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National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices:

Australia (03) 879 9422, Austria (0662) 435986, Belgium 02/757.00.20, Canada (Ontario) (519) 622-9310, Canada (QuŽbec) (514) 694-8521, Denmark 45 76 26 00, Finland (90) 527 2321, France (1) 48 14 24 24, Germany 089/741 31 30, Italy 02/48301892, Japan (03) 3788-1921, Netherlands 03480-33466, Norway 32-848400, Spain (91) 640 0085, Sweden 08-730 49 70, Switzerland 056/27 00 20, U.K. 0635 523545

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Limited Warranty

The AT-MIO-64F-5 is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OF

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation, or maintenance instructions; owner's modification of the product; owner's abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

. CUSTOMER'S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

. This limitation of the liability of National Instruments will apply regardless of the form of action,

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

LabVIEW¨, NI-DAQ¨, and RTSI¨ are trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

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Warning Regarding Medical and Clinical Use

of National Instruments Products

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

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Preface

This manual describes the mechanical and electrical aspects of the AT-MIO-64F-5 board and contains information concerning its operation and programming. The AT-MIO-64F-5 is a highperformance, multifunction analog, digital, and timing I/O board for the IBM PC AT and compatible computers and EISA personal computers (PCs).

Organization of This Manual

The AT-MIO-64F-5 User Manual is organized as follows:

¥ Chapter 1, Introduction, describes the AT-MIO-64F-5, lists the contents of your

AT-MIO-64F-5 kit, the optional software, and the optional equipment, and explains how to unpack the AT-MIO-64F-5.

¥ Chapter 2, Configuration and Installation, explains the board configuration, installation of

the AT-MIO-64F-5 into the PC, signal connections to the AT-MIO-64F-5, and cable considerations.

¥ Chapter 3, Theory of Operation, contains a functional overview of the AT-MIO-64F-5 and

explains the operation of each functional unit making up the AT-MIO-64F-5.

¥ Chapter 4, Register Map and Descriptions, describes in detail the address and function of

each of the AT-MIO-64F-5 control and status registers.

¥ Chapter 5, Programming, contains programming instructions for operating the circuitry on

the AT-MIO-64F-5.

¥ Chapter 6, Calibration Procedures, discusses the calibration resources and procedures for the

AT-MIO-64F-5 analog input and analog output circuitry.

¥ Appendix A, Specifications, lists the specifications of the AT-MIO-64F-5.

¥ Appendix B, AT-MIO-64F-5 I/O Connector, describes the pinout and signal names for the

AT-MIO-64F-5 100-pin I/O connector.

¥ Appendix C, MIO SubConnector, describes the pinout and signal names for the

AT-MIO-64F-5 50-pin MIO subconnector.

¥ Appendix D, Extended Analog Input SubConnector, describes the pinout and signal names

for the 50-pin extended analog input subconnector of the AT-MIO-64F-5.

¥ Appendix E, AMD Am9513A Data Sheet, contains the manufacturer data sheet for the AMD

Am9513A System Timing Controller integrated circuit (Advanced Micro Devices, Inc.). This controller is used on the AT-MIO-64F-5.

¥ Appendix F, Customer Communication, contains forms you can use to request help from

National Instruments or to comment on our products and manuals.

¥ The Index contains an alphabetical list of key terms and topics in this manual, including the

page where each one can be found.

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Preface

Conventions Used in This Manual

The following conventions are used in this manual.

italic Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

NI-DAQ NI-DAQ is used throughout this manual to refer to the NI-DAQ software

for DOS/Windows/LabWindows unless otherwise noted.

PC PC refers to the IBM PC AT and compatible computers, and to EISA

personal computers.

Abbreviations

The following metric system prefixes are used with abbreviations for units of measure in this manual:

Prefix Meaning Value

p- pico- 10 n- nano- 10

µ- micro- 10

m- milli- 10

k- kilo- 10

M- mega- 10

G- giga- 10

The following abbreviations are used in this manual:

A amperes dB decibels ft feet F farads hex hexadecimal Hz hertz ksamples 1,000 samples M megabytes of memory m meters W ohms % percent ppm parts per million rms root mean square sec seconds V volts Vref reference voltage Vrms volts, root mean square

-12

-9

-6

-3

AT-MIO-64F-5 User Manual vi © National Instruments Corporation

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Acronyms

The following acronyms are used in this manual:

AC alternating current A/D analog-to-digital ADC analog-to-digital converter AWG American Wire Gauge BCD binary-coded decimal CPU central processing unit D/A digital-to-analog DAC digital-to-analog converter DC direct current DIFF differential DIO digital input/output DIP dual inline package DMA direct memory access DNL differential nonlinearity EEPROM electrically erased programmable read-only memory EISA Extended Industry Standard Architecture FIFO first-in-first-out HCT high-speed CMOS TTL-compatible INL integral nonlinearity I/O input/output LED light-emitting diode LSB least significant bit MSB most significant bit NRSE nonreferenced single-ended PGIA programmable gain instrumentation amplifier RSE referenced single-ended RTSI Real-Time System Integration SCXI Signal Conditioning eXtension Interface SDK Software Developers kit TTL transistor-transistor logic VDC volts direct current

Preface

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix F, Customer

Communication, at the end of this manual.

AT-MIO-64F-5 User Manual viii © National Instruments Corporation

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Chapter 1 Introduction

Board Description..........................................................................................................1-1

Chapter 2 Configuration and Installation

Board Configuration......................................................................................................2-1

Analog Input Configuration...........................................................................................2-6

Analog Output Configuration........................................................................................2-9

Digital I/O Configuration...............................................................................................2-10

Board and RTSI Clock Configuration...........................................................................2-10

Hardware Installation.....................................................................................................2-10

Signal Connections........................................................................................................2-11

..........................................................................................................................1-1

Analog Input......................................................................................................1-1

Analog Output....................................................................................................1-1

Digital and Timing I/O.......................................................................................1-2

What Your Kit Should Contain..........................................................................1-3

Optional Software..............................................................................................1-3

Optional Equipment...........................................................................................1-4

Custom Cables...................................................................................................1-5

Unpacking..........................................................................................................1-6

.......................................................................................2-1

AT Bus Interface................................................................................................2-3

Base I/O Address Selection................................................................................2-3

Interrupt and DMA Channel Selection..............................................................2-5

Input Mode.........................................................................................................2-6

DIFF Input (32 Channels)......................................................................2-6

RSE Input (64 Channels).......................................................................2-7

NRSE Input (64 Channels)....................................................................2-7

Input Polarity and Input Range..........................................................................2-8

Considerations for Selecting Input Ranges............................................2-8

Analog Output Reference Selection...................................................................2-9

Analog Output Polarity Selection......................................................................2-9

MIO Subconnector Signal Connection Descriptions.........................................2-14

Extended Analog Input Subconnector Signal Descriptions..............................2-18

Types of Signal Sources.....................................................................................2-20

Floating Signal Sources.........................................................................2-20

Ground-Referenced Signal Sources.......................................................2-20

Input Configurations..........................................................................................2-20

Differential Connection Considerations (DIFF Input Configuration)...2-21

Differential Connections for Ground-Referenced Signal Sources.........2-22

Differential Connections for Nonreferenced or Floating Signal

Sources...................................................................................................2-23

Single-Ended Connection Considerations.............................................2-24

Single-Ended Connections for Floating Signal Sources (RSE

Configuration)........................................................................................2-25

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Contents

Single-Ended Connections for Grounded Signal Sources (NRSE

Configuration)........................................................................................2-26

Common-Mode Signal Rejection Considerations..................................2-26

Analog Output Signal Connections....................................................................2-27

Digital I/O Signal Connections..........................................................................2-28

Power Connections............................................................................................2-30

Timing Connections...........................................................................................2-30

Data Acquisition and Analog Output Timing Connections...................2-30

General-Purpose Timing Signal Connections........................................2-33

Field Wiring Considerations..........................................................................................2-37

Cabling Considerations..................................................................................................2-38

Chapter 3 Theory of Operation

Functional Overview......................................................................................................3-1

PC I/O Channel Interface Circuitry...............................................................................3-2

Analog Input and Data Acquisition Circuitry................................................................3-4

Analog Input Circuitry.......................................................................................3-6

A/D Converter........................................................................................3-6

Analog Input Multiplexers.....................................................................3-6

Analog Input Configuration...................................................................3-6

PGIA......................................................................................................3-6

ADC FIFO Buffer..................................................................................3-7

Analog Input Calibration.......................................................................3-7

Data Acquisition Timing Circuitry....................................................................3-8

Single-Read Timing...............................................................................3-8

Single-Channel Data Acquisition Timing..............................................3-8

Multiple-Channel Data Acquisition...................................................................3-10

Continuous Scanning Data Acquisition Timing....................................3-11

Interval Scanning Data Acquisition Timing..........................................3-12

Data Acquisition Rates...........................................................................3-12

Analog Output and Timing Circuitry.............................................................................3-12

Analog Output Circuitry........................................................................3-13

Analog Output Configuration................................................................3-14

Analog Output Calibration.....................................................................3-14

DAC Waveform Generation Timing and Circuitry...........................................3-14

DAC Waveform Circuitry......................................................................3-15

DAC Waveform Timing Circuitry.........................................................3-16

FIFO Continuous Cyclic Waveform Generation...................................3-17

FIFO Programmed Cyclic Waveform Generation.................................3-18

FIFO Pulsed Waveform Generation......................................................3-18

Digital I/O Circuitry.......................................................................................................3-19

Timing I/O Circuitry......................................................................................................3-20

RTSI Bus Interface Circuitry.........................................................................................3-23

..........................................................................................................3-1

Chapter 4 Register Map and Descriptions

Register Map..................................................................................................................4-1

AT-MIO-64F-5 User Manual x © National Instruments Corporation

......................................................................................4-1

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Contents

Configuration and Status Register Group..........................................................4-4

Command Register 1..............................................................................4-5

Command Register 2..............................................................................4-8

Command Register 3..............................................................................4-11

Command Register 4..............................................................................4-16

Status Register 1.....................................................................................4-19

Status Register 2.....................................................................................4-22

Analog Input Register Group.............................................................................4-23

ADC FIFO Register...............................................................................4-24

CONFIGMEM Register.........................................................................4-26

Analog Output Register Group..........................................................................4-31

DAC0 Register.......................................................................................4-33

DAC1 Register.......................................................................................4-34

ADC Event Strobe Register Group....................................................................4-35

CONFIGMEMCLR Register.................................................................4-36

CONFIGMEMLD Register....................................................................4-37

DAQ Clear Register...............................................................................4-38

DAQ Start Register................................................................................4-39

Single Conversion Register....................................................................4-40

DAC Event Strobe Register Group....................................................................4-41

TMRREQ Clear Register.......................................................................4-42

DAC Update Register............................................................................4-43

DAC Clear Register...............................................................................4-44

General Event Strobe Register Group................................................................4-45

DMA Channel Clear Register................................................................4-46

DMATCA Clear Register......................................................................4-47

DMATCB Clear Register.......................................................................4-48

External Strobe Register........................................................................4-49

Calibration DAC 0 Load Register..........................................................4-50

Am9513A Counter/Timer Register Group ........................................................4-51

Am9513A Data Register........................................................................4-52

Am9513A Command Register...............................................................4-53

Am9513A Status Register......................................................................4-54

Digital I/O Register Group.................................................................................4-55

Digital Input Register.............................................................................4-56

Digital Output Register..........................................................................4-57

RTSI Switch Register Group.............................................................................4-58

RTSI Switch Shift Register....................................................................4-59

RTSI Switch Strobe Register.................................................................4-60

Chapter 5 Programming

Resource Allocation Considerations..............................................................................5-1

Initializing the AT-MIO-64F-5......................................................................................5-2

Programming the Analog Input Circuitry......................................................................5-4

........................................................................................................................5-1

Initializing the Am9513A..................................................................................5-2

Single Conversions Using the SCONVERT or EXTCONV* Signal................5-4

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Contents

Generating a Single Conversion........................................................................5-5

Reading a Single Conversion Result..................................................................5-5

Programming a Single-Channel Data Acquisition Sequence............................5-5

Programming Data Acquisition Sequences with Channel Scanning.............................5-7

Continuous Channel-Scanning Data Acquisition..............................................5-7

Interval Channel-Scanning Data Acquisition....................................................5-8

Data Acquisition Programming Functions.....................................................................5-10

Clearing the Analog Input Circuitry..................................................................5-10

Programming Single Analog Input Channel Configurations.............................5-10

Programming Multiple Analog Input Channel Configurations.........................5-11

Programming the Sample-Interval Counter.......................................................5-11

Programming the Sample Counter(s).................................................................5-12

Programming the Scan-Interval Counter...........................................................5-14

Applying a Trigger.............................................................................................5-15

Servicing the Data Acquisition Operation.........................................................5-16

Resetting the Hardware after a Data Acquisition Operation..............................5-16

Resetting a Single Am9513A Counter/Timer........................................5-16

Programming the Analog Output Circuitry.......................................................5-18

Cyclic Waveform Generation............................................................................5-18

Programmed Cycle Waveform Generation........................................................5-19

Pulsed Cyclic Waveform Generation.................................................................5-21

Waveform Generation Programming Functions................................................5-23

Clearing the Analog Output Circuitry....................................................5-23

Selecting the Internal Update Counter...................................................5-23

Programming the Update-Interval Counter............................................5-23

Programming the Waveform Cycle Counter.........................................5-24

Programming the Waveform Cycle Interval Counter............................5-25

Servicing Update Requests....................................................................5-26

Programming the Digital I/O Circuitry..........................................................................5-26

Programming the Am9513A Counter/Timer.................................................................5-27

RTSI Bus Trigger Line Programming Considerations..................................................5-27

RTSI Switch Signal Connection Considerations...........................................................5-28

Programming the RTSI Switch......................................................................................5-29

Programming DMA Operations.........................................................................5-30

Interrupt Programming.......................................................................................5-31

Chapter 6 Calibration Procedures

Calibration Equipment Requirements............................................................................6-5

Calibration DACs...........................................................................................................6-5

Calibration Channels......................................................................................................6-6

Reference Calibration....................................................................................................6-6

Analog Input Calibration...............................................................................................6-6

Analog Output Calibration.............................................................................................6-7

.....................................................................................................6-1

Appendix A Specifications

Analog Input..................................................................................................................A-1

AT-MIO-64F-5 User Manual xii © National Instruments Corporation

........................................................................................................................A-1

Explanation of Analog Input Specifications......................................................A-2

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Contents

Figures

Figure1-1. AT-MIO-64F-5 Board........................................................................................1-2

Figure2-1. AT-MIO-64F-5 Parts Locator Diagram.............................................................2-2

Figure2-2. Example Base I/O Address Switch Settings......................................................2-3

Figure2-3. AT-MIO-64F-5 I/O Connector..........................................................................2-12

Figure2-4. 50-Pin MIO Subconnector.................................................................................2-13

Figure2-5. Extended Analog Input Subconnector...............................................................2-17

Figure2-6. AT-MIO-64F-5 PGIA........................................................................................2-19

Figure2-7. Differential Input Connections for Ground-Referenced Signals.......................2-22

Figure2-8. Differential Input Connections for Nonreferenced Signals...............................2-23

Figure2-9. Single-Ended Input Connections for Nonreferenced or Floating Signals..........2-25

Figure2-10.Single-Ended Input Connections for Ground-Referenced Signals....................2-26

Figure2-11 Analog Output Connections...............................................................................2-28

Figure2-12.Digital I/O Connections.....................................................................................2-29

Figure2-13.EXTSTROBE* Signal Timing...........................................................................2-30

Figure2-14.EXTCONV* Signal Timing...............................................................................2-31

Figure2-15.EXTTRIG* Signal Timing.................................................................................2-32

Figure2-16.EXTTMRTRIG* Signal Timing........................................................................2-33

Figure2-17.Event-Counting Application with External Switch Gating................................2-34

Figure2-18.Frequency Measurement Application................................................................2-35

Figure2-19.General-Purpose Timing Signals.......................................................................2-36

Figure3-1. AT-MIO-64F-5 Block Diagram.........................................................................3-1

Figure3-2. PC I/O Channel Interface Circuitry Block Diagram..........................................3-3

Figure3-3. Analog Input and Data Acquisition Circuitry Block Diagram..........................3-5

Figure3-4. ADC Conversion Timing...................................................................................3-8

Figure3-5. Single-Channel Posttrigger Data Acquisition Timing.......................................3-9

Figure3-6. Single-Channel Pretrigger Data Acquisition Timing.........................................3-10

Figure3-7. Scanning Posttrigger Data Acquisition Timing.................................................3-11

Figure3-8. Interval Scanning Posttrigger Data Acquisition Timing....................................3-12

Figure3-9. Analog Output Circuitry Block Diagram...........................................................3-13

Figure3-10.Analog Output Waveform Circuitry..................................................................3-15

Figure3-11.Posted DAC Update Timing..............................................................................3-16

Figure3-12.Analog Output Waveform Circuitry..................................................................3-17

Figure3-13.FIFO Cyclic Waveform Generation with Disable.............................................3-17

Figure3-14.FIFO Programmed Cyclic Waveform Timing...................................................3-18

Figure3-15.FIFO Pulsed Waveform Generation Timing......................................................3-18

Figure3-16.Digital I/O Circuitry Block Diagram.................................................................3-19

Figure3-17.Timing I/O Circuitry Block Diagram.................................................................3-20

Figure3-18.Counter Block Diagram.....................................................................................3-21

Figure3-19.RTSI Bus Interface Circuitry Block Diagram....................................................3-23

Figure5-1. Initializing the Am9513A Counter/Timer..........................................................5-3

Figure5-2 Single Conversion Programming.......................................................................5-4

Figure5-3. Single-Channel Data Acquisition Programming................................................5-6

Figure5-4. Continuous Scanning Data Acquisition Programming......................................5-8

Figure5-5. Interval Scanning Data Acquisition Programming............................................5-9

AT-MIO-64F-5 User Manual xiv © National Instruments Corporation

Page 15

Contents

Figure5-6. Resetting an Am9513A Counter/Timer.............................................................5-17

Figure5-7. Cyclic Waveform Programming........................................................................5-19

Figure5-8. Programmed Cycle Waveform Programming....................................................5-20

Figure5-9. Pulsed Cyclic Waveform Programming............................................................5-22

Figure5-10.RTSI Switch Control Pattern.............................................................................5-29

Figure6-1. AT-MIO-64F-5 EEPROM Map.........................................................................6-1

Figure6-2. Revision and Subrevision Field.........................................................................6-3

Figure6-3. Configuration Memory Depth Field..................................................................6-3

Figure6-4. ADC and DAC FIFO Depth Field.....................................................................6-4

Figure6-5. Area Information Field.......................................................................................6-4

FigureB-1. AT-MIO-64F-5 I/O Connector..........................................................................B-2

FigureC-1. 50-Pin MIO Subconnector.................................................................................C-1

FigureD-1. Extended Analog Input Subconnector...............................................................D-1

Tables

Table1-1. Optional Equipment...........................................................................................1-4

Table2-1. Default Settings of National Instruments Products for the PC..........................2-4

Table2-2. Switch Settings with Corresponding Base I/O Address and Base I/O

Address Space....................................................................................................2-5

Table2-3. Available Input Configurations for the AT-MIO-64F-5....................................2-6

Table2-4. Actual Range and Measurement Precision Versus Input Range Selection

and Gain.............................................................................................................2-9

Table2-5. Recommended Input Configurations for Ground-Referenced and

Floating Signal Sources.....................................................................................2-21

Table4-1. AT-MIO-64F-5 Register Map............................................................................4-1

Table4-2. DMA Channel Selection....................................................................................4-10

Table4-3. DMA and Interrupt Modes.................................................................................4-13

Table4-4. Interrupt Level Selection....................................................................................4-15

Table4-5. Board and RTSI Clock Selection.......................................................................4-16

Table4-6. Analog Output Waveform Modes......................................................................4-17

Table4-7. Straight Binary Mode A/D Conversion Values.................................................4-25

Table4-8. Two’s Complement Mode A/D Conversion Values..........................................4-25

Table4-9. Input Configuration............................................................................................4-26

Table4-10.Calibration Channels ........................................................................................4-27

Table4-11.Extended Analog Input Connections ................................................................4-30

Table4-12.Analog Output Voltage Versus Digital Code (Unipolar Mode)........................4-31

Table4-13.Analog Output Voltage Versus Digital Code (Bipolar Mode)..........................4-32

Table5-1. Am9513A Counter/Timer Allocations...............................................................5-1

Table5-2. RTSI Switch Signal Connections.......................................................................5-28

Page 16

Page 17

Chapter 1 Introduction

This chapter describes the AT-MIO-64F-5, lists the contents of your AT-MIO-64F-5 kit, the optional software and optional equipment, and explains how to unpack the AT-MIO-64F-5.

Board Description

Analog Input

The AT-MIO-64F-5 is a high-performance multifunction analog, digital, and timing I/O board for the PC. The AT-MIO-64F-5 has a 5 µsec, 12-bit sampling ADC that can monitor a single input channel, or scan through the 64 single-ended or 32 differential channels (expandable with National Instruments multiplexing products) at a programmable gain of 0.5, 1, 2, 5, 10, 20, 50, or 100 for unipolar or bipolar input ranges. A 512-word ADC FIFO buffer can perform seamless data acquisition at the maximum rate without data loss. Internal or external triggering and sampling are supported. If signal conditioning or additional analog inputs are required, you can use the SCXI signal conditioning modules, SCXI multiplexer products, or the AMUX-64T multiplexer board.

You can use the NI-DAQ software included with the AT-MIO-64F-5 to calibrate the analog input circuitry. This software adjusts the offset and gain errors to zero by means of board-level calibration DACs. You can store calibration DAC constants resulting from the calibration procedure in the onboard EEPROM for later use. See Chapter 6, Calibration Procedures, for additional information on calibration procedures for the AT-MIO-64F-5.

Analog Output

The AT-MIO-64F-5 also has two double-buffered multiplying 12-bit DACs that may be configured for a unipolar or bipolar voltage output range. An onboard +10 V reference is the internal reference to the circuitry of the DAC. A 2,048-word DAC FIFO buffer allows seamless waveform generation at the maximum rate without data loss. The DAC FIFO can perform cyclic waveform generation directly from the FIFO, independent of the PC interface. You can use the analog output circuitry for internal timer and external signal update capability for waveform generation.

You calibrate the analog output circuitry through the NI-DAQ software provided with the board. This software adjusts the DAC offset and gain errors of each channel to zero by means of boardlevel calibration DACs. Calibration DAC constants resulting from the calibration procedure may be stored in the onboard EEPROM for later use. See Chapter 6, Calibration Procedures, for additional information on calibration procedures for the AT-MIO-64F-5.

Page 18

Introduction Chapter 1

Digital and Timing I/O

In addition to the analog input and analog output capabilities of the AT-MIO-64F-5, the AT-MIO-64F-5 also has eight digital I/O lines that can sink up to 24 mA of current, and three independent 16-bit counter/timers for frequency counting, event counting, and pulse output applications. The AT-MIO-64F-5 has timer-generated interrupts, a high-performance RTSI bus interface, and four triggers for system-level timing.

Figure 1-1 shows the AT-MIO-64F-5 board.

This art not available in PDF version of this document.

Figure 1-1. AT-MIO-64F-5 Board

You can use the AT-MIO-64F-5 with its multifunction analog, digital, and timing I/O in many applications, including machine and process control automation, level monitoring and control, instrumentation, electronic testing, and many others. You can use the multichannel analog input for signal and transient analysis, data logging, and chromatography. The two analog output channels are useful for machine and process control, analog function generation, 12-bit resolution voltage source, and programmable signal attenuation. You can use the eight TTL-compatible digital I/O lines for machine and process control, intermachine communication, and relay switching control. The three 16-bit counter/timers are useful for such functions as pulse and clock generation, timed control of laboratory equipment, and frequency, event, and pulse width measurement. With all these functions on one board, you can automatically monitor and control laboratory processes.

The AT-MIO-64F-5 is interfaced to the National Instruments RTSI bus. With this bus, National Instruments AT Series boards can send timing signals to each other. The AT-MIO-64F-5 can send signals from the onboard counter/timer to another board, or another board can control single and multiple A/D conversions on the AT-MIO-64F-5.

Detailed specifications for the AT-MIO-64F-5 are listed in Appendix A, Specifications.

AT-MIO-64F-5 User Manual 1-2 © National Instruments Corporation

Page 19

Chapter 1 Introduction

What Your Kit Should Contain

The contents of the AT-MIO-64F-5 kit (part number 776655-01) are listed as follows.

Kit Component Part Number

AT-MIO-64F-5 board

AT-MIO-64F-5 User Manual

NI-DAQ software for DOS/Windows/LabWindows, with manuals

NI-DAQ Software Reference Manual for DOS/Windows/LabWindows NI-DAQ Function Reference Manual for DOS/Windows/LabWindows

If your kit is missing any of the components, contact National Instruments.

Your AT-MIO-64F-5 is shipped with the NI-DAQ software for DOS/Windows/LabWindows. NI-DAQ has a library of functions that can be called from your application programming environment. These functions include routines for analog input (A/D conversion), buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion), waveform generation, digital I/O, counter/timer, SCXI, RTSI, and self-calibration. NI-DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code. NI-DAQ comes with language interfaces for Professional BASIC, Turbo Pascal, Turbo C, Turbo C++, Borland C++, and Microsoft C for DOS; and Visual Basic, Turbo Pascal, Microsoft C with SDK, and Borland C++ for Windows. NI-DAQ software is on high-density 5.25 in. and 3.5 in. diskettes.

181395-01 320487-01 776250-01 320498-01 320499-01

Optional Software

This manual contains complete instructions for directly programming the AT-MIO-64F-5. Normally, however, you should not need to read the low-level programming details in the user manual because the NI-DAQ software package for controlling the AT-MIO-64F-5 is included with the board. Using NI-DAQ is quicker and easier than and as flexible as using the low-level programming described in Chapter 5, Programming.

You can use the AT-MIO-64F-5 with LabVIEW for Windows or LabWindows for DOS. LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications. LabVIEW uses graphical programming, whereas LabWindows enhances Microsoft C and QuickBASIC. Both packages include extensive libraries for data acquisition, instrument control, data analysis, and graphical data presentation.

Part numbers for these software packages are listed in the following table.

Page 20

Introduction Chapter 1

Software Part Number

LabVIEW for Windows LabWindows

Standard package Advanced Analysis Library Standard package with the Advanced Analysis Library

Optional Equipment

Table 1-2. Optional Equipment

Equipment Part Number

CB-100 I/O connector block

0.5-m cable

1.0-m cable

Type NB5 100-conductor ribbon cable

0.5-m cable

1.0-m cable

SCXI signal conditioning chassis

SCXI-1000 4-slot chassis SCXI-1001 12-slot chassis

SCXI signal conditioning modules

SCXI-1100 32-channel differential multiplexer/amplifier SCXI-1120 8-channel isolated analog input SCXI-1121 4-channel isolated transducer amplifier with excitation SCXI-1140 8-channel simultaneously sampling differential amplifier SCXI-1180 feedthrough panel SCXI-1181 breadboard

AMUX-64T analog multiplexer board without cable

with 0.2-m ribbon cable with 0.5-m ribbon cable with 1.0-m ribbon cable with 2.0-m ribbon cable

AT Series RTSI bus cables for

2 boards 3 boards 4 boards 5 boards

776670-01

776473-01 776474-01 776475-01

776455-01 776455-02

181304-05 181304-10

776570-XX 776571-XX

776572-00 776572-20 776572-21 776572-40 776572-80 776572-81 776366-90 776366-02 776366-05 776366-10 776366-20

776249-02 776249-03 776249-04 776249-05

(continues)

AT-MIO-64F-5 User Manual 1-4 © National Instruments Corporation

Page 21

Chapter 1 Introduction

Table 1-2. Optional Equipment (Continued)

Equipment Part Number

Cable adapter board for signal conditioning

SC-2050 without cable

SC-2060 optically isolated digital input board with conductor cable 0.2 m

0.4 m

SC-2061 optically isolated digital output board

with 26-conductor cable 0.2 m

0.4 m

SC-2062 electromechanical relay digital control board

with 26-conductor cable 0.2 m

0.4 m

General-purpose termination breadboard

SC-2070 without cable SC-2072 without cable

SC-2072D without cable BNC-2080 BNC adapter board without cable Digital signal conditioning modules

SSR Series mounting rack and 1.0 m cable

8-channel with SC-205X cable

776336-10

776336-01 776336-11

776336-02 776336-12

776358-90 776358-92 776358-192 776579-90

776290-18

Custom Cables

The AT-MIO-64F-5 I/O connector is a 100-pin male ribbon-cable header. The manufacturer part number for this header is as follows:

¥ Robinson Nugent (part number P50E-100P1-SR1-TG)

The mating connector for the AT-MIO-64F-5 is a 100-position polarized ribbon socket connector. This connector breaks out into two 50-pin female connectors with 50-conductor ribbon cables via a cable assembly. National Instruments uses a keyed connector to prevent inadvertent upside-down connection to the AT-MIO-64F-5. The recommended manufacturer part number for this mating connector is as follows:

¥ Robinson Nugent (part number P25E-100-5-TG)

Figure 1-2 shows the AT-MIO-64F-5 cable assembly.

Page 22

Introduction Chapter 1

50-Pin MIO

Subconnector

AT-MIO-64F-5 Board

Extended Analog Input

50-Pin Subconnector

100-Pin Primary

AT-MIO-64F-5

I/O Connector

Figure 1-2. AT-MIO-64F-5 Cable Assembly

Recommended manufacturer part numbers for the standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with these connectors are as follows:

¥ Electronic Products Division/3M (part number 3365/50)

¥ T&B/Ansley Corporation (part number 171-50)

You can plug a polarizing key into these edge connectors to prevent inadvertent upside-down connection to the I/O module rack. The location of this key varies from rack to rack. Consult the specification for the rack you intend to use for the location of any polarizing key. The recommended manufacturer part numbers for this polarizing key are as follows:

¥ Electronic Products Division/3M (part number 3439-2)

¥ T&B Ansley Corporation (part number 609-0005)

Unpacking

Your AT-MIO-64F-5 board is shipped in an antistatic package to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, take the following precautions:

¥ Touch the antistatic package to a metal part of your PC chassis before removing the board

from the package.

¥ Remove the board from the package and inspect the board for loose components or any other

sign of damage. Notify National Instruments if the board appears damaged in any way. Do

not install a damaged board into your computer.

AT-MIO-64F-5 User Manual 1-6 © National Instruments Corporation

Page 23

Chapter 2 Configuration and Installation

This chapter explains the board configuration, installation of the AT-MIO-64F-5 into the PC, signal connections to the AT-MIO-64F-5, and cable considerations.

Board Configuration

The AT-MIO-64F-5 contains one DIP switch to configure the base address selection for the AT bus interface. The remaining resource selections, such as DMA and interrupt channel selections, are determined by programming the individual registers in the AT-MIO-64F-5 register set. The general location of the registers in the I/O space of the PC is determined by the base address selection, whereas the specific location of the registers within the register set is determined by the AT-MIO-64F-5 decode circuitry. Figure 2-1 shows the parts locator diagram of the AT-MIO-64F-5 board.

Page 24

Configuration and Installation Chapter 2

This art not available in PDF version of this document.

Figure 2-1. AT-MIO-64F-5 Parts Locator Diagram

AT-MIO-64F-5 User Manual 2-2 © National Instruments Corporation

Page 25

Chapter 2 Configuration and Installation

AT Bus Interface

Operation of the AT-MIO-64F-5 multifunction I/O board is controlled through accesses to registers within the board register set. Some of the registers in the register set retain data written to them to determine board operation. Other registers in the register set contain important status information necessary for the proper sequencing of events. Still other registers perform functions by accessing them either by reading from or writing to their location. However, these registers do not retain pertinent data when written to, nor do they provide pertinent status information when read.

The PC defines accesses to plug-in boards to be I/O mapped accesses within the I/O space of the computer. Locations are either written to or read from as bytes or words. Each register in the register set is mapped to a certain offset from the base address selection of the board as read or write, and as a word or byte location as defined by the decode circuitry.

Base I/O Address Selection

The AT-MIO-64F-5 is configured at the factory to a base I/O address of 220 hex. This base address setting is suitable for most systems. However, if your system has other hardware at this base I/O address, you must change either the AT-MIO-64F-5 base address DIP switch or the other hardware base address to avoid a conflict. Figure 2-2 shows a graphical representation of the base address selection DIP switch, and also shows how to reconfigure the selected base address.

U104

1234 5

Switch up for 1

Switch down for 0

A. Switches Set to Base I/O Address of Hex 000

Switch up for 1

Switch down for 0

B. Switches Set to Base I/O Address of Hex 220 (Factory Setting)

O N

O F F

U104

1234 5

O N

O F F

Figure 2-2. Example Base I/O Address Switch Settings

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Configuration and Installation Chapter 2

The base address DIP switch is arranged so that a logical 1 or true state for the associated address selection bit is selected by pushing the toggle switch up, or toward the top of the board. Alternately, a logical 0 or false state is selected by pushing the toggle switch down, or toward the bottom of the board. In Figure 2-2B, A9 is up (true), A8 through A6 are down (false), and A5 is up (true). This represents a binary value of 10001XXXXX, or hex 220. The Xs indicate don't care bits and are the five least significant bits (LSBs) of the address (A4 through A0) used by the AT-MIO-64F-5 circuitry to decode the individual register selections. The don't care bits indicate the size of the register space. In this case, the AT-MIO-64F-5 uses I/O address hex 220 through hex 23F in the factory-default setting.

Note: If you change the AT-MIO-64F-5 base I/O address, you must make a corresponding

change to any software packages you use with the AT-MIO-64F-5. Table 2-1 lists the default settings of other National Instruments products for the PC. Table 2-2 lists the possible switch settings, the corresponding base I/O address, and the base I/O address space used for that setting. For more information about the I/O address of your PC, refer to the technical reference manual for your computer.

Table 2-1. Default Settings of National Instruments Products for the PC

Board DMA Channel Interrupt Level Base I/O Address

AT-A2150 AT-AO-6/10 AT-DIO-32F AT-DSP2200 AT-GPIB AT-MIO-16 AT-MIO-16D AT-MIO-16F-5 AT-MIO-16X AT-MIO-64F-5 GPIB-PCII GPIB-PCIIA GPIB-PCIII Lab-PC PC-DIO-24 PC-DIO-96 PC-LPM-16 PC-TIO-10

None* Channel 5 Channels 5, 6 None* Channel 5 Channels 6, 7 Channels 6, 7 Channels 6, 7 None* None* Channel 1 Channel 1 Channel 1 Channel 3 None None None None

None* Lines 11, 12 Lines 11, 12 None* Line 11 Line 10 Lines 5, 10 Line 10 None* None* Line 7 Line 7 Line 7 Line 5 Line 5 Line 5 Line 5 Line 5

* These settings are software configurable and are disabled at startup time.

120 hex 1C0 hex 240 hex 120 hex 2C0 hex 220 hex 220 hex 220 hex 220 hex 220 hex 2B8 hex 02E1 hex 280 hex 260 hex 210 hex 180 hex 260 hex 1A0 hex

AT-MIO-64F-5 User Manual 2-4 © National Instruments Corporation

Page 27

Chapter 2 Configuration and Installation

Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space

Switch Setting

A9 A8 A7 A6 A5

0 0 XXX 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

Base I/O Address

(hex)

000 - E00

100 120 140 160 180

1A0

1C0 1E0

200 220 240 260 280

2A0

2C0 2E0

300 320 340 360 380

3A0

3C0 3E0

Base I/O Address Space

Used (hex)

Reserved 100 - 11F 120 - 13F 140 - 15F 160 - 17F 180 - 19F

1A0 - 1BF 1C0 - 1DF

1E0 - 1FF

200 - 21F 220 - 23F 240 - 25F 260 - 27F 280 - 29F

2A0 - 2BF 2C0 - 2DF

2E0 - 2FF

300 - 31F 320 - 33F 340 - 35F 360 - 37F 380 - 39F

3A0 - 3BF 3C0 - 3DF

3E0 - 3FF

Interrupt and DMA Channel Selection

The base I/O address selection is the only resource on the AT-MIO-64F-5 board that must be set manually before the board is placed into the PC. The interrupt level and DMA channels used by the AT-MIO-64F-5 are selected via registers in the AT-MIO-64F-5 register set. The AT-MIO-64F-5 powers up with all interrupt and DMA requests disabled. To use the interrupt capability of the AT-MIO-64F-5, an interrupt level must first be selected via register programming, then the specific interrupt mode must be enabled. The same method holds for DMA channel selection. To use the DMA capability of the board, one or two DMA channels must be selected through the appropriate register, then the specific DMA mode must be enabled. It is possible to have interrupt and DMA resources concurrently enabled.

The interrupt lines supported by the AT-MIO-64F-5 hardware are IRQ3, IRQ4, IRQ5, IRQ7, IRQ10, IRQ11, IRQ12, and IRQ15. The DMA channels supported are channels 0 through 3, and channels 5 through 7. If the AT-MIO-64F-5 is used in an AT-type computer, only DMA channels 5 through 7 should be used because these are the only 16-bit channels available. If the board is used in an EISA computer, all channels are capable of 16-bit transfers and can be used.

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Configuration and Installation Chapter 2

The AT-MIO-64F-5 does not use and cannot be configured to use the 8-bit DMA channels 0 through 3 on the PC I/O channel for 16-bit transfers.

Analog Input Configuration

The analog input section of the AT-MIO-64F-5 is software configurable. You can select different analog input configurations by programming the appropriate register in the AT-MIO-64F-5 register set. The following paragraphs describe in detail each of the analog input categories.

Input Mode

The AT-MIO-64F-5 offers three different input modesÐnonreferenced single-ended (NRSE) input, referenced single-ended (RSE) input, and differential (DIFF) input. The single-ended input configurations use up to 64 channels. The DIFF input configuration uses up to 32 channels. Input modes are programmed on a per channel basis for multimode scanning. For example, you can configure the circuitry to scan 48 channels (16 differentially configured channels and 32 single-ended channels). The three input configurations are described in Table 2-3.

Table 2-3. Available Input Configurations for the AT-MIO-64F-5

Configuration Description

DIFF Differential configuration has up to 32 differential inputs with the

negative (-) input of the PGIA tied to the multiplexer output of Channels 8 through 15 and 40 through 63.

RSE Referenced single-ended configuration has up to 64 single-ended inputs

with the negative (-) input of the PGIA referenced to analog ground.

NRSE Nonreferenced single-ended configuration has up to 64 single-ended

inputs with the negative (-) input of the PGIA tied to AI SENSE and not connected to ground.

While reading the following paragraphs, you may find it helpful to refer to the Analog Input Signal Connections section later in this chapter, which contains diagrams showing the signal paths for the three configurations.

DIFF Input (32 Channels)

DIFF input means that each input signal has its own reference, and the difference between each signal and its reference is measured. The signal and its reference are assigned an input channel. This is the recommended configuration. With this input configuration, the AT-MIO-64F-5 can monitor up to 32 different analog input signals. This configuration is selected via software. See

AT-MIO-64F-5 User Manual 2-6 © National Instruments Corporation

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Chapter 2 Configuration and Installation

the configuration memory register and Table 4-9 in Chapter 4, Register Map and Descriptions. The results of this configuration are as follows.

¥ One of channels 0 through 7 or 16 through 39 is tied to the positive (+) input of the PGIA.

¥ One of channels 8 through 15 or 40 through 63 is tied to the negative (-) input of the PGIA.

¥ Multiplexer control is configured to control up to 32 input channels.

¥ AI SENSE may be driven by the board analog input ground or left unconnected.

Considerations for using the DIFF input configuration are discussed in the Signal Connections section later in this chapter. Figures 2-7 and 2-8 show schematic diagrams of this configuration.

RSE Input (64 Channels)

RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT-MIO-64F-5 board. The negative (-) input of the differential input amplifier is tied to the analog ground. This configuration is useful when measuring floating signal sources. See the Types of Signal Sources section later in this chapter for more information. With this input configuration, the AT-MIO-64F-5 can monitor up to 64 different analog input signals. This configuration is selected via software. See the configuration memory register and Table 4-9 in Chapter 4, Register Map and Descriptions. The results of this configuration are as follows:

¥ The negative (-) input of the PGIA is tied to the PGIA signal ground.

¥ Multiplexer outputs are tied together into the positive (+) input of the PGIA.

¥ Multiplexer control is configured to control up to 64 input channels.

¥ AI SENSE may be driven by the board analog input ground or left unconnected.

Considerations for using the RSE configuration are discussed in the Signal Connections section later in this chapter. Figure 2-9 shows a schematic diagram of this configuration.

NRSE Input (64 Channels)

NRSE input means that all input signals are referenced to the same common-mode voltage, but this common-mode voltage can float with respect to the analog ground of the AT-MIO-64F-5 board. This common-mode voltage is subsequently subtracted by the input PGIA. This configuration is useful when measuring ground-referenced signal sources. See the Types of

Signal Sources section later in this chapter for more information.

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Configuration and Installation Chapter 2

With this input configuration, the AT-MIO-64F-5 can measure up to 64 different analog input signals. This configuration is selected via software. See the configuration memory register and Table 4-9 in Chapter 4, Register Map and Descriptions, for additional information. The results of this configuration are as follows:

¥ AI SENSE is tied into the negative (-) input of the PGIA.

¥ Multiplexer outputs are tied together into the positive (+) input of the PGIA.

¥ Multiplexer control is configured to control up to 64 input channels.

Note: The NRSE input mode is the only mode in which the AI SENSE signal from the I/O

connector is used as an input. In all other modes, AI SENSE is programmed to be unused or driven with the board analog input ground.

Considerations for using the NRSE input configuration are discussed in the Signal Connections section later in this chapter. Figure 2-10 shows a schematic diagram of this configuration.

Input Polarity and Input Range

The AT-MIO-64F-5 has two polaritiesÐunipolar input and bipolar input. Unipolar input means that the input voltage range is between 0 and V

Bipolar input means that the input voltage range is between -V AT-MIO-64F-5 has a unipolar input range of 10 V, and a bipolar input range of 10 V (±5 V).

Polarity and range settings are programmed on a per channel basis through the configuration memory register.

where V

ref

is a positive reference voltage.

ref

ref /2

and +V

.2/ The

ref

Considerations for Selecting Input Ranges

Input polarity and range selection depend on the expected input range of the incoming signal. A large input range can accommodate a large signal variation but worsens the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range. For best results, the input range should be matched as closely as possible to the expected range of the input signal. For example, if the input signal is certain not to be negative (below 0 V), a unipolar input is best. However, if the signal is negative, inaccurate readings will occur if unipolar input polarity is used.

The software-programmable gain on the AT-MIO-64F-5 increases its overall flexibility by matching the input signal ranges to those that the AT-MIO-64F-5 ADC can accommodate. The AT-MIO-64F-5 board has gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and is suited for a wide variety of signal levels. With the proper gain setting, the full resolution of the ADC can be used to measure the input signal. Table 2-4 shows the overall input range and precision according to the input range configuration and gain used.

AT-MIO-64F-5 User Manual 2-8 © National Instruments Corporation

Page 31

Chapter 2 Configuration and Installation

Table 2-4. Actual Range and Measurement Precision Versus Input Range Selection and Gain

Range Configuration Gain Actual Input Range Precision*

0 to +10 V 1.0

2.0

5.0

10.0

20.0

50.0

100.0

-5 to +5 V 0.5

1.0

2.0

5.0

10.0

20.0

50.0

100.0

* The value of 1 LSB of the 12-bit ADC; that is, the voltage increment

corresponding to a change of 1 count in the ADC 12-bit count.

Note: See Appendix A, Specifications, for absolute maximum ratings.

0 to +10.0 V 0 to +5.0 V 0 to +2.0 V 0 to +1.0 V 0 to +0.5 V 0 to +0.2 V 0 to 100.0 mV

-10.0 to +10.0 V

-5.0 to +5.0 V

-2.5 to +2.5 V

-1.0 to +1.0 V

-0.5 to +0.5 V

-0.25 to +0.25 V

-100.0 to +100.0 mV

-50.0 to +50.0 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

4.88 mV

2.44 mV

1.22 mV

488.28 µV

244.14 µV

122.07 µV

48.83 µV

24.41 µV

Analog Output Configuration

The AT-MIO-64F-5 supplies two channels of analog output voltage at the I/O connector. The analog output circuitry is configurable through programming of a register in the board register set. The reference and range for the analog output circuitry can be selected through software. The reference can be either internal or external, whereas the range can be either bipolar or unipolar.

Analog Output Reference Selection

Each DAC can be connected to the AT-MIO-64F-5 internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I/O connector. This signal applied to EXTREF must be between -10 and +10 V. Both channels need not be configured for the same mode.

Analog Output Polarity Selection

Each analog output channel can be configured for either unipolar or bipolar output. A unipolar configuration has a range of 0 to V

-V

to +V

ref

at the analog output. V

ref

output circuitry and can be either the +10 V onboard reference or an externally supplied reference between -10 and +10 V. Both channels need not be configured for the same range.

at the analog output. A bipolar configuration has a range of

ref

is the voltage reference used by the DACs in the analog

ref

Page 32

Configuration and Installation Chapter 2

Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two's complement format. In two's complement mode, data values written to the analog output channel range from -2,048 to +2,047 decimal (800 to 7FF hex). If unipolar range is selected, data is interpreted in straight binary format. In straight binary mode, data values written to the analog output channel range from 0 to 4,095 decimal (0 to FFF hex).

Digital I/O Configuration

The AT-MIO-64F-5 contains eight lines of digital I/O for general-purpose use. The eight digital I/O lines supplied are configured as two 4-bit ports. Each port can be individually configured through programming of a register in the board register set as either input or output. At system startup and reset, the digital I/O ports are both configured for input.

Board and RTSI Clock Configuration

When multiple AT Series boards are connected via the RTSI bus, you may want all of the boards to use the same 10 MHz clock. This arrangement is useful for applications that require counter/timer synchronization between boards. Each AT Series board with a RTSI bus interface has an onboard 10 MHz oscillator. Thus, one board can drive the RTSI bus clock signal, and the other boards can receive this signal or disconnect from it.

Many functions performed by the AT-MIO-64F-5 board require a frequency timebase to generate the necessary timing signals for controlling ADC conversions, DAC updates, or general-purpose signals at the I/O connector. You select this timebase through programming one of the registers in the AT-MIO-64F-5 register set.

The AT-MIO-64F-5 can use either its internal 10 MHz timebase, or it can use a timebase received over the RTSI bus. In addition, if the board is configured to use the internal timebase, it can also be programmed to drive its internal timebase over the RTSI bus to another board that is programmed to receive this timebase signal. This clock source, whether local or from the RTSI bus, is then divided by 10 and used as the Am9513A frequency source. The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal.

Hardware Installation

You can install the AT-MIO-64F-5 in any available 16-bit expansion slot in your AT Series computer. However, to achieve best noise performance, you should leave as much room as possible between the AT-MIO-64F-5 and other boards and hardware. The AT-MIO-64F-5 does not work if installed in an 8-bit expansion slot (PC Series). After you have made any necessary changes, verified, and recorded the switches and jumper settings (a form is included for this purpose in Appendix F, Customer Communication), you are ready to install the AT-MIO-64F-5.

AT-MIO-64F-5 User Manual 2-10 © National Instruments Corporation

Page 33

Chapter 2 Configuration and Installation

The following are general installation instructions, but consult your PC user manual or technical reference manual for specific instructions and warnings.

1. Turn off your computer.

2. Remove the top cover or access port to the I/O channel.

3. Remove the expansion slot cover on the back panel of the computer.

4. Insert the AT-MIO-64F-5 into a 16-bit slot. Do not force the board into place. Verify that there are no extended components on the circuit board of the computer that may touch or be in the way of any part of the AT-MIO-64F-5.

5. Attach a RTSI cable to the RTSI connectors to connect AT Series boards to each other.

6. Screw the AT-MIO-64F-5 mounting bracket of the to the back panel rail of the computer.

7. Check the installation.

8. Replace the cover.

The AT-MIO-64F-5 board is installed and ready for operation.

Signal Connections

This section describes input and output signal connections to the AT-MIO-64F-5 board via the AT-MIO-64F-5 I/O connector. This section also includes specifications and connection instructions for the signals given on the AT-MIO-64F-5 I/O connector.

The I/O connector contains 100 pins that can be split into two standard 50-pin connectors via a cable assembly such as a Type NB5 ribbon cable (see Figure 1-2). One 50-pin connector contains signals associated with the generic MIO circuitry, whereas the other 50-pin connector contains signals for extended analog input channels.

Figure 2-3 shows the pin assignments for the 100-pin primary AT-MIO-64F-5 I/O connector. Figures 2-4 and 2-5 show the pin assignments for the 50-pin MIO subconnector and the 50-pin extended analog input subconnector. The signal descriptions for pins 1 through 50 of the 100-pin primary connector are the same as those of the MIO subconnector pins and the signal descriptions for pins 51 through 100 of the 100-pin primary connector are the same as the extended analog input subconnector pins.

Warning: Connections that exceed any of the maximum ratings of input or output signals on

the AT-MIO-64F-5 can result in damage to the AT-MIO-64F-5 board and to the PC. Maximum input ratings for each signal are given in this chapter under the discussion of that signal. National Instruments is not liable for any damages resulting from such signal connections.

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Configuration and Installation Chapter 2

ACH16

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1 2 3 4 5 6 7 8 9

100

52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

ACH40 ACH17 ACH41 ACH18 ACH42 ACH19 ACH43 ACH20 ACH44 ACH21 ACH45 ACH22 ACH46 ACH23 ACH47 ACH24 ACH48 ACH25 ACH49 ACH26 ACH50 ACH27 ACH51 AISENSE AIGND ACH28 ACH52 ACH29 ACH53 ACH30 ACH54 ACH31 ACH55 ACH32 ACH56 ACH33 ACH57 ACH34 ACH58 ACH35 ACH59 ACH36 ACH60 ACH37 ACH61 ACH38 ACH62 ACH39 ACH63

AI GND AI GND

ACH0 ACH8 ACH1 ACH9 ACH2

ACH10

ACH3

ACH11

ACH4

ACH12

ACH5

ACH13

ACH6

ACH14

ACH7

ACH15

AI SENSE DAC0 OUT DAC1 OUT

EXTREF

AO GND

DIG GND

ADIO0 BDIO0 ADIO1 BDIO1 ADIO2 BDIO2 ADIO3 BDIO3

DIG GND

+5 V +5 V

SCANCLK

EXTSTROBE*

EXTTRIG*

EXTGATE*

EXTCONV*

SOURCE1

GATE1

OUT1

EXTTMRTRIG*

GATE2

OUT2

SOURCE5

GATE5

OUT5 FOUT

MIO Subconnector

{

Pins

{

Extended Analog Input

Subconnector Pins

Figure 2-3. AT-MIO-64F-5 I/O Connector Pin Assignment

AT-MIO-64F-5 User Manual 2-12 © National Instruments Corporation

Page 35

Chapter 2 Configuration and Installation

MIO Subconnector Pin Assignment

Figure 2-4 shows the pin assignment for the 50-pin MIO subconnector.

AI GND

ACH0

ACH1

ACH2

ACH3

ACH4

ACH5

ACH6

ACH7

AI SENSE

DAC1 OUT

AO GND

ADIO0

ADIO1

ADIO2

ADIO3

DIG GND

+5 V

EXTSTROBE*

EXTGATE*

SOURCE1

OUT1

GATE2

SOURCE5

OUT5

109

1211

1413

1615

1817

2019

2221

2423

2625

2827

3029

3231

3433

3635

3837

4039

4241

4443

4645

4847

5049

AI GND

ACH8

ACH9

ACH10

ACH11

ACH12

ACH13

ACH14

ACH15

DAC0 OUT

EXTREF

DIG GND

BDIO0

BDIO1

BDIO2

BDIO3

+5 V

SCANCLK

EXTTRIG*

EXTCONV*

GATE1

EXTTMRTRIG*

OUT2

GATE5

FOUT

Figure 2-4. 50-Pin MIO Subconnector Pin Assignment

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Configuration and Installation Chapter 2

MIO Subconnector Signal Connection Descriptions

Pin Signal Name Reference Description

1-2 AI GND N/A Analog Input Ground Ð These pins are the

reference point for single-ended measurements and the bias current return point for differential measurements.

3-18 ACH<0..15> AI GND Analog Input Channels 0 through 15 Ð In

the DIFF mode, the input is configured for up to 32 channels, with ACH<0..15> representing differential channels 0 through 7. In the RSE and NRSE modes, the input is configured for up to 64 channels, with ACH<0..15> as channels 0 through 15. ACH<0..15> represents the first eight channels in the differential configuration, and the first 16 channels in the single-ended configuration.

19 AI SENSE AI GND Analog Input Sense Ð This pin serves as

the reference node when the board is in NRSE configuration. If desired, this signal can be programmed to be driven by the board analog input ground in the DIFF and RSE analog input modes.

20 DAC0 OUT AO GND Analog Channel 0 Output Ð This pin

supplies the voltage output of analog output channel 0.

21 DAC1 OUT AO GND Analog Channel 1 Output Ð This pin

supplies the voltage output of analog output channel 1.

22 EXTREF AO GND External Reference Ð This is the external

reference input for the analog output circuitry.

23 AO GND N/A Analog Output Ground Ð The analog

output voltages are referenced to this node.

24, 33 DIG GND N/A Digital Ground Ð This pin supplies the

reference for the digital signals at the I/O connector as well as the +5 VDC supply.

25, 27, 29, 31 ADIO<0..3> DIG GND Digital I/O port A signals.

AT-MIO-64F-5 User Manual 2-14 © National Instruments Corporation

Page 37

Chapter 2 Configuration and Installation

Pin Signal Name Reference Description (continued)

26, 28, 30, 32 BDIO<0..3> DIG GND Digital I/O port B signals.

34, 35 +5 V DIG GND +5 VDC Source Ð These pins are fused for

up to 1 A of +5 V supply.

36 SCANCLK DIG GND Scan Clock Ð This pin pulses once for

each A/D conversion in the scanning modes. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.

37 EXTSTROBE* DIG GND External Strobe Ð Writing to the

EXTSTROBE Register results in a minimum 500-nsec low pulse on this pin.

38 EXTTRIG* DIG GND External Trigger Ð In posttrigger data

acquisition sequences, a high-to-low edge on EXTTRIG* initiates the sequence. In pretrigger applications, the first high-tolow edge of EXTTRIG* initiates pretrigger conversions while the second high-to-low edge initiates the posttrigger sequence.

39 EXTGATE* DIG GND External Gate Ð When EXTGATE* is low,

A/D conversions are inhibited. When EXTGATE* is high, A/D conversions are enabled.

40 EXTCONV* DIG GND External Convert Ð A high-to-low edge on

EXTCONV* causes an A/D conversion to occur. Conversions initiated by the EXTCONV* signal are inhibited outside of a data acquisition sequence, and when gated off.

41 SOURCE1 DIG GND SOURCE1 Ð This pin is from the

Am9513A Counter 1 signal.

42 GATE1 DIG GND GATE1 Ð This pin is from the Am9513A

Counter 1 signal.

43 OUT1 DIG GND OUTPUT1 Ð This pin is from the

Am9513A Counter 1 signal.

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Configuration and Installation Chapter 2

Pin Signal Name Reference Description (continued)

44 EXTTMRTRIG* DIG GND External Timer Trigger Ð If selected, a

high-to-low edge on EXTTMRTRIG* results in the output DACs being updated with the value written to them in the posted update mode. EXTTMRTRIG* will also generate a timed interrupt if enabled.

45 GATE2 DIG GND GATE2 Ð This pin is from the Am9513A

Counter 2 signal.

46 OUT2 DIG GND OUTPUT2 Ð This pin is from the

Am9513A Counter 2 signal.

47 SOURCE5 DIG GND SOURCE5 Ð This pin is from the

Am9513A Counter 5 signal.

48 GATE5 DIG GND GATE5 Ð This pin is from the Am9513A

Counter 5 signal.

49 OUT5 DIG GND OUT5 Ð This pin is from the Am9513A

Counter 5 signal.

50 FOUT DIG GND Frequency Output Ð This pin is from the

Am9513A FOUT signal.

AT-MIO-64F-5 User Manual 2-16 © National Instruments Corporation

Page 39

Chapter 2 Configuration and Installation

Extended Analog Input Subconnector Pin Assignment

Figure 2-5 shows the pin assignment for the 50-pin extended analog subconnector.

ACH17

ACH18

ACH19

ACH20

ACH21

ACH22

ACH23

ACH24

ACH25

ACH26

ACH27

AI SENSE

ACH28

ACH29

ACH30

ACH31

ACH32

ACH33

ACH34

ACH35

ACH36

ACH37

ACH38

ACH39

ACH40ACH16

ACH41

ACH42

ACH43

109

1211

1413

1615

1817

4847

5049

ACH44

ACH45

ACH46

ACH47

ACH48

ACH49

2019

ACH50

2221

ACH51

2423

AI GND

2625

ACH52

2827

ACH53

3029

3231

ACH54

3433

ACH55

ACH56

3635

ACH57

3837

ACH58

4039

ACH59

4241

ACH60

4443

ACH61

4645

ACH62

ACH63

Figure 2-5. Extended Analog Input Subconnector Pin Assignment

Page 40

Configuration and Installation Chapter 2

Extended Analog Input Subconnector Signal Descriptions

Pin Signal Name Reference Description

1-24 ACH<16..27> AI GND Analog Input Channels 16 through 27 and

ACH<40..51>51 AI GND 40 through Ð In the differential mode, the

input is configured for up to 32 channels, with ACH<16..27> and ACH<40..51> representing differential Channels 16 through 27 and 40 through 51. In the RSE and NRSE modes, the input is configured for up to 64 channels with ACH<16..27> as Channels 16 through 27 and ACH<40..51>as Channels 40 through 51.

25 AI SENSE AI GND Analog Input Sense Ð This pin serves as

the reference mode when the board is in NRSE configuration. If desired, this signal can be programmed to be driven by the board analog input ground.

26 AI GND N/A Analog Input Ground Ð These pins are the

reference point for single-ended measurements and the bias current return point for differential measurements.

27-50 ACH<28..39> AI GND Analog Input Channels 28 through 39 and

ACH<52..63>63 AI GND 52 through Ð In the DIFF mode,

ACH<28..39> and ACH<52..63> represent differential Channels 28 through

39. In the RSE and NRSE modes, ACH<28..39> represent Channels 28 through 39, and ACH<52..63> represent Channels 52 through 63.

The signals on the connector are classified as analog input signals. Signal connection guidelines for each of these groups are given in the following section.

Analog Input Signal Connections

Pins 1 through 19 of the MIO subconnector and pins 1 through 50 of the extended analog input subconnector are analog input signal pins. Pins 1 and 2 of the MIO subconnector and pin 26 of the extended analog input subconnector are AI GND signal pins. AI GND is an analog input common signal that is routed directly to the ground tie point on the AT-MIO-64F-5. These pins can be used for a general analog power ground tie point to the AT-MIO-64F-5 if necessary.

Pin 19 of the MIO subconnector and pin 25 of the extended analog input subconnector comprise the AI SENSE signal. In NRSE mode, AI SENSE is connected internally to the negative (-) input of the AT-MIO-64F-5 PGIA. In the DIFF and RSE modes, this signal is driven by AI GND or left unconnected. Each subconnector individually buffers the AI SENSE signal with

AT-MIO-64F-5 User Manual 2-18 © National Instruments Corporation

Page 41

Chapter 2 Configuration and Installation

a 1.2 kW resistor. From either AI SENSE pin to the board, there is 1.2 kW of resistance. However, from the AI SENSE signal at pin 19 to the AI SENSE signal at pin 25, there is 2.4 kW of resistance.

Pins 3 through 18 of the MIO subconnector are ACH<0..15> signal pins, while the remaining ACH<16..63> signal pins are located on the extended analog input subconnector. These pins are tied to the 64 analog input channels of the AT-MIO-64F-5. In single-ended mode, signals connected to ACH<0..63> are routed to the positive (+) input of the AT-MIO-64F-5 PGIA. In differential mode, signals connected to ACH<0..7> and ACH<16..39>are routed to the positive (+) input of the AT-MIO-64F-5 PGIA, and signals connected to ACH<8..15> and ACH<40..63> are routed to the negative (-) input of the AT-MIO-64F-5 PGIA.

Warning: Exceeding the differential and common-mode input ranges results in distorted input

signals. Exceeding the maximum input voltage rating can result in damage to the AT-MIO-64F-5 board and to the PC. National Instruments is not liable for any damages resulting from such signal connections.

Connection of analog input signals to the AT-MIO-64F-5 depends on the configuration of the AT-MIO-64F-5 analog input circuitry and the type of input signal source. With the different AT-MIO-64F-5 configurations, you can use the AT-MIO-64F-5 PGIA in different ways. Figure 2-6 shows a diagram of the AT-MIO-64F-5 PGIA.

Programmable Gain

Gain = 0.5, 1, 2, 5, 10, 20, 50, 100

Vm = [

Gain

- ]

GAIN

Measured Voltage

Figure 2-6. AT-MIO-64F-5 PGIA

The AT-MIO-64F-5 PGIA applies gain and common-mode voltage rejection, and presents highinput impedance to the analog input signals connected to the AT-MIO-64F-5 board. Signals are routed to the positive (+) and negative (-) inputs of the PGIA through input multiplexers on the AT-MIO-64F-5. The PGIA converts two input signals to a signal that is the difference between

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Configuration and Installation Chapter 2

the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the AT-MIO-64F-5 ground. The AT-MIO-64F-5 ADC measures this output voltage when it performs A/D conversions.

All signals must be referenced to ground, either at the source device or at the AT-MIO-64F-5. If you have a floating source, the AT-MIO-64F-5 should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors (see the Differential Connections for Nonreferenced or Floating Signal Sources section later in this chapter). If you have a grounded source, the AT-MIO-64F-5 should not reference the signal to AI GND. The AT-MIO-64F-5 board avoids this reference by using the DIFF or NRSE input configurations.

Types of Signal Sources

When configuring the input mode of the AT-MIO-64F-5 and making signal connections, you must first determine whether the signal source is floating or ground-referenced. These two types of signals are described in the following sections.

Floating Signal Sources

A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolator outputs, and isolation amplifiers. An instrument or device that provides an isolated output falls into the floating signal source category. The ground reference of a floating signal must be tied to the AT-MIO-64F-5 analog input ground in order to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats out of the common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT-MIO-64F-5 board, assuming that the PC AT is plugged into the same power system. Nonisolated outputs of instruments and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected. If a grounded signal source is improperly measured, this difference may show up as an error in the measurement. The following connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal.

Input Configurations

The AT-MIO-64F-5 can be configured for one of three input modesÐNRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements, and considerations for measuring both floating and ground-referenced signal sources. Table 2-5 summarizes the recommended input configuration for both types of signal sources.

AT-MIO-64F-5 User Manual 2-20 © National Instruments Corporation

Page 43

Chapter 2 Configuration and Installation

Table 2-5. Recommended Input Configurations for Ground-Referenced

and Floating Signal Sources

Type of Signal Recommended Input

Configuration

Ground-referenced (nonisolated outputs, plug-in instruments) DIFF

NRSE

Floating (batteries, thermocouples, isolated outputs) DIFF with bias resistors

RSE

Differential Connection Considerations (DIFF Input Configuration)

Differential connections are those in which each AT-MIO-64F-5 analog input signal has its own reference signal or signal return path. These connections are available when the AT-MIO-64F-5 is configured in the DIFF input mode. Each input signal is tied to the positive (+) input of the PGIA, and its reference signal, or return, is tied to the negative (-) input of the PGIA.

When the AT-MIO-64F-5 is configured for differential input, each signal uses two multiplexer inputsÐone for the signal and one for its reference signal. Therefore, with a differential configuration, up to 32 analog input channels are available. Differential input connections should be used when any of the following conditions are present:

¥ You are connecting 32 or fewer signals to the AT-MIO-64F-5.

¥ Input signals are low level (less than 1 V).

¥ Leads connecting the signals to the AT-MIO-64F-5 are greater than 10 ft.

¥ Any of the input signals require a separate ground-reference point or return signal.

¥ The signal leads travel through noisy environments.

Differential signal connections reduce picked-up noise and increase common-mode noise rejection. Differential signal connections also cause input signals to float within the commonmode limits of the PGIA.

Page 44

Configuration and Installation Chapter 2

Differential Connections for Ground-Referenced Signal Sources

Figure 2-7 shows how to connect a ground-referenced signal source to an AT-MIO-64F-5 board configured in the DIFF input mode. The AT-MIO-64F-5 analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions.

ACH<0..7>

ACH<16..39>

GroundReferenced Signal Source

CommonMode Noise, Ground Potential, and so on

ACH<8..15>

ACH<40..63>

Gain

PGIA

Measured Voltage

Input Multiplexers

AI SENSE

AI GND

I/O Connector

AT-MIO-64F-5 Board in the DIFF Input Configuration

Figure 2-7. Differential Input Connections for Ground-Referenced Signals

With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the AT-MIO-64F-5 ground, shown as Vcm in Figure 2-7.

AT-MIO-64F-5 User Manual 2-22 © National Instruments Corporation

Page 45

Chapter 2 Configuration and Installation

Differential Connections for Nonreferenced or Floating Signal Sources

Figure 2-8 shows how to connect a floating signal source to an AT-MIO-64F-5 board configured in the DIFF input mode. The AT-MIO-64F-5 analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4,

ACH<0..7>

ACH<16..39>

Bias Resistors

Floating Signal Source +

PGIA

Gain

Measured

Voltage

Bias Current Return Paths

I/O Connector

ACH<8..15>

ACH<40..63>

Input Multiplexers

AI SENSE

AI GND

AT-MIO-64F-5 Board in the DIFF Input Configuration

Figure 2-8. Differential Input Connections for Nonreferenced Signals

Figure 2-8 shows two bias resistors connected in parallel with the signal leads of a floating signal source. If the source is truly floating, it is not likely to remain within the common-mode signal range of the PGIA, and the PGIA will saturate (causing erroneous readings). You must reference the source to AI GND. The best way is simply to connect the positive side of the signal to the positive (+) input of the PGIA and connect the negative side of the signal to AI GND as well as to the negative (-) input of the PGIA. This works well for DC-coupled sources with low source impedance (less than 100 W). However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise, which couples electrostatically onto the positive (+) line, does not couple onto the negative (-) line because it is connected to ground.

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Configuration and Installation Chapter 2

Hence, this noise appears as a differential-mode signal instead of a common-mode signal, and so the PGIA does not reject it. In this case, instead of directly connecting the negative (-) line to AIÊGND, connect it to AI GND through a resistor that is about 100 times the equivalent source impedance. This puts the signal path nearly in balance, so about the same noise couples onto both (+) and (-) connections, yielding better rejection of electrostatically coupled noise. Also, this configuration does not load down the source (other than the 100-GW input impedance of the PGIA). You can fully balance the signal path by connecting another resistor of the same value between the positive (+) input and AI GND. This fully balanced configuration offers slightly better noise rejection, but has the disadvantage of loading the source down with the series combination (sum) of the two resistors. If, for instance, the source impedance is 2 kW and the two resistors are each 100 kW, the resistors load down the source with 200 kW and produce a 1% gain error.

Both inputs of the PGIA require a DC path to ground in order for the PGIA to work. If the source is AC coupled (capacitively coupled), then the PGIA needs a resistor between the positive (+) input and AI GND. If the source has low impedance, choose a resistor that is large enough not to significantly load the source, but small enough not to produce significant input offset voltage as a result of input bias current (typically 100 kW to 1 MW). If the source has high output impedance, you should balance the signal path (as described above) using the same value resistor on both the positive (+) and negative (-) inputs, and you should be aware that there is some gain error from loading down the source.

The PGIA obtains its input DC bias currents from the DC paths to ground. These currents are typically less than ±200 pA, and do not contribute significantly to error in most applications. If the source is DC coupled, the resulting DC offset is less than 200 pA times the DC source resistance. For instance, a 1 kW source will produce no more than 0.2 µV of input offset (0.01 LSB at a gain of 100). If the source is AC coupled, then the resulting DC offset is less than 200 pA times the sum of the two bias resistors. For example, if two 100 kW bias resistors are used, there could be as much as 40 µV of input offset voltage (1.6 LSB at a gain of 100).

Single-Ended Connection Considerations

Single-ended connections are those in which all AT-MIO-64F-5 analog input signals are referenced to one common ground. The input signals are tied to the positive (+) input of the PGIA, and their common ground point is tied to the negative (-) input of the PGIA.

When the AT-MIO-64F-5 is configured for single-ended input, up to 64 analog input channels are available. Single-ended input connections can be used when all input signals meet the following criteria:

¥ Input signals are high level (greater than 1 V).

¥ Leads connecting the signals to the AT-MIO-64F-5 are less than 15 ft.

¥ All input signals share a common-reference signal (at the source) or are floating.

DIFF input connections are recommended for greater signal integrity if any of the preceding criteria are not met.

AT-MIO-64F-5 User Manual 2-24 © National Instruments Corporation

Page 47

Chapter 2 Configuration and Installation

d g

The AT-MIO-64F-5 can be software configured for two different types of single-ended connectionsÐRSE configuration and NRSE configuration. The RSE configuration is used for floating signal sources; in this case, the AT-MIO-64F-5 provides the reference ground point for the external signal. The NRSE input configuration is used for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the AT-MIO-64F-5 should not supply one.

In single-ended configurations, more electrostatic and magnetic noise couples into the signal connections than in differential configurations. Moreover, the amount of coupling varies among channels, especially if a ribbon cable is used. The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors. Referring to the MIO subconnector, for example, if AI GND is used as the signal reference, Channels 0 and 8 are the quietest and Channels 7 and 15 are the noisiest. AI GND is on pins 1 and 2, which are very close to pins 3 and 4, which are Channels 0 and 1. On the other hand, Channels 7 and 15 are on pins 17 and 18, which are the farthest analog inputs from AI GND. The sensitivities to noise of the other channels in the middle are between those of Channels 0 and 15 and vary according to their distance from AI GND. If AI SENSE is used as a reference instead of AI GND, the sensitivity to noise still varies among the channels, but in this case according to their distance from AI SENSE, pin 19 (so Channel 15 is the least sensitive and Channel 0 is the most sensitive).

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 2-9 shows how to connect a floating signal source to an AT-MIO-64F-5 board configured for single-ended input. The AT-MIO-64F-5 analog input circuitry must be configured for RSE input to make these types of connections. Configuration instructions are included in Chapter 4,

ACH<0..63>

Nonreference

or Floatin

Signal Source

Input Multiplexe

AI SENSE

AI GND

Gain

PGIA

Measured Voltage

AT-MIO-64F-5 Board in the RSE Input Configuration

I/O Connector

Figure 2-9. Single-Ended Input Connections for Nonreferenced or Floating Signals

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Configuration and Installation Chapter 2

e e

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

If a grounded signal source is to be measured with a single-ended configuration, then the AT-MIO-64F-5 must be configured in the NRSE input configuration. The signal is connected to the positive (+) input of the AT-MIO-64F-5 PGIA and the signal local ground reference is connected to the negative (-) input of the AT-MIO-64F-5 PGIA. The ground point of the signal should therefore be connected to the AI SENSE pin. Any potential difference between the AT-MIO-64F-5 ground and the signal ground appears as a common-mode signal at both the positive (+) and negative (-) inputs of the PGIA and this difference is rejected by the amplifier. On the other hand, if the input circuitry of the AT-MIO-64F-5 is referenced to ground, such as in the RSE input configuration, this difference in ground potentials appears as an error in the measured voltage.

Figure 2-10 shows how to connect a grounded signal source to an AT-MIO-64F-5 board configured for nonreferenced single-ended input. The AT-MIO-64F-5 analog input circuitry must be configured for NRSE input configuration to make these types of connections. Configuration instructions are included in Chapter 4, Register Map and Descriptions.

ACH<0..63>

Ground-

Referenced

Signal Source

Common-

Mod Nois

I/O Connector

Input Multiplexer

AI GND

AT-MIO-64F-5 Board in the NRSE Input Configuration

AI SENSE

- V

PGIA

Measured Voltage

Figure 2-10. Single-Ended Input Connections for Ground-Referenced Signals

Common-Mode Signal Rejection Considerations

Figures 2-7 and 2-10, located earlier in this chapter, show connections for signal sources that are already referenced to some ground point with respect to the AT-MIO-64F-5. In these cases, the PGIA can reject any voltage caused by ground potential differences between the signal source and the AT-MIO-64F-5. In addition, with differential input connections, the PGIA can reject common-mode noise pickup in the leads connecting the signal sources to the AT-MIO-64F-5.

AT-MIO-64F-5 User Manual 2-26 © National Instruments Corporation

Page 49

Chapter 2 Configuration and Installation

The common-mode input range of the AT-MIO-64F-5 PGIA is defined as the magnitude of the greatest common-mode signal that can be rejected. The PGIA can reject common-mode signals

as long as V

and V

the AT-MIO-64F-5 depends on the size of the differential input signal (V

are both in the range ±12 V. Thus, the common-mode input range for

diff

= V

- V

). The

exact formula for the allowed common-mode input range is as follows:

cm-max

= ± (12 V - V

diff

/2)

With a differential voltage of 10 V, the maximum possible common-mode voltage is ±7 V. The common-mode voltage is measured with respect to the AT-MIO-64F-5 ground and can be calculated by the following formula:

cm-actual

where V

is the signal at the positive (+) input of the PGIA and V

negative (-) input of the PGIA. Both V

Ê+ÊÊV

)

is the signal at the

and V

are measured with respect to AI GND.

Analog Output Signal Connections

Pins 20 through 23 of the MIO subconnector are analog output signal pins.

Pins 20 and 21 of the MIO subconnector are the DAC0 OUT and DAC1 OUT signal pins. DAC0 OUT is the voltage output signal for analog output Channel 0. DAC1 OUT is the voltage output signal for analog output Channel 1.

Pin 22 of the MIO subconnector, EXTREF, is the external reference input for both analog output channels. Each analog output channel must be configured individually for external reference selection in order for the signal applied at the external reference input to be used by that channel. Analog output configuration instructions are in the Analog Output Configuration section earlier in this chapter.

The following ranges and ratings apply to the EXTREF input:

Normal input voltage range ±10 V peak with respect to AO GND Usable input voltage range ±12 V peak with respect to AO GND Absolute maximum ratings ±30 V peak with respect to AO GND

Pin 23 of the MIO subconnector, AO GND, is the ground-reference point for both analog output channels and for the external reference signal.

Figure 2-11 shows how to make analog output connections and the external reference input connection to the AT-MIO-64F-5 board.

Page 50

Configuration and Installation Chapter 2

EXTREF

DAC0 OUT

AO GND

Channel

External Reference

Signal (Optional)

Load

VOUT 0

VOUT 1

Load

MIO Subconnecto

DAC1 OUT

Channel 1

Analog Output Channels

AT-MIO-64F-5 Board

Figure 2-11. Analog Output Connections

The external reference signal can be either a DC or an AC signal. This reference signal is multiplied by the DAC code to generate the output voltage.

Digital I/O Signal Connections

Pins 24 through 32 of the MIO subconnector are digital I/O signal pins.

Pins 25, 27, 29, and 31 are connected to the digital lines ADIO<0..3> for digital I/O port A. Pins 26, 28, 30, and 32 are connected to the digital lines BDIO<0..3> for digital I/O port B. Pin 24, DIG GND, is the digital ground pin for both digital I/O ports. Ports A and B can be programmed individually to be inputs or outputs.

The following specifications and ratings apply to the digital I/O lines.

Absolute maximum voltage input rating 5.5 V with respect to DIG GND

Digital input specifications (referenced to DIG GND):

input logic high voltage 2 V minimum

input logic low voltage 0.8 V maximum

IIH input current load,

logic high input voltage 40 µA maximum

input current load,

logic low input voltage -120 µA maximum

AT-MIO-64F-5 User Manual 2-28 © National Instruments Corporation

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Chapter 2 Configuration and Installation

Digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

output logic low voltage 0.5 V maximum

output source current, logic high 2.6 mA maximum

output sink current, logic low 24 mA maximum

With these specifications, each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads.

Figure 2-12 depicts signal connections for three typical digital I/O applications.

+5 V

LED

Port A

ADIO<3..0>

+5 V

Switch

TTL Signal

MIO Subconnecto

DIG GND

Port B

BDIO<3..0>

AT-MIO-64F-5 Board

Figure 2-12. Digital I/O Connections

In Figure 2-12, port A is configured for digital output, and port B is configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-12. Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2-12.

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Configuration and Installation Chapter 2

Power Connections

Pins 34 and 35 of the MIO subconnector provide +5 V from the PC power supply. These pins are referenced to DIG GND and can be used to power external digital circuitry.

Power rating 1.0 A at +5 V ± 10%, fused

Warning: Under no circumstances should these +5-V power pins be directly connected to

analog or digital ground or to any other voltage source on the AT-MIO-64F-5 or any other device. Doing so can damage the AT-MIO-64F-5 and the PC. National Instruments is not liable for damages resulting from such a connection.

Timing Connections

Pins 36 through 50 of the MIO subconnector are connections for timing I/O signals. Pins 36 through 40 and pin 44 carry signals used for data acquisition timing and analog output triggering. These signals are explained in the next section, Data Acquisition Timing Connections. Pins 41 through 50 carry general-purpose timing signals and analog output provided by the onboard Am9513A Counter/Timer. These signals are explained in the General-Purpose Timing Signal Connections section later in this chapter.

Data Acquisition and Analog Output Timing Connections

The data acquisition and analog output timing signals are SCANCLK, EXTSTROBE*, EXTTRIG*, EXTGATE*, EXTCONV*, and EXTTMRTRIG*.

SCANCLK Signal

SCANCLK is an output signal that generates a low-to-high edge whenever an A/D conversion begins. SCANCLK pulses only when scanning is enabled on the AT-MIO-64F-5. SCANCLK is normally low and pulses high for approximately 4 µsec after the A/D conversion begins. The low-to-high edge can be used to clock external analog input multiplexers. The SCANCLK signal is driven by one CMOS TTL gate.

EXTSTROBE* Signal

A low pulse of no less than 500 nsec is generated on the EXTSTROBE* pin when the External Strobe Register is accessed. See the External Strobe Register section in Chapter 4, Register Map and Descriptions, for more information. Figure 2-13 shows the timing for the EXTSTROBE* signal.

>500 nsec

Figure 2-13. EXTSTROBE* Signal Timing

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Chapter 2 Configuration and Installation

The pulse width is defined as 500 nsec minimum. The EXTSTROBE* signal can be used by an external device to latch signals or trigger events. The EXTSTROBE* signal is an HCT signal.

EXTCONV* Signal

A/D conversions can be externally triggered with the EXTCONV* pin. Applying an active low pulse to the EXTCONV* signal initiates an A/D conversion. Figure 2-14 shows the timing requirements for the EXTCONV* signal.

ADC switches to hold mode within 100 nsec from this point

50 nsec minimum

Figure 2-14. EXTCONV* Signal Timing

The minimum allowed pulse width is 50 nsec. The ADC switches to hold mode within 100 nsec of the high-to-low edge. This hold mode delay time is a function of temperature and does not vary from one conversion to the next. There is no maximum pulse width limitation. EXTCONV* should be high for at least one conversion period before going low. The EXTCONV* signal is one HCT load and is pulled up to +5 V through a 10 kW resistor.

EXTCONV* is also driven by the output of Counter 3 of the Am9513A Counter/Timer. This counter is also referred to as the sample-interval counter. The output of Counter 3 and the RTSI connection to EXTCONV* must be disabled to a high-impedance state if A/D conversions are to be controlled by pulses applied to the EXTCONV* pin. If Counter 3 is used to control A/D conversions, its output signal can be monitored at the EXTCONV* pin.

A/D conversions generated by either the EXTCONV* signal or the sample-interval counter are inhibited outside of a data acquisition sequence and when gated by either the hardware (EXTGATE*) signal or software command register gate.

Note: EXTCONV* and the output of Counter 3 of the Am9513A are physically connected

together on the AT-MIO-64F-5. If Counter 3 is used in an application, the EXTCONV* signal must be left undriven. Conversely, if EXTCONV* is used in an application, Counter 3 must be disabled.

EXTTRIG* Signal

Any data acquisition sequence can be initiated by an external trigger applied to the EXTTRIG* pin. Applying a falling edge to the EXTTRIG* pin starts the sample and sample-interval counters, thereby initiating a data acquisition sequence. Figure 2-15 shows the timing requirements for the EXTTRIG* signal.

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Configuration and Installation Chapter 2

First A/D conversion starts within 1 sample interval from this point

50 nsec minimum

Figure 2-15. EXTTRIG* Signal Timing

The EXTTRIG* pin is also used to initiate AT-MIO-64F-5 pretriggered data acquisition operations. In pretriggered mode, data is acquired after the first falling edge trigger is received, but no sample counting occurs until after a second falling edge trigger is applied to the EXTTRIG* pin. The acquisition then completes when the sample counter decrements to zero. This mode acquires data both before and after a hardware trigger is received.

The minimum pulse width allowed is 50 nsec. The first A/D conversion starts within one sample interval from the high-to-low edge. The sample interval is controlled by Counter 3 or EXTCONV*. There is no maximum pulse width limitation; however, EXTTRIG* should be high for at least 50Ênsec before going low. The EXTTRIG* signal is one HCT load and is pulled up to +5 V through a 10 kW resistor.

The EXTTRIG* signal is logically ANDed with the internal DAQSTART signal. If a data acquisition sequence is to be initiated with an internal trigger, EXTTRIG* must be high at both the I/O connector and the RTSI switch. If EXTTRIG* is low, the sequence will not be triggered. In addition, triggers from the EXTTRIG* signal can be inhibited through programming of a register in the AT-MIO-64F-5 register set.

EXTGATE* Signal

EXTGATE* is an input signal used for hardware gating. EXTGATE* controls A/D conversion pulses. If EXTGATE* is low, no A/D conversion pulses occur from EXTCONV* or the sample-interval counter. If EXTGATE* is high, conversions take place if programmed and otherwise enabled.

EXTTMRTRIG* Signal

The analog output DACs on the AT-MIO-64F-5 can be updated using either internal or external signals in posted update mode. The DACs can be updated externally by using the EXTTMRTRIG* signal from the I/O connector. This signal updates the DACs when A4RCV is disabled and the appropriate DAC waveform mode is programmed through one of the registers in the AT-MIO-64F-5 register set.

The analog output DACs are updated by the high-to-low edge of the applied pulse. Figure 2-16 shows the timing requirements for the EXTTMRTRIG* signal.

AT-MIO-64F-5 User Manual 2-32 © National Instruments Corporation

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Chapter 2 Configuration and Installation

DACs update 100 nsec from this point

=50 nsec minimum

Figure 2-16. EXTTMRTRIG* Signal Timing

The minimum pulse width allowed is 50 nsec. The DACs are updated within 100 nsec of the high-to-low edge. There is no maximum pulse width limitation. EXTTMRTRIG* should be high for at least 50 nsec before going low. The EXTTMRTRIG* signal is one HCT load and is pulled up to +5 V through a 10 kW resistor.

General-Purpose Timing Signal Connections

The general-purpose timing signals include the GATE and OUT signals for the Am9513A Counters 1, 2, and 5, SOURCE signals for Counters 1 and 5, and the FOUT signal generated by the Am9513A. Counters 1, 2, and 5 of the Am9513A Counter/Timer can be used for generalpurpose applications, such as pulse and square wave generation, event counting, pulse-width, time-lapse, and frequency measurements. For these applications, SOURCE and GATE signals can be directly applied to the counters from the I/O connector. The counters are programmed for various operations.

The Am9513A Counter/Timer is described briefly in Chapter 3, Theory of Operation. For detailed programming information, consult Appendix E, AMD Am9513A Data Sheet. For detailed applications information, consult the Am9513A/Am9513 System Timing Controller technical manual published by Advanced Micro Devices, Inc.

Pulses and square waves can be produced by programming Counter 1, 2, or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count.

For event counting, one of the counters is programmed to count rising or falling edges applied to any of the Am9513A SOURCE inputs. The counter value can then be read to determine the number of edges that have occurred. Counter operation can be gated on and off during event counting.

Figure 2-17 shows connections for a typical event-counting operation in which a switch is used to gate the counter on and off.

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Configuration and Installation Chapter 2

+5 V

4.7 kW

SOURCE

OUT

GATE

Switch

Signal

Source

MIO Subconnector

DIG GND

AT-MIO-64F-5 Board

Counter

Figure 2-17. Event-Counting Application with External Switch Gating

To perform pulse-width measurement, a counter is programmed to be level gated. The pulse to be measured is applied to the counter GATE input. The counter is programmed to count while the signal at the GATE input is either high or low. If the counter is programmed to count an internal timebase, then the pulse width is equal to the counter value multiplied by the timebase period.

For time-lapse measurement, a counter is programmed to be edge gated. An edge is applied to the counter GATE input to start the counter. The counter can be programmed to start counting after receiving either a high-to-low edge or a low-to-high edge. If the counter is programmed to count an internal timebase, then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period.

To measure frequency, a counter is programmed to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input. The gate signal applied to the counter GATE input is of some known duration. In this case, the counter is programmed to count either rising or falling edges at the SOURCE input while the gate is applied. The frequency of the input signal is then the count value divided by the known gate period. Figure 2-18 shows the connections for a frequency measurement application. A second counter can also be used to generate the gate signal in this application.

AT-MIO-64F-5 User Manual 2-34 © National Instruments Corporation

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Chapter 2 Configuration and Installation

+5 V

4.7 kW

SOURCE

OUT

GATE

Signal

Source

MIO Subconnector

Gate

Source

Counter

DIG GND

AT-MIO-64F-5 Board

Figure 2-18. Frequency Measurement Application

Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter. The counters can then be treated as one 32-bit or 48-bit counter for most counting applications.

The signals for Counters 1, 2, and 5, and the FOUT output signal are directly tied from the Am9513A input and output pins to the I/O connector. In addition, the GATE, SOURCE, and OUT1 pins are pulled up to +5 V through a 4.7 kW resistor. The input and output ratings and timing specifications for the Am9513A signals are given as follows:

Absolute maximum voltage input rating -0.5 V to +7.0 V with respect to DIG GND

Am9513A digital input specifications (referenced to DIG GND):

input logic high voltage 2.2 V minimum

input logic low voltage 0.8 V maximum

Input load current ±10 µA maximum

Am9513A digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

output logic low voltage 0.4 V maximum

output source current, at V

output sink current, at V

200 µA maximum

3.2 mA maximum

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Configuration and Installation Chapter 2

Output current, high-impedance state ±25 µA maximum

Figure 2-19 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A.

SOURCE

GATE

OUT

ttt

gsu

t = 145 nsec minimum

= 70 nsec minimum

= 100 nsec minimum

gsu

= 10 nsec minimum

= 145 nsec minimum

= 300 nsec maximu

out

Figure 2-19. General-Purpose Timing Signals

The GATE and OUT signal transitions in Figure 2-19 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, with the source signal inverted and referenced to the falling edge of the source signal, applies to the case in which the counter is programmed to count falling edges.

The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter/timers and by the Am9513A frequency division output FOUT. The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of the Am9513A. The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins.

In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates five internal timebase clocks from the clock signal supplied by the AT-MIO-64F-5. This clock signal is selected by a register in the AT-MIO-64F-5 register set and then divided by 10. The default value is 1 MHz into the Am9513A (10 MHz clock signal on the AT-MIO-64F-5). The five internal timebase clocks can be used as counting sources, and these clocks have a maximum

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Chapter 2 Configuration and Installation

skew of 75 nsec between them. The SOURCE signal shown in Figure 2-19 represents any of the signals applied at the SOURCE inputs, GATE inputs, or internal timebase clocks. See Appendix E, AMD Am9513A Data Sheet, for further details.

Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals. Figure 2-19 shows the GATE signal referenced to the rising edge of a source signal. The gate must be valid (either high or low) at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t

at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge. The gate high or low period must be at least 145 nsec in duration. If an internal timebase clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.

Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals. Figure 2-19 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 300 nsec after the source signal rising or falling edge.

and tgh in Figure 2-19. Similarly, the gate signal must be held for

gsu

Field Wiring Considerations

Accuracy of measurements made with the AT-MIO-64F-5 can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT-MIO-64F-5 board. The following recommendations apply mainly to analog input signal routing to the AT-MIO-64F-5 board, although they are applicable for signal routing in general.

You can minimize noise pickup and maximize measurement accuracy by doing the following:

¥ Use differential analog input connections to reject common-mode noise.

¥ Use individually shielded, twisted-pair wires to connect analog input signals to the

AT-MIO-64F-5. With this type of wire, the signals attached to the CH+ and CH- inputs are twisted together and then covered with a shield. This shield is then connected only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

¥ Route signals to the AT-MIO-64F-5 carefully. Keep cabling away from noise sources. The

most common noise source in a PC data acquisition system is the video monitor. Separate the monitor from the analog signals as much as possible.

The following recommendations apply for all signal connections to the AT-MIO-64F-5:

¥ Separate AT-MIO-64F-5 signal lines from high-current or high-voltage lines. These lines are

capable of inducing currents in or voltages on the AT-MIO-64F-5 signal lines if they run in parallel paths at a close distance. Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel, or by running the lines at right angles to each other.

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Configuration and Installation Chapter 2

¥ Do not run AT-MIO-64F-5 signal lines through conduits that also contain power lines.

¥ Protect AT-MIO-64F-5 signal lines from magnetic fields caused by electric motors, welding

equipment, breakers, or transformers by running the AT-MIO-64F-5 signal lines through special metal conduits.

Cabling Considerations

National Instruments has a cable termination accessory, the CB-100, for use with the AT-MIO-64F-5 board. This kit includes two terminated 50-conductor flat ribbon cables and two CB-50 connector blocks. Signal I/O leads can be attached to screw terminals on the connector block and thereby connected to the AT-MIO-64F-5 I/O connector.

The CB-100 is useful for prototyping an application or in situations where AT-MIO-64F-5 interconnections are frequently changed. When you develop a final field wiring scheme, however, you may want to develop your own cable. This section contains information and guidelines for designing custom cables.

In making your own cabling, you may decide to shield your cables. The following guidelines may help:

¥ For the analog input signals, shielded twisted-pair wires for each analog input pair yield the

best results, assuming that differential inputs are used. Tie the shield for each signal pair to the ground reference at the source.

¥ The analog lines, pins 1 through 23 of the MIO subconnector, should be routed separately

from the digital lines, pins 24 through 50.

¥ When using a cable shield, use separate shields for the analog and digital halves of the cable.

Failure to do so results in noise from switching digital signals coupling into the analog signals.

AT-MIO-64F-5 User Manual 2-38 © National Instruments Corporation

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Chapter 3 Theory of Operation

This chapter contains a functional overview of the AT-MIO-64F-5 and explains the operation of each functional unit making up the AT-MIO-64F-5.

Functional Overview

The block diagram in Figure 3-1 is a functional overview of the AT-MIO-64F-5 board.

Analog

Muxes

Timing

Digital

Output

I/O Connector

Digital

Input

DAC0

DAC1

Voltage

Ref

Ground

REF

Calibration

Mux Mode

Selection

Switches

Dither

DAC Timing Control

DACs

5-Channel

Counter/Timer

DAC FIFO

PGIA

Serial ADC Data

Serial DAC Data

16-Bit

Sampling

A/D

Conversion

Data Acquisition

Conversion Control

Data/Control

ADC Interrupt

ADC FIFO

Timer Interrupt

RTSI Bus

Interface

PC AT

Bus

Interface

Circuitry

DMA

Interface

Interrupt Interface

PC I/O Channel

Calibration

DACs

RTSI Bus

Figure 3-1. AT-MIO-64F-5 Block Diagram

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Theory of Operation Chapter 3

The following major components make up the AT-MIO-64F-5 board:

¥ PC I/O channel interface circuitry

¥ Analog input circuitry

¥ Data acquisition timing circuitry

¥ Analog output and timing circuitry

¥ DAC waveform generation and timing circuitry

¥ Digital I/O circuitry

¥ Timing I/O circuitry

¥ RTSI bus interface circuitry

The internal data and control buses interconnect the components. The theory of operation of each of these components is explained in the remainder of this chapter.

PC I/O Channel Interface Circuitry

The AT-MIO-64F-5 board is a full-size 16-bit PC I/O channel adapter. The PC I/O channel consists of a 24-bit address bus, a 16-bit data bus, a DMA arbitration bus, interrupt lines, and several control and support signals. The components making up the AT-MIO-64F-5 PC I/O channel interface circuitry are shown in Figure 3-2.

AT-MIO-64F-5 User Manual 3-2 © National Instruments Corporation

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Chapter 3 Theory of Operation

Address

Bus

I/O Channel

Control Lines

Data

Bus

PC I/O Channel

DMA Request

DMA

Acknowledge

IRQ

Address

Latches

PC I/O

Channel

Timing

Interface

Data

Buffers

DMA

Control

Circuitry

Interrupt

Control

Circuitry

Address Decoder

Read-and-Write Signals

Internal Data Bus

AT-MIO-64F-5 DMA Request

AT-MIO-64F-5 DMA Acknowledge and Terminal Count

AT-MIO-64F-5 Interrupt Request

Figure 3-2. PC I/O Channel Interface Circuitry Block Diagram

The PC I/O channel interface circuitry consists of address latches, address decoder circuitry, data buffers, PC I/O channel interface timing signals, interrupt circuitry, and DMA arbitration circuitry. The PC I/O channel interface circuitry generates the signals necessary to control and monitor the operation of the AT-MIO-64F-5 multiple-function circuitry.

The PC I/O channel has 24 address lines; the AT-MIO-64F-5 uses 10 of these lines to decode the board address. Therefore, the board address range is 000 to 3FF hex. SA5 through SA9 are used to generate the board enable signal. SA0 through SA4 are used to select individual onboard registers. The address-decoding circuitry generates the register select signals that identify which AT-MIO-64F-5 register is being accessed. The AT-MIO-64F-5 is factory configured for a base address of 220 hex. With this base address, all of the registers on the board will fall into the address range of 220 hex to 23F hex. If this address range conflicts with any other equipment in your PC, you must change the base address of the AT-MIO-64F-5 or of the other device. See Chapter 2, Configuration and Installation, for more information.

The PC I/O channel interface timing signals are used to generate read-and-write signals and to define the transfer cycle size. A transfer cycle can be either an 8-bit or a 16-bit data I/O operation. The AT-MIO-64F-5 returns signals to the PC I/O channel to indicate when the board has been accessed, when the board is ready for another transfer, and the data bit size of the current I/O transfer. You must pay particular attention to the AT-MIO-64F-5 register sizes. An

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Theory of Operation Chapter 3

8-bit access to a 16-bit location, and vice versa, is invalid and will cause sporadic operation. The interrupt control circuitry routes any enabled board-level interrupt requests to the selected interrupt request line. The interrupt requests are tristate output signals that allow the AT-MIO-64F-5 board to share the interrupt line with other devices. Eight interrupt request lines are available for use by the AT-MIO-64F-5ÐIRQ3, IRQ4, IRQ5, IRQ7, IRQ10, IRQ11, IRQ12, and IRQ15. These interrupt levels are selectable from one of the registers in the AT-MIO-64F-5 register set. Six different interrupts can be generated by the AT-MIO-64F-5. Each of the following cases is individually enabled and cleared:

¥ When the ADC FIFO buffer is ready to be serviced

¥ When a data acquisition operation completes (including an OVERFLOW or OVERRUN

error)

¥ When a DMA terminal count pulse is received on DMA channel A or DMA channel B

¥ When the DAC FIFO buffer is ready to be serviced

¥ When a DAC sequence completes (including an UNDERFLOW error)

¥ When a falling edge signal is detected on the DAC update signal (internal or external)

The DMA control circuitry generates DMA requests whenever an A/D measurement is available from the ADC FIFO and when the DAC FIFO is ready to receive more data. The DMA circuitry supports full PC I/O channel 16-bit DMA transfers. DMA channels 5, 6, and 7 of the PC I/O channel are available for such transfers. DMA channels 0, 1, 2, and 3 are available for 16-bit transfers on EISA computers only, and not on PC AT and compatible computers. With the DMA circuitry, either single-channel transfer mode or dual-channel transfer mode can be selected for DMA transfer. These DMA channels are selectable from one of the registers in the AT-MIO-64F-5 register set.

Analog Input and Data Acquisition Circuitry

The AT-MIO-64F-5 handles 64 channels of analog input with software-programmable configuration and 12-bit A/D conversion. In addition, the AT-MIO-64F-5 contains data acquisition configuration for automatic timing of multiple A/D conversions and includes advanced options such as external triggering, gating, and clocking. Figure 3-3 shows a block diagram of the analog input and data acquisition circuitry.

AT-MIO-64F-5 User Manual 3-4 © National Instruments Corporation

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Chapter 3 Theory of Operation

PC I/O Channel

Data

A/D RD

EEPROM

Calibration

Constants

Calibration

Gain

DACs

CHAN_BIP

Out Off

In Off

A/D

Data

ADC

PGIA

CONV AVAIL

Extension

ADC FIFO and Sign

Data

CONFIGMEMWR

Convert

Unipolar

GAIN1

GAIN0

GAIN2

Memory

Channel Configuration

CHAN_LAST

CHANSEL5

CHANSEL<4..0>

Signals

Counter/Timer

CONFIG CLK

Data

Timing

Acquisition

GND

DAC1

Switches

Reference

Selection

Mux Mode

DAC0

SCAN CLK

MUX1OUT

MUX0OUT

CHAN_SE

CHAN_AIS

CHAN_CAL

MUX

External Convert

I/O Connector

ACH0

ACH7

ACH16

ACH31

ACH8

AISENSE

ACH15

ACH40

ACH63

SCANCLK

EXTCONV

Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram

External Trigger

EXTTRIG*

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Theory of Operation Chapter 3

Analog Input Circuitry

The analog input circuitry consists of input multiplexers, multiplexer-mode selection circuitry, a PGIA, calibration circuitry, a 12-bit sampling ADC, and a 16-bit, 512-word-deep FIFO.

A/D Converter

The ADC is a 12-bit, sampling, subranging ADC. With 12-bit resolution, the converter can resolve its input range into 4,096 different steps. This resolution generates a 12-bit digital word that represents the value of the input voltage level with respect to the converter input range. The ADC has two input modes that are software selectable on the AT-MIO-64F-5 board on a per channel basis, -5 to +5 V, or 0 to +10 V. The ADC on the AT-MIO-64F-5 is guaranteed to convert at a rate of at least 200 ksamples/sec.

The data format circuitry is software programmable to generate either straight binary numbers or two's complement numbers. In unipolar mode, values returned from the ADC are straight binary and result in a range of 0 to 4,095. In bipolar mode, the ADC returns two's complement values, resulting in a range of -2,048 to +2,047.

Analog Input Multiplexers

The input multiplexer consists of four dual eight-to-one CMOS analog input multiplexers preceded by input protection resistors, and the input multiplexer has 16 analog input channels. Analog input overvoltage protection is ±25 V powered on and ±15 V powered off. Input signals should be in the range of +10 to -10 V for bipolar operation, and 0 to +10 V for unipolar operation. Bipolar or unipolar mode configuration is programmed on a per channel basis and is controlled through one of the registers in the AT-MIO-64F-5 register set.

Analog Input Configuration

Inputs can be configured for differential or single-ended signals on a per channel basis through a register in the AT-MIO-64F-5 register set. In addition, single-ended inputs can be configured for referenced or nonreferenced signals. In the differential configuration, one of input Channels 0 through 7 or 16 through 39 is routed to the positive input of the PGIA, and one of Channels 8 through 15 or 40 through 63 is routed to the negative input of the PGIA. In the single-ended configuration, one of input Channels 0 through 63 is routed to the positive input of the PGIA. The negative input of the PGIA in single-ended mode is connected to either the input ground or the AI SENSE signal at the I/O connector depending on the software configuration.

PGIA

The PGIA fulfills two purposes on the AT-MIO-64F-5 board. It converts a differential input signal into a single-ended signal with respect to the AT-MIO-64F-5 ground for input common-mode signal rejection. This conversion allows the input analog signal to be extracted from common-mode voltage or noise before being sampled and converted. The PGIA also applies gain to the input signal, amplifying an input analog signal before sampling and conversion to increase measurement resolution and accuracy. Software-selectable gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 are available through the AT-MIO-64F-5 PGIA on a per channel basis.

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Chapter 3 Theory of Operation

Dither Circuitry

When you enable the dither circuitry, you add approximately 0.5 LSB rms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of the AT-MIO-64F-5 to more than 12 bits, as in calibration or spectral analysis. In such applications, noise modulation is decreased and differential linearity is improved by the addition of the dither. For high-speed 12-bit applications not involving averaging or spectral analysis, you may want to disable the dither to reduce noise. Enabling and disabling of the dither circuitry is accomplished through software (see Chapter 4, Register Map and Descriptions).

When taking DC measurements, such as when calibrating the board, enable dither and average about 1,000 points to take a single reading. This process removes the effects of 12-bit quantization and reduces measurement noise, resulting in improved resolution. Dither, or additive white noise, has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of input. For more information on the effects of dither, see "Dither in Digital Audio" by John Vanderkooy and Stanley P. Lipshitz, Journal of the Audio Engineering Society, Vol. 35, No. 12, Dec., 1987.

ADC FIFO Buffer

When an A/D conversion is complete, the ADC circuitry shifts the result into the ADC FIFO buffer. The FIFO buffer is 16-bits wide and 512-words deep. This FIFO serves as a buffer to the ADC and is beneficial for two reasons. Any time an A/D conversion is complete, the value is saved in the FIFO buffer for later reading, and the ADC is free to start a new conversion. Secondly, the FIFO can collect up to 512 A/D conversion values before any information is lost; thus software or DMA has extra time (512 times the sample interval) to catch up with the hardware. If more than 512 values are stored in the FIFO without the FIFO being read from, an error condition called FIFO overflow occurs and A/D conversion information is lost. When the ADC FIFO contains a single A/D conversion value or more, it can generate a DMA or interrupt request to be serviced.

Analog Input Calibration

Measurement reliability is assured through the use of the onboard calibration circuitry of the AT-MIO-64F-5. This circuitry uses a stable, internal, +5 VDC reference that is measured at the factory against a higher accuracy reference; then its value is permanently stored in the EEPROM on the AT-MIO-64F-5. With this stored reference value, the AT-MIO-64F-5 board can be recalibrated without additional external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time. The AT-MIO-64F-5 is calibrated at the factory in both unipolar and bipolar modes, and these values are also permanently stored in the EEPROM. Calibration constants can be read from the EEPROM then written to the calibration DACs that adjust pregain offset, postgain offset, and gain errors associated with the analog input section. There is an 8-bit pregain offset calibration DAC, an 8-bit postgain offset calibration DAC, an 8-bit unipolar offset calibration DAC, and an 8-bit gain calibration DAC. Functions are provided with the board to calibrate the analog input section, access the EEPROM on the board, and write to the calibration DACs. When the AT-MIO-64F-5 leaves the factory, locations 96 through 127 of the EEPROM are protected and cannot be modified. Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used. Refer to Chapter 6, Calibration Procedures, for additional calibration information.

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Theory of Operation Chapter 3

Data Acquisition Timing Circuitry

This section details the different methods of acquiring A/D data from a single channel or multiple channels. Prior to any of these operations, the channel, gain, mode, and range settings must be configured. This is accomplished through writing to a register in the AT-MIO-64F-5 register set.

Single-Read Timing

The simplest method of acquiring data from the A/D converter is to initiate a single conversion and then read the resulting value from the ADC FIFO buffer after the conversion is complete. A single conversion can be generated three different waysÐapplying an active low pulse to the EXTCONV* pin of the I/O connector, generating a falling edge on the sample-interval counter output pin (Counter 3 of the Am9513A Counter/Timer), or strobing the appropriate register in the AT-MIO-64F-5 register set. Any one of these operations will generate the timing shown in Figure 3-4. The ADC_BUSY* signal status can be monitored through a status register on the AT-MIO-64F-5.

CONVERT*

ADC_BUSY*

FIFO_LD*

Figure 3-4. ADC Conversion Timing

When the ADC value is shifted into the ADC FIFO buffer by FIFO_LD*, a signal is generated that indicates valid data is available to be read. Single conversion timing of this type is appropriate for reading channel data on an ad hoc basis. However, if a sequence of conversions is needed, this method is not very reliable because it relies on the software to generate the conversions in the case of the strobe register. If finely timed conversions are desired that require triggering and gating, then it is necessary to program the board to automatically generate timed signals that initiate and gate conversions. This is known as a data acquisition sequence.

A data acquisition operation refers to the process of taking a sequence of A/D conversions with the sample interval (the time between successive A/D conversions) carefully timed. The data acquisition timing circuitry consists of various clocks and timing signals. Three types of data acquisition are available with the AT-MIO-64F-5 boardÐsingle-channel data acquisition, multiple-channel data acquisition with continuous scanning, and multiple-channel data acquisition with interval scanning. All data acquisition operations work with pretrigger and posttrigger modes with either internal or external timing signals. Pretriggering acquires data before a software or hardware trigger is applied. Posttriggering acquires data only after a software or hardware trigger is received.

Single-Channel Data Acquisition Timing

The sample-interval timer is a 16-bit down counter that can be used with the six internal timebases of the Am9513A to generate sample intervals from 0.4 µsec to 6 sec (see the Timing I/O Circuitry section later in this chapter). Conversion intervals of less than 5 µsec will result in an overrun condition. Counter 3 of the Am9513A Counter/Timer is used to generate conversion

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interval timing signals. The sample-interval timer can also use any of the external clock inputs to the Am9513A as a timebase. During data acquisition, the sample interval counts down at the rate given by the internal timebase or external clock. Each time the sample-interval timer reaches zero, it generates an active low pulse and reloads with the programmed sample-interval count, initiating a conversion. This operation continues until data acquisition halts.

External control of the sample interval is possible by applying a stream of pulses at the EXTCONV* input. In this case, you have complete external control over the sample interval and the number of A/D conversions performed. All data acquisition operations are functional with external signals to control conversions. This means that in a data acquisition sequence that employs external conversion timing, conversions are inhibited by the hardware until a trigger condition is received, then the programmed number of conversions occurs, and conversions are inhibited after the sequence completes. When using internal timing, the EXTCONV* signal at the I/O connector must be left unconnected or in the high-impedance state.

Data acquisition can be controlled by the onboard sample counter. This counter is loaded with the number of posttrigger samples to be taken during a data acquisition operation. The sample counter can be 16-bit for counts up to 65,535 or 32-bit for counts up to 232 - 1. If a 16-bit counter is needed, Counter 4 of the Am9513A Counter/Timer is used. If more than 16-bits are needed, Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32-bit counter. The sample counter decrements its count each time the sample-interval counter generates an A/D conversion pulse, and the sample counter stops the data acquisition process when it counts down to zero. The sample counter can also be used to count conversions generated by external conversion signals.

The configuration memory register is set up to select the analog input channel and configuration before data acquisition is initiated for a single-channel data acquisition sequence. These settings remain constant during the entire data acquisition process; therefore, all A/D conversions are performed on a single channel. Single-channel acquisition is enabled through a register in the AT-MIO-64F-5 register set. The data acquisition process can be initiated via software or by applying an active low pulse to the EXTTRIG* input on the AT-MIO-64F-5 I/O connector. Figure 3-5 shows the timing of a typical single-channel data acquisition sequence.

Trigger*

DAQPROG

CONVERT

Sample CTR

DAQCMPLT

Interrupt DAQCLEAR*

9 8

7 6 5 4 3 2 1 10 9

Figure 3-5. Single-Channel Posttrigger Data Acquisition Timing

In this sequence, the sample-interval counter, Counter 3, is programmed to generate conversion signals only under a certain gating signal, such as the DAQPROG signal. In addition, the sample counter, Counter 4, is programmed to count the number of conversions generated. In this case, the sample counter is programmed to count 10 samples, then stop the acquisition sequence.

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A signal is generated at the end of the sequence to indicate its completion. An interrupt request can be generated from this signal if desired. Because the sample counter begins counting immediately after the application of the trigger, this is a posttrigger sequence. If samples are necessary before and after the trigger, then a pretrigger sequence is needed. This sequence is described in the following paragraphs.

Figure 3-6 depicts a pretrigger data acquisition sequence. It is called a pretrigger sequence because the first trigger initiates the sample-interval timer without enabling the sample counter. Conversions occur after this initial trigger and are stored in the ADC FIFO for later retrieval in the same way they are for a posttrigger sequence. After a second trigger is received, the sample counter begins counting conversions. In this example, there are three pretrigger samples, and seven posttrigger samples. Only the number of posttrigger samples is programmable.

Trigger*

DAQPROG

CONVERT Samp CTR Gate

Sample CTR

DAQCMPLT

Interrupt

DAQCLEAR*

5 4 3 2 1 7

Figure 3-6. Single-Channel Pretrigger Data Acquisition Timing

The pretrigger sequence is programmed in much the same way as a posttrigger sequence. The sample-interval timer is programmed to generate conversion pulses under a gate signal, and the sample counter is programmed to count the number of conversions. The only difference between pretrigger and posttrigger sequences for all data acquisition modes is that the sample counter waits for a gating signal in the pretrigger mode before beginning the count. For posttrigger sequences, the sample timer is independent of the gating signal, and for pretrigger sequences, the sample timer is dependent on the gating signal.

Multiple-Channel Data Acquisition

Multiple-channel data acquisition is performed by enabling scanning during data acquisition. Multiple-channel scanning is controlled by the configuration memory register.

The configuration memory register consists of 512 words of memory. Each word of memory contains a multiplexer address for input analog channel selection, a gain setting, a mode setting (single-ended or differential), and a range setting (unipolar or bipolar). Each word of memory also contains a bit for synchronizing scanning sequences of different rates, a bit enabling serial data transmission of channel conversion data over the RTSI bus to the AT-DSP2200 digital signal processing board, and a bit indicating if the entry is the last in the scan sequence. In interval scanning, a scan list can consist of any number of scan sequences. Whenever a configuration memory location is selected, the information bits contained in that memory location are applied to the analog input circuitry. For scanning operations, a counter steps through successive locations in the configuration memory at a rate determined by the scan clock. With the configuration memory, therefore, an arbitrary sequence of channels with separate gain, mode, and range settings for each channel can be clocked through during a scanning operation.

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A SCANCLK signal is generated from the sample-interval counter. This signal pulses once at the beginning of each A/D conversion and is supplied at the I/O connector. During multiple-channel scanning, the configuration memory location pointer is incremented repeatedly, thereby sequencing through the memory and automatically selecting new channel settings during data acquisition. The signal used to increment the configuration memory location pointer is generated from the SCANCLK signal. Incrementing can be identical to SCANCLK, sequencing the configuration memory location pointer once after every A/D conversion, or it can also be generated by dividing SCANCLK by Counter 1 of the Am9513A Counter/Timer. With this method, the location pointer can be incremented once every N A/D conversions so that N conversions can be performed on a single-channel configuration selection before switching to the next configuration memory selection.

Continuous Scanning Data Acquisition Timing

Continuous scanning data acquisition uses the configuration memory register to automatically sequence from one analog input channel setting to another during the data acquisition sequence. Continuous scanning cycles through the configuration memory without any delays between cycles. Scanning is similar to the single-channel acquisition in the programming of both the sample-interval counter and the sample counter. Scanning data acquisition is enabled through a register in the AT-MIO-64F-5 register set. Figure 3-7 shows the timing for a continuous scanning data acquisition sequence.

Trigger*

DAQPROG

CONVERT

0120120Channel

SCANCLK

DAQCMPLT

Interrupt DAQCLEAR*

Figure 3-7. Scanning Posttrigger Data Acquisition Timing

In this sequence, the timing is the same as the single-channel acquisition except for the addition of the channel sequencing and the generation of the SCANCLK signal. The first sampled channel is Channel 0, followed in time by Channel 1, and finally Channel 2. After this, the sequence is repeated. For this example, the sequence consists of Channels 0, 1, and 2 which are cycled through twice to generate six values of conversion data. After the six samples have been acquired, the sample counter terminates the data acquisition sequence.

The SCANCLK signal is generated to indicate when the input signal can be removed from the conversion channel. This signal is available at the I/O connector and can be used to control external multiplexers for higher channel-count applications. The rising edge of SCANCLK signals when the ADC has acquired the input signal and no longer needs to have it held available. In the scanning acquisition modes, this signal pulses for every conversion.

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Interval Scanning Data Acquisition Timing

Interval scanning assigns a time between the beginning of consecutive scan sequences. If only one scan sequence is in the configuration memory list, the circuitry stops at the end of the list and waits the necessary interval time before starting the scan sequence again. If multiple scan sequences are in the configuration memory list, the circuitry stops at the end of each scan sequence and waits the necessary time interval before starting the next scan sequence. When the end of the scan list is reached, the circuitry stops and waits the necessary time interval before sequencing through the channel information list again. Figure 3-8 shows an example of the interval scanning sequence timing.

Trigger*

DAQPROG

CONVERT Channel

COUNTER2

SCANCLK

DAQCMPLT Interrupt

DAQCLEAR*

01 0 10

Figure 3-8. Interval Scanning Posttrigger Data Acquisition Timing

In interval-scanning applications, the first sample does not occur until after the first falling edge of the Counter 2 output, or one scan interval after the trigger. Scanning stops at the end of the first scan sequence or at the end of the entire scan list. The sequence restarts after a rising edge on Counter 2 is detected. The interval-scanning mode is useful for applications where a number of channels need to be monitored over a long period of time. Interval-scanning monitors the N channels every scan interval, so the effective channel conversion interval is equal to the interval between scans.

Data Acquisition Rates

The acquisition and channel selection hardware function so that in the channel scanning mode, the next channel in the channel configuration register is selected immediately after the conversion process has begun on the previous channel. With this method, the input multiplexers and the PGIA begin to settle to the new value while the conversion of the last value is still taking place. The circuitry on the AT-MIO-64F-5 is designed and defined to settle to within 0.5 LSBs, or 0.01% of full scale, in 5 µsec.

Analog Output and Timing Circuitry

The AT-MIO-64F-5 has two channels of 12-bit D/A output. Unipolar or bipolar output and internal or external reference voltage selection are available with each analog output channel through a register in the AT-MIO-64F-5 register set. Figure 3-9 shows a block diagram of the analog output circuitry.

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REF Selection

From Gain DAC1

DAC1WR

DATA

PC I/O Channel

DAC0WR

From Gain DAC0

REF

DAC1

From Offset DAC1

+10 V INT REF

From Offset DAC0

DAC0

REF

REF Selection

Figure 3-9. Analog Output Circuitry Block Diagram

DAC1 OUT

AO GND

I/O Connector

DAC0 OUT

EXTREF

Analog Output Circuitry

Each analog output channel contains a 12-bit DAC, reference selection switches, unipolar/bipolar output selection switches, and output data coding circuitry.

The DAC in each analog output channel generates a voltage proportional to the input voltage reference (V

) multiplied by the digital code loaded into the DAC. Each DAC can be loaded

ref

with a 12-bit digital code by writing to registers on the AT-MIO-64F-5 board. The output voltage is available on the AT-MIO-64F-5 I/O connector DAC0 OUT and DAC1 OUT pins. The analog output of the DACs is updated to reflect the loaded 12-bit digital code in one of the following three ways:

¥ Immediately when the 12-bit code is written to the DACs (in immediate update mode)

¥ When an active low pulse is detected on the TMRTRIG* signal (in posted update mode)

¥ When the Update Register is strobed (in posted update mode)

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Analog Output Configuration

The DAC output amplifiers can be configured through one of the AT-MIO-64F-5 registers to generate either a unipolar voltage output or a bipolar voltage output range. A unipolar output has an output voltage range of 0 to +V

bipolar output has an output voltage range of -V

- 1 LSB V and accepts straight binary input values. A

ref

to +V

-1 LSB V and accepts two's

ref

complement input values. One LSB is the voltage increment corresponding to an LSB change in the digital code word. For unipolar output, 1 LSB = (V

1 LSB = (V

)/2,048.

ref

)/4,096. For bipolar output,

ref

The voltage reference source for each DAC is selectable through one of the AT-MIO-64F-5 registers and can be supplied either externally at the EXTREF input or internally. The external reference can be either a DC or an AC signal. If an AC reference is applied, the analog output channel acts as a signal attenuator, and the AC signal appears at the output multiplied by the digital code divided by 4,096 for unipolar output or 2,048 for bipolar output. The internal reference is a 5 V reference multiplied by 2. Using the internal reference supplies an output voltage range of 0 to 9.9976 V in steps of 2.44 mV for unipolar output and an output voltage range of -10 to +9.9951 V in steps of 4.88 mV for bipolar output. Gain calibration for the DACs is intended only for the internal reference; it will only add a variable offset to the external reference. Offset calibration can be applied to both references.

Analog Output Calibration

Output voltage accuracy is assured through the use of the onboard calibration circuitry of the AT-MIO-64F-5. This circuitry uses a stable, internal, +5 VDC reference that is measured at the factory against a higher accuracy reference; then its value is permanently stored in the EEPROM on the AT-MIO-64F-5. With this stored reference value, the AT-MIO-64F-5 board can be recalibrated without external hardware at any time under any number of different operating conditions in order to remove errors caused by temperature drift and time. The AT-MIO-64F-5 is factory calibrated in both unipolar and bipolar modes, and these values are also permanently stored in the EEPROM. Calibration constants can be read from the EEPROM then written to the calibration DACs that adjust offset and gain errors associated with each analog output channel. For each DAC channel, there is an 8-bit offset calibration DAC, and an 8-bit gain calibration DAC. Functions are provided with the board to calibrate the analog output section, access the EEPROM on the board, and write to the calibration DACs. When the AT-MIO-64F-5 leaves the factory, locations 96 through 127 of the EEPROM are protected and cannot be modified. Locations 0 through 95 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used. Refer to Chapter 6, Calibration Procedures, for additional calibration information.

DAC Waveform Generation Timing and Circuitry

There are primarily two modes under which the DACs in the analog output section operateÐ immediate update and posted update. Immediate update mode is self-evident. You write a value to the DAC and its voltage is immediately available at the output. In posted update mode, the voltage is not available at the output until a timer trigger signal initiates an update. This mode has advantages in waveform generation applications which need precisely timed updates that are not software-dependent.

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DAC Waveform Circuitry

Figure 3-10 depicts the three different data paths to the analog output DACs.

Update*

Serial RTSI Data

R_Latch*

Local Data Bus DAC Data Bus•

L_Latch*

From Control Circuitry

RTSI Latch

LATCHEN*

Local Latch

LATCHEN*

FIFO

IN OUT

DACFIFOWR* DACFIFORD* DACFIFORT* DACFIFORS*

DACFIFOFF* DACFIFOHF* DACFIFOEF*

DAC0

DAC1

To Control Circuitry

Figure 3-10. Analog Output Waveform

The local latch is used for immediate updating of the DACs. When data is written to the DACs in immediate updating mode, the data is directly routed to the DACs to be converted to a voltage at the output. In this mode, the Update* signal is held low, or true. The only path available for data transfer to the DACs in the immediate update mode is the local latch. The path that the data takes to the DACs is determined by the DAC mode enabled through a register in the AT-MIO-64F-5 register set.

The DAC FIFO and RTSI latch are used for posted updating of the DACs. Data written to the DACs is buffered by the DAC FIFO to be updated at a later time. The DAC FIFO can buffer up to 2,048 values before updating the DAC. The RTSI latch is a special case of the posted update mode because data is not directly written to the AT-MIO-64F-5 board from the PC, but it is received serially from the AT-DSP2200. In this case, only one value can be buffered before updating the DAC.

In the posted update mode, you can use any one of the three paths to transfer data to the DACs. Data can be sent through the FIFO and local latch concurrently or separately. In this instance, the value written to the DAC through the local latch is not updated until the update pulse trigger occurs. If the RTSI latch is used to transfer serial data from the AT-DSP2200 over the RTSI bus, no other transferring path is allowed. In other words, data cannot be transmitted serially over the RTSI bus to DAC channel 0 and transferred through the FIFO to DAC channel 1 at the same time. These modes are mutually exclusive.

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DAC Waveform Timing Circuitry

Waveform timing implies precise updating of the analog output DACs to create a pure waveform without any jitter or uncertainty. This timing is accomplished by posting updates to the DACs. Posted update mode configures the DACs to buffer values written to them and update the output voltage only after a trigger signal. This trigger signal can come in the form of an internal counter pulse from Counters 1, 2, 3, or 5 of the Am9513A Counter/Timer, it can be supplied from the EXTTMRTRIG* signal at the I/O connector, or it can be obtained by accessing a register in the AT-MIO-64F-5 register set.

In the posted update mode, requests for writes to the DAC are generated from the TMRREQ signal and can be acknowledged in one of three waysÐeither polled I/O through monitoring the TMRREQ signal in Status Register 1, interrupts, or DMA. All three response mechanisms will have a delay associated with them in how fast they can respond to the requesting signal. DMA will have the fastest response, followed by polled I/O, and finally interrupts. The advantage of using interrupts is that the CPU is not solely dedicated to monitoring Status Register 1 and can simultaneously perform other tasks. If writes generated from these requests updated the DAC immediately, there could be significant jitter in the resulting output waveform, so values are written to a buffer where they are updated later with a precisely timed update signal. Figure 3-11 depicts the timing for the posted DAC update mode.

Update Trigger

TMRREQ

DAC Write*

X-1 X YDAC Output

Figure 3-11. Posted DAC Update Timing

In Figure 3-11, the update trigger signal serves to update the previously written value to the DAC. In the posted update mode, the DAC FIFO is used to buffer the data. Requests are generated either when the FIFO is not full or when the FIFO is less than half full. One of these two signals generates the TMRREQ signal. In the example above, requesting is generated when the FIFO is not full. Because each update removes a value from the DAC FIFO, each update also results in the TMRREQ signal being asserted. This sequence of events continues until the output buffer data is exhausted.

There are effectively two different modes in which to operate the DAC FIFOs in posted update mode. Data flows in and out at equal rates, or data is initialized in the FIFO and, once updating begins, the data is cycled through when the end of the FIFO buffer is encountered. If waveform cycles involving more than 2,048 values are required, data must continuously flow into and out of the FIFO buffer to be replenished. If waveform cycles of less than 2,048 points are required, the data can be transferred to the DAC FIFO only once where it can be cycled through to generate a continuous waveform. This mode removes the burden on the PC to continuously transfer new data to the DAC FIFO buffer, allowing it to perform other operations. In both cases, waveforms like the one shown in Figure 3-12 can be realized.

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Figure 3-12. Analog Output Waveform Circuitry

Whether the waveform size is greater than or less than 2,048 points, a waveform can be generated that is seamless, that is, there will be no gaps or missed points in the output waveform. If a point is missed for any reason, the waveform circuitry will automatically stop updating the DAC, and a waveform error signal will be generated that can be monitored in Status Register 1. An error condition, or underflow, occurs when data is extracted from the DAC FIFO faster than it enters, such that at one point the DAC FIFO becomes empty.

Underflow errors occur because of software or hardware latencies in acknowledging the signal requesting more data for the DAC FIFOs. This condition can be prevented in the cyclic mode where the buffer resides wholly in the DAC FIFO and is cycled through to generate a continuous waveform. The advantage of having the data in the DAC FIFO is that the FIFO never needs to have the data refreshed, therefore it is never empty. Rather than requesting new data, the FIFO simply reuses existing data, removing a large demand on the PC bus bandwidth. Maximum updating performance is achieved in this mode because it does not rely on the speed of the computer. All described waveform modes involving cycling within the DAC FIFO can also be accomplished without the entire buffer fitting inside the FIFO. However, this requires more software intervention and therefore results in a slower rate and decreased reliability.

FIFO Continuous Cyclic Waveform Generation

In addition to allowing better performance, the cyclic mode provides greater flexibility. Because the hardware is in full control of the buffer, it can start, stop, and restart the generation of the waveform as programmed. An example of this added functionality is shown in Figure 3-13.

DACFIFORT*

CYCLICSTOP

Figure 3-13. FIFO Cyclic Waveform Generation with Disable

In this example, the entire buffer fits within the DAC FIFO. After the waveform is initiated, it cycles and recycles through the buffer. The end of the buffer is indicated by the DACFIFORT* signal, or DAC FIFO Retransmit. This is a signal generated by the hardware in cyclic mode to trigger the DAC FIFO to retransmit its buffer. The CYCLICSTOP signal is programmable through a register in the AT-MIO-64F-5 register set. If this bit is cleared, the DAC FIFO hardware runs ad infinitum or until the timer update pulse triggering is disabled. If necessary,

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the waveform can be stopped by disabling the timer trigger. The result of this action is to leave the DAC at some unknown value, for example the last updated value. The advantage of the CYCLICSTOP control signal is that DAC updating ends gracefully. When this signal is set, the waveform ends after it encounters the next retransmit signal. Thus, it will always end in a known state at the end of the buffer.

FIFO Programmed Cyclic Waveform Generation

One step beyond the continuous waveform generation is the programmed cyclic waveform generation. This mode is also available only when the entire buffer fits within the DAC FIFO. Figure 3-14 shows the operation of this mode.

DACFIFORT*

543 2 1 0 5

COUNTER 1, 2, or 5

Figure 3-14. FIFO Programmed Cyclic Waveform Timing

In this case, one of the counters in the Am9513A Counter/Timer is programmed to count the number of DAC FIFO Retransmit signals. When the counter counts the appropriate number of occurrences, it terminates the waveform sequence. A bit is available in Status Register 1 to indicate termination of a waveform sequence.

FIFO Pulsed Waveform Generation

Another step beyond cycle counting is pulsed waveform generation. Again, this mode is applicable only if the entire buffer fits within the DAC FIFO. Figure 3-15 shows the operation of this mode and the resulting waveform.

DACFIFORT*

21 2 1 2 1 2CTR 1

CTR 1 Output CTR 2 Terminal Count

Figure 3-15. FIFO Pulsed Waveform Generation Timing

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In the pulsed waveform application, Counter 1 of the Am9513A is programmed to count the number of retransmit signals, before terminating the sequence. At this point, Counter 2 serves as an interval timer–waiting a programmed amount of time and then restarting the sequence. This process proceeds ad infinitum until the timer trigger is removed or disabled, or the CYCLICSTOP bit is set.

Digital I/O Circuitry

The AT-MIO-64F-5 has eight digital I/O lines. These eight digital I/O lines are divided into two ports of four lines each and are located at pins ADIO<3..0> and BDIO<3..0> on the I/O connector. Figure 3-16 shows a block diagram of the digital I/O circuitry.

ADIO <3..0>

BDIO <3..0>

EXTSTROBE*

I/O Connector

EXT STROBE WR*

DOUT0

Digital Output

DOUT1

Digital Output

Digital

Input

DATA <3..0>

DOUT0 ENABLE

DO REG WR

DATA <7..4>

DOUT1 ENABLE

DATA <7..0>

DIREG RD

PC I/O Channel

Figure 3-16. Digital I/O Circuitry Block Diagram

The digital I/O lines are controlled by the Digital Output Register and monitored by the Digital Input Register. The Digital Output Register is an 8-bit register that contains the digital output values for both ports 0 and 1. When port 0 is enabled, bits <3..0> in the Digital Output Register are driven onto digital output lines ADIO<3..0>. When port 1 is enabled, bits <7..4> in the Digital Output Register are driven onto digital output lines BDIO<3..0>.

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Reading the Digital Input Register returns the state of the digital I/O lines. Digital I/O lines ADIO<3..0> are connected to bits <3..0> of the Digital Input Register. Digital I/O lines BDIO<3..0> are connected to bits <7..4> of the Digital Input Register. When a port is enabled, the Digital Input Register serves as a read-back register, returning the digital output value of the port. When a port is not enabled, reading the Digital Input Register returns the state of the digital I/O lines driven by an external device.

Both the digital input and output registers are TTL-compatible. The digital output ports, when enabled, are capable of sinking 24 mA of current and sourcing 2.6 mA of current on each digital I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs.

The external strobe signal EXTSTROBE*, shown in Figure 3-16, is a general-purpose strobe signal. Writing to an address location on the AT-MIO-64F-5 board generates an active low 500-nsec pulse on this output pin. EXTSTROBE* is not necessarily part of the digital I/O circuitry but is shown here because it can be used to latch digital output from the AT-MIO-64F-5 into an external device.

Timing I/O Circuitry

The AT-MIO-64F-5 uses an Am9513A Counter/Timer for data acquisition timing and for general-purpose timing I/O functions. An onboard oscillator is used to generate the 10 MHz clock. Figure 3-17 shows a block diagram of the timing I/O circuitry.

FOUT

GATE2

OUT2

GATE1

SOURCE1

OUT1

GATE5

SOURCE5

OUT5

EXTTRIG*

5 MHz

÷5

Data

Acquisition

Timing

/ 16

/ 2

I/O Connector

Flip

Flop

Am9513A

Five-Channel

Counter/

Timer

SOURCE4 SOURCE3

GATE4

1 MHz

SOURCE2

OUT1 OUT2 OUT3 OUT4 OUT5

GATE3

Figure 3-17. Timing I/O Circuitry Block Diagram

÷2

BRDCLK (10 MHz)

DATA<15..0>

Am9513A RD/WR

RTSI Bus

CONVERT

SCANCLK

CONFIGCLK

PC I/O Channel

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The Am9513A contains five independent 16-bit counter/timers, a 4-bit frequency output channel, and five internally generated timebases. The five counter/timers can be programmed to operate in several useful timing modes. The programming and operation of the Am9513A are presented in detail in Appendix E, AMD Am9513A Data Sheet.

The Am9513A clock input is one-tenth the BRDCLK frequency selected by the W1 and W2 jumpers. The factory default for BRDCLK is 10 MHz, which generates a 1 MHz clock input to the Am9513A. The Am9513A uses this clock input plus a BRDCLK divided-by-two input at Source 2 to generate six internal timebases. These timebases can be used as clocks by the counter/timers and by the frequency output channel. When BRDCLK is 10 MHz, the six internal timebases normally used for AT-MIO-64F-5 timing functions are 5 MHz, 1 MHz, 100 kHz, 10 kHz, 1 kHz, and 100 Hz. The 16-bit counters in the Am9513A can be diagrammed as shown in Figure 3-18.

SOURCE

COUNTER

GATE

OUT

Figure 3-18. Counter Block Diagram

Each counter has a SOURCE input pin, a GATE input pin, and an output pin labeled OUT. The Am9513A counters are numbered 1 through 5, and their GATE, SOURCE, and OUT pins are labeled GATE N, SOURCE N, and OUT N, where N is the counter number.

For counting operations, the counters can be programmed to use any of the five internal timebases, any of the five GATE and five SOURCE inputs to the Am9513A, and the output of the previous counter (Counter 4 uses Counter 3 output, and so on). A counter can be configured to count either falling or rising edges of the selected input.

The counter GATE input allows counter operation to be gated. Once a counter is configured for an operation through software, a signal at the GATE input can be used to start and stop counter operation. The five gating modes available with the Am9513A are as follows:

• No gating

• Level gating active high

• Level gating active low

• Low-to-high edge gating

• High-to-low edge gating

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A counter can also be active high-level gated by a signal at GATE N+1 and GATE N-1, where N is the counter number.

The counter generates timing signals at its OUT output pin. The OUT output pin can also be set to a high-impedance state or a grounded-output state. The counters generate two types of output signals during counter operation–terminal count pulse output and terminal count toggle output. Terminal count is often referred to as TC. A counter reaches TC when it counts up or down and rolls over. In many counter applications, the counter reloads from an internal register when it reaches TC. In TC pulse output mode, the counter generates a pulse during the cycle that it reaches TC and reloads. In TC toggle output mode, the counter output changes state after it reaches TC and reloads. In addition, the counters can be configured for positive logic output or negative (inverted) logic output for a total of four possible output signals generated for one timing mode.

The GATE and OUT pins for Counters 1, 2, and 5 and SOURCE pins for Counters 1 and 5 of the onboard Am9513A are located on the AT-MIO-64F-5 I/O connector. A falling edge signal on the EXTTRIG* pin of the I/O connector or writing to the STARTDAQ register during a data acquisition sequence sets the flip-flop output signal connected to the GATE4 input of the Am9513A and can be used as an additional gate input. This mode is also used in the pretrigger data acquisition mode. The flip-flop output connected to GATE4 is cleared when the sample counter reaches TC, when an overflow or overrun occurs, or when the DAQ Clear Register is written to. An overrun is defined as an error generated when the ADC cannot keep up with its programmed conversion speed.

The Am9513A SOURCE5 pin is connected to the AT-MIO-64F-5 RTSI switch, which means that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A counters.

The Am9513A OUT1, OUT2, OUT3 (EXTCONV*), and OUT5 pins can be used in several different ways. If waveform generation is enabled, an active low pulse on the output of the counter selected through the RTSI switch updates the analog output on the two DACs. The counter outputs can also be used to trigger interrupt and DMA requests. If the proper mode is selected in Command Register 2, an interrupt or DMA request occurs when a falling edge signal is detected on the selected DAC update signal.

Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing, and therefore are not available for general-purpose timing applications. Signals generated at OUT3 and OUT4 are sent to the data acquisition timing circuitry. GATE3 is controlled by the data acquisition timing circuitry. OUT3 is internally connected to EXTCONV* so that when internal data acquisition sequences (OUT3) are used, EXTCONV* should be disconnected or tristated. For the same reason, if external data acquisition sequences (EXTCONV*) are used, OUT3 should be programmed to the high-impedance state.

Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32-bit sample counter. The SCANCLK signal is connected to the SOURCE3 input of the Am9513A, and OUT1 is sent to the data acquisition timing circuitry. This allows Counter 1 to be used to divide the SCANCLK signal for generating the CONFIGCLK signal. See the Data Acquisition Timing Circuitry section earlier in this chapter.

Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the channel configuration register. This mode is called interval channel scanning. See the Multiple-Channel Data Acquisition section earlier in this chapter.

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Chapter 3 Theory of Operation

The Am9513A 4-bit programmable frequency output channel is located at the I/O connector FOUT pin. Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source. The frequency output channel divides the selected source by its 4-bit programmed value and makes the divided down signal available at the FOUT pin.

RTSI Bus Interface Circuitry

The AT-MIO-64F-5 is interfaced to the National Instruments RTSI bus. The RTSI bus has seven trigger lines and a system clock line. All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC and share these signals. A block diagram of the RTSI bus interface circuitry is shown in Figure 3-19.

OUT2

GATE1

TMRTRIG

OUT5

DRV

Drivers

RCV

EXTCONV

SOURCE5

OUT1

EXTTRIG

RTSI SEL

Internal

Data Bus

FOUT

BRDCLK

A0 A1 A2 A3 A4 A5 A6

/SEL DATA

RTSI

Switch

B0 B1 B2 B3 B4 B5 B6

10-MHz Oscillator

DAC_SDATA

ADC_SDATA

RTSICLK

Trigger

RTSI Bus Connector

DAC_SYNC

DAC_CLK

ADC_CLK

ADC_SYNC

Figure 3-19. RTSI Bus Interface Circuitry Block Diagram

The RTSICLK line can be used to source a 10 MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus. BRDCLK is the system clock used by the AT-MIO-64F-5. Bits in a command register in the AT-MIO-64F-5 register set control how these clock signals are routed.

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Theory of Operation Chapter 3

The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch. Pins B<6..0> are connected to the seven RTSI bus trigger lines. Pins A<6..0> are connected to seven signals on the board. The RTSI switch can drive any of the signals at pins A<6..0> onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A<6..0>. This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus. The RTSI switch is programmed via its chip select and data inputs.

On the AT-MIO-64F-5 board, nine signals are connected to pins A<6..0> of the RTSI switch with the aid of additional drivers. The signals GATE1, OUT1, OUT2, SOURCE5, OUT5, and FOUT are shared with the AT-MIO-64F-5 I/O connector and Am9513A Counter/Timer. The EXTCONV* and EXTTRIG* signals are shared with the I/O connector and the data acquisition timing circuitry. The TMRTRIG* signal is used to update the two DACs on the AT-MIO-64F-5. These onboard interconnections allow AT-MIO-64F-5 general-purpose and data acquisition timing to be controlled over the RTSI bus as well as externally, and allow the AT-MIO-64F-5 and the I/O connector to send timing signals to other AT boards connected to the RTSI bus.

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Chapter 4 Register Map and Descriptions

This chapter describes in detail the address and function of each of the AT-MIO-64F-5 control and status registers.

Note: If you plan to use a programming software package such as NI-DAQ or LabWindows

with your AT-MIO-64F-5 board, you need not read this chapter. However, you will gain added insight into your AT-MIO-64F-5 board by reading this chapter.

Register Map

The register map for the AT-MIO-64F-5 is shown in Table 4-1. This table gives the register name, the register offset address, the type of the register (read-only, write-only, or read-andwrite) and the size of the register in bits. The actual register address is obtained by adding the appropriate register offset to the I/O base address of the AT-MIO-64F-5.

Registers are grouped in the table by function. Each register group is introduced in the order shown in Table 4-1, then described in detail, including a bit-by-bit description.

Table 4-1. AT-MIO-64F-5 Register Map

(Hex)

Configuration and Status Register Group

Command Register 1 0 Write-only 16-bit Command Register 2 2 Write-only 16-bit Command Register 3 4 Write-only 16-bit Command Register 4 6 Write-only 16-bit Status Register 1 18 Read-only 16-bit Status Register 2 1A Read-only 16-bit

Analog Input Register Group

ADC FIFO Register 0 Read-only 16-bit CONFIGMEM Register 8 Write-only 16-bit

Analog Output Register Group

DAC0 Register 10 Write-only 16-bit DAC1 Register 12 Write-only 16-bit

(continues)

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Table 4-1. AT-MIO-64F-5 Register Map (Continued)

(Hex)

ADC Event Strobe Register Group

CONFIGMEMCLR Register 1B Read-only 8-bit

CONFIGMEMLD Register 1B Write-only 8-bit

DAQ Clear Register 19 Read-only 8-bit DAQ Start Register 1D Read-only 8-bit Single Conversion Register 1D Write-only 8-bit

DAC Event Strobe Register Group

TMRREQ Clear Register 1F Read-only 8-bit DAC Update Register 18 Write-only 16-bit DAC Clear Register 1E Read-only 8-bit

General Event Strobe Register Group

DMA Channel Clear Register 0B Read-only 8-bit DMATCA Clear Register 19 Write-only 8-bit DMATCB Clear Register 09 Read-only 8-bit External Strobe Register 1E Write-only 8-bit Calibration DAC 0 Load Register 0A Write-only 8-bit

Am9513A Counter/Timer Register Group

Am9513A Data Register 14 Read-and-write 16-bit Am9513A Command Register 16 Write-only 16-bit Am9513A Status Register 16 Read-only 16-bit

Digital I/O Register Group

Digital Input Register 1C Read-only 16-bit Digital Output Register 1C Write-only 16-bit

RTSI Switch Register Group

RTSI Switch Shift Register 0C Write-only 8-bit RTSI Switch Strobe Register 0E Write-only 8-bit

Register Sizes

Two different transfer sizes for read-and-write operations are available on the PCÐbyte (8-bit) and word (16-bit). Table 4-1 shows the size of each AT-MIO-64F-5 register. For example, reading the ADC FIFO Register requires a 16-bit (word) read operation at the selected address, whereas writing to the RTSI Strobe Register requires an 8-bit (byte) write operation at the selected address. These register size accesses must be adhered to for proper board operation. Performing a byte access on a word location is an invalid operation and should be avoided. The converse is also true. Performing a word access on a byte location is also an invalid operation and should be avoided. You should pay particular attention to the register sizes because they are very important.

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Chapter 4 Register Map and Descriptions

Register Description Format

The remainder of this register description chapter discusses each of the AT-MIO-64F-5 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.

The register bit map shows a diagram of the register with the MSB shown on the left (bit 15 for a 16-bit register, bit 7 for an 8-bit register), and the LSB shown on the right (bit 0). A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after the bit name indicates that the bit is inverted (negative logic).

In many of the registers, several bits are labeled with an X, indicating donÕt care bits. When a register is read, these bits may appear set or cleared but should be ignored because they have no significance.

The bit map field for some registers states not applicable, no bits used. Accessing these registers generates a strobe in the AT-MIO-64F-5. These strobes are used to initiate some onboard event to occur. For example, they can be used to clear the analog input circuitry or to start a data acquisition operation. The data is ignored when writing to these registers; therefore, any bit pattern suffices. Likewise, data returned from a strobe register read access is meaningless.

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Configuration and Status Register Group

The six registers making up the Configuration and Status Register Group allow general control and monitoring of the AT-MIO-64F-5 hardware. Command Registers 1, 2, 3, and 4 contain bits that control operation of several different pieces of the AT-MIO-64F-5 hardware. Status Registers 1 and 2 can be used to read the state of different pieces of the AT-MIO-64F-5 hardware.

Bit descriptions of the six registers making up the Configuration and Status Group are given on the following pages.

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Chapter 4 Register Map and Descriptions

Command Register 1

Command Register 1 contains 12 bits that control AT-MIO-64F-5 serial device access, and data acquisition mode selection. The contents of this register are not defined upon power up and are not cleared after a reset condition. This register should be initialized through software.

Address: Base address + 00 (hex)

Type: Write-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

EEPROMCS SDATA SCLK SCANDIV DITHER INTGATE RETRIG_DIS DAQEN

MSB

76543210

SCANEN SCN2 CNT32/16* RTSITRIG 0000

LSB

Bit Name Description

15 EEPROMCS EEPROM Chip Select Ð This bit controls the chip select of the

onboard EEPROM used to store calibration constants. When EEPROMCS is set, the chip select signal to the EEPROM is enabled. Before EEPROMCS is brought high, SCLK should first be pulsed high to initialize the EEPROM circuitry.

14 SDATA Serial Data Ð This bit is used to transmit a single bit of data to the

EEPROM and both of the calibration DACs.

13 SCLK Serial Clock Ð A low-to-high transition of this bit clocks data from

SDATA into the EEPROM (when EEPROMCS is set) and the calibration DAC. If EEPROMCS is cleared, toggling SCLK does not affect the EEPROM. Serial data is always loaded into the calibration DACs, but the information is not updated until after the application of the appropriate load signal.

12 SCANDIV Scan Divide Ð This bit controls the configuration memory

sequencing during scanned data acquisition. If SCANDIV is set, then sequencing is controlled by Counter 1 of the Am9513A Counter/Timer. If SCANDIV is cleared, the configuration memory is sequenced after each conversion during scanning.

11 DITHER Dither Ð When this bit is set, 0.5 LSBs of white Gaussian noise is

added to the selected analog input signal. By enabling DITHER and using averaging, input resolution greater than 12 bits is obtainable.

Page 90

Bit Name Description (continued)

10 INTGATE Internal Gate Ð This bit controls internal and external A/D

conversions. When INTGATE is set, no A/D conversions take place. When INTGATE is cleared, A/D conversions take place normally. INTGATE can be used as a software gating tool, or to inhibit random conversions during setup operations.

9 RETRIG_DIS Retrigger Disable Ð This bit controls retriggering of the

AT-MIO-64F-5 data acquisition circuitry. When RETRIG_DIS is set, retriggering of the data acquisition circuitry is inhibited until the end of the previous operation is acknowledged by clearing the DAQPROG bit in Status Register 0. When RETRIG_DIS is cleared, the data acquisition circuitry may be retriggered any time following the end of the previous acquisition sequence.

8 DAQEN Data Acquisition Enable Ð This bit enables and disables a data

acquisition operation that is controlled by the onboard sampleinterval and sample counters. If DAQEN is set, a software DAQ Start or hardware (EXTTRIG*) trigger starts the programmed counters, thereby initiating a data acquisition operation. If DAQEN is cleared, software and hardware triggers have no effect.

7 SCANEN Scan Enable Ð This bit controls multiple-channel scanning during

data acquisition. If SCANEN is set and DAQEN is also set, alternate analog input channels are sampled during data acquisition under control of the channel configuration memory. If SCANEN is cleared and DAQEN is set, a single analog input channel is sampled during the entire data acquisition operation. When SCANEN is set, the SCANCLK signal at the I/O connector is enabled. Otherwise, it is disabled.

6 SCN2 Scan Mode 2 Ð This bit selects the data acquisition scanning mode

used when scanning multiple A/D channels. If SCN2 is set and SCANEN and DAQEN are set, interval-channel scanning is used. In this mode, scan sequences occur during a programmed time interval, called a scan interval. One cycle of the scan sequence occurs during each scan interval. If SCN2 is cleared and SCANEN and DAQEN are set, continuous channel scanning is used. In this mode, scan sequences are repeated with no delays between cycles.

5 CNT32/16* 32 or 16 Bit Sample Count Ð This bit selects the count resolution

for the number of A/D conversions to be performed in a data acquisition operation. If CNT32/16* is cleared, a 16-bit count mode is selected and Counter 4 of the Am9513A Counter/Timer controls conversion counting. If CNT32/16* is set, a 32-bit count mode is selected and Counter 4 is concatenated with Counter 5 to control conversion counting. A 16-bit count mode can be used if the number of A/D sample conversions to be performed is less than 65,537. A 32-bit count mode should be used if the number of A/D sample conversions to be performed is greater than or equal to 65,537.

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Chapter 4 Register Map and Descriptions

Bit Name Description (continued)

4 RTSITRIG RTSI Trigger Ð This bit controls multiple board synchronization

through RTSI Bus triggering. If RTSITRIG is set, then triggering of the data acquisition sequence by another National Instruments board over the RTSI bus is enabled. Otherwise, if RTSITRIG is cleared, the data acquisition sequence is triggered by the onboard Start DAQ Register or a high-to-low transition on the EXTTRIG* signal at the I/O Connector. When this bit is set, the local DAQ Start Register and the EXTTRIG* signal have no effect.

3-0 0 Reserved Ð These bits must always be set to zero.

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Command Register 2

Command Register 2 contains 15 bits that control AT-MIO-64F-5 RTSI bus transceivers, analog output configuration, and DMA channels A and B selection. Bits 8-15 of this register are cleared upon power up and after a reset condition. Bits 0-7 of this register are undefined upon power up and are not cleared after a reset condition. These bits should be initialized through software.

Address: Base address + 02 (hex)

Type: Write-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

A4RCV A4DRV A2RCV A2DRV BIPDAC1 BIPDAC0 EXTREFDAC1EXTREFDAC

MSB

76543210

EISA_DMA 0 DMACHBB2 DMACHBB1 DMACHBB0 DMACHAB2 DMACHAB1 DMACHAB0

LSB

Bit Name Description

15 A4RCV RTSI A4 Receive Ð This bit controls the signal source for the

TMRTRIG*(Timer Trigger) signal. The TMRTRIG* signal updates the DACs in delayed update mode. If A4RCV is set, pin A4 of the RTSI switch drives the TMRTRIG* signal. If A4RCV is cleared, the TMRTRIG* signal is driven by the EXTTMRTRG* signal from the I/O connector.

14 A4DRV RTSI A4 Drive Ð This bit controls the driver that allows the OUT5

signal to drive pin A4 of the RTSI switch. If A4DRV is set, pin A4 of the RTSI switch is driven by OUT5. If A4DRV is cleared, pin A4 is not driven by OUT5, and it can be driven by a signal on the RTSI bus.

13 A2RCV RTSI A2 Receive Ð This bit controls the driver that allows the

GATE1 signal to be driven from pin A2 of the RTSI switch. If A2RCV is set, pin A2 of the RTSI switch drives the GATE1 signal. In this case, GATE1 may not be driven by a signal at the I/O connector.

12 A2DRV RTSI A2 Drive Ð This bit controls the driver that allows the OUT2

signal to drive pin A2 of the RTSI switch. If A2DRV is set, pin A2 of the RTSI switch is driven by OUT2. If A2DRV is cleared, pin A2 is not driven by OUT2, and it can be driven by a signal on the RTSI bus.

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Chapter 4 Register Map and Descriptions

Bit Name Description (continued)

11 BIPDAC1 Bipolar DAC 1 Ð This bit configures the range of DAC 1 in the

analog output section. If this bit is set, DAC 1 is configured for bipolar operation of -V

to +V

ref

. In this mode, data written to

ref

this DAC is interpreted in twoÕs complement format. If this bit is cleared, DAC 1 is configured for unipolar operation of 0 V to +V

. In this mode, data written to DAC 1 is interpreted in

ref

straight binary format.

10 BIPDAC0 Bipolar DAC 0 Ð This bit configures the range of DAC 0 in the

analog output section. If this bit is set, then DAC 0 is configured for bipolar operation of -V

ref

to +V

. In this mode, data written

ref

to this DAC is interpreted in twoÕs complement format. If this bit is cleared, then DAC 0 is configured for unipolar operation of 0 V to +V

. In this mode, data written to DAC 0 is interpreted in

ref

straight binary format.

9 EXTREFDAC1 External Reference for DAC 1 Ð This bit controls the reference

selection for DAC 1 in the analog output section. If this bit is set, the reference used for DAC 1 is the external reference voltage from the I/O connector. If this bit is cleared, the internal +10 V

ref

is used for the DAC 1 reference.

8 EXTREFDAC0 External Reference for DAC 0 Ð This bit controls the reference

selection for DAC 0 in the analog output section. If this bit is set, the reference used for DAC 0 is the external reference voltage from the I/O connector. If this bit is cleared, the internal +10 V

is used for the DAC 0 reference.

7 EISA_DMA EISA Computer DMA Ð This bit controls the type of DMA

transfer from the ADC FIFO on an EISA computer. If EISA_DMA is clear, single transfer DMA mode is used. If EISA_DMA is set, demand-mode DMA is used. This bit should only be set if the AT-MIO-64F-5 is installed in an EISA-type computer.

6 0 Reserved Ð This bit must always be set to zero.

5-3 DMACHBB<2..0> DMA Channel B Select Ð These bits select the secondary DMA

channel for use by the AT-MIO-64F-5. See Table 4-2.

2-0 DMACHAB<2..0> DMA Channel A Select Ð These bits select the primary DMA

channel for use by the AT-MIO-64F-5. See Table 4-2.

ref

Page 94

Table 4-2. DMA Channel Selection

Bit Pattern Effect Bit Pattern Effect

DMACHAB2

DMACHAB1

DMACHAB0

Primary

DMA Channel

Selected (A)

DMACHBB2

DMACHBB1

DMACHBB0

Secondary

DMA Channel

Selected (B)

000 DMA Channel 0 0 0 0 DMA Channel 0

001 DMA Channel 1 0 0 1 DMA Channel 1

010 DMA Channel 2 0 1 0 DMA Channel 2

011 DMA Channel 3 0 1 1 DMA Channel 3

100 No effect 1 0 0 No effect

101 DMA Channel 5 1 0 1 DMA Channel 5

110 DMA Channel 6 1 1 0 DMA Channel 6

111 DMA Channel 7 1 1 1 DMA Channel 7

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Chapter 4 Register Map and Descriptions

Command Register 3

Command Register 3 contains 16 bits that control the ADC link to the AT-DSP2200, digital I/O port, interrupt and DMA modes, and interrupt channel selection. The contents of this register are defined to be cleared upon power up and after a reset condition.

Address: Base address + 04 (hex)

Type: Write-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

ADCDSP DIOPBEN DIOPAEN DMATCINT DACCMPLINT DAQCMPLINT I/O_INT DMACHA

MSB

76543210

DMACHB ADCREQ DAC1REQ DAC0REQ DRVAIS INTCHB2 INTCHB1 INTCHB0

LSB

Bit Name Description

15 ADCDSP ADC DSP Link Enable Ð This bit controls the serial link from the

A/D converter to the AT-DSP2200. If ADCDSP is set, then the serial link is enabled. Data from channels that have been marked in the channel configuration memory will be transmitted over the RTSI bus. If ADCDSP is cleared, the serial RTSI link is disabled, irrespective of the marking of channels in the channel configuration memory.

14 DIOPBEN Digital I/O Port B Enable Ð This bit controls the 4-bit digital output

port B. If DIOPBEN is set, the Digital Output Register drives the DIO<8..5> digital lines at the I/O connector. If DIOPBEN is cleared, the Digital Output Register drivers are set to a highimpedance state; therefore, an external device can drive the DIO<8..5> digital lines.

13 DIOPAEN Digital I/O Port A Enable Ð This bit controls the 4-bit digital

output port A. If DIOPAEN is set, the Digital Output Register drives the DIO<4..1> digital lines at the I/O connector. If DIOPAEN is cleared, the Digital Output Register drivers are set to a high-impedance state; therefore, an external device can drive the DIO<4..1> digital lines.

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Bit Name Description (continued)

12 DMATCINT DMA Terminal Count Interrupt Enable Ð This bit controls the

generation of an interrupt when a DMA terminal count pulse is received from the DMA controller in the PC AT. If DMATCINT is set, an interrupt request is generated when the DMA controller transfers the final value on the primary DMA channel, channel A, or the secondary DMA channel, channel B. The interrupt request is serviced by strobing the appropriate DMATC Clear Register. When DMATCINT is cleared, no DMA terminal count interrupts are generated.

11 DACCMPLINT DAC Complete Interrupt Enable Ð This bit controls the generation

of an interrupt when a DAC sequence completes. If DACCMPLINT is set, an interrupt request is generated when the sequence completes. The interrupt request is serviced by strobing the TMRREQ Clear or DAC Clear Register. When DACCMPLINT is cleared, completion of a sequence does not generate an interrupt. A DAC sequence ends by running its course or when an error condition occurs such as UNDERFLOW.

10 DAQCMPLINT DAQ Complete Interrupt Enable Ð This bit controls the generation

of an interrupt when a data acquisition sequence completes. If DAQCMPLINT is set, an interrupt request is generated when the data acquisition operation completes. The interrupt request is serviced by strobing the DAQ Clear Register. When DAQCMPLINT is cleared, completion of a data acquisition sequence does not generate an interrupt. A data acquisition sequence ends by running its course or when an error condition occurs such as OVERRUN or OVERFLOW.

9 I/O_INT Input/Output Interrupt Enable Ð This bit, along with the

appropriate mode bits, enables and disables I/O interrupts generated from the AT-MIO-64F-5. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns.

8 DMACHA DMA Channel A Enable Ð This bit controls the generation of

DMA requests on DMA channel A as selected in Command Register 2. DMA requests are generated from A/D conversions as well as from timer updates. If DMACHA is set, then requesting is enabled for DMA channel A. If DMACHA is cleared, no DMA requests are generated on DMA channel A. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns.

7 DMACHB DMA Channel B Enable Ð This bit controls the generation of

DMA requests on DMA channel B as selected in Command Register 2. DMA requests are generated from A/D conversions as well as from timer updates. If DMACHB is set, requesting is enabled for DMA channel B. If DMACHB is cleared, no DMA requests are generated on DMA channel B. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns.

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Chapter 4 Register Map and Descriptions

Bit Name Description (continued)

6 ADCREQ ADC Request Enable Ð This bit controls DMA requesting and

interrupt generation from an A/D conversion. If this bit is set, an interrupt or DMA request is generated when an A/D conversion is available in the FIFO. If this bit is cleared, no DMA request or interrupt is generated following an A/D conversion. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns.

Table 4-3. DMA and Interrupt Modes

Interface Mode

Mode Description

IO_INT

DMACHA

0 1 0 0 0 1 Channel A to DAC0

0 1 0 0 1 0 Channel A to DAC1

0 1 0 0 1 1 Channel A to DAC0 and DAC1 (interleaved)

0 1 0 1 0 0 Channel A from ADC

0 0 1 0 0 1 Channel B to DAC0

0 0 1 0 1 0 Channel B to DAC1

0 0 1 0 1 1 Channel B to DAC0 and DAC1 (interleaved)

0 0 1 1 0 0 Channel B from ADC

ADCREQ

DMACHB

DAC1REQ

DAC0REQ

0 1 1 0 0 0 Channel A and Channel B to DAC0 and DAC1 (double-buffered)

0 1 1 0 0 1 Channel A and Channel B to DAC0 (double-buffered)

0 1 1 0 1 0 Channel A and Channel B to DAC1 (double-buffered)

0 1 1 0 1 1 Channel A and Channel B to DAC0 and DAC1 (sync double-channel)

0 1 1 1 0 0 Channel A and Channel B from ADC (double-buffered)

0 1 1 1 0 1 Channel A from ADC, Channel B to DAC0

0 1 1 1 1 0 Channel A from ADC, Channel B to DAC1

0 1 1 1 1 1 Channel A from ADC, Channel B to DAC0 and DAC1 (interleaved)

1 0 0 0 0 1 Timer interrupt

1 0 0 0 1 0 Timer interrupt

1 0 0 0 1 1 Timer interrupt

1 0 0 1 0 0 ADC interrupt

1 0 0 1 0 1 ADC and timer interrupt

1 0 0 1 1 0 ADC and timer interrupt

1 0 0 1 1 1 ADC and timer interrupt

(continues)

Page 98

Bit Name Description (continued)

Table 4-3. DMA and Interrupt Modes (Continued)

Interface Mode

Mode Description

IO_INT

DMACHA

1 1 0 0 0 1 Channel A to DAC0 with ADC interrupt

1 1 0 0 1 0 Channel A to DAC1 with ADC interrupt

1 1 0 0 1 1 Channel A to DAC0 and DAC1 (interleaved) with ADC interrupt

1 1 0 1 0 0 Channel A from ADC with timer interrupt

1 0 1 0 1 0 Channel B to DAC1 with ADC interrupt

1 0 1 0 1 1 Channel B to DAC0 and DAC1 (interleaved) with ADC interrupt

1 0 1 1 0 0 Channel B from ADC with timer interrupt

1 1 1 0 0 0 Channels A and B to DACs 0 and 1 (double-buffered) with ADC interrupt

1 1 1 0 0 1 Channel A and Channel B to DAC0 (double-buffered) with ADC interrupt

1 1 1 0 1 0 Channel A and Channel B to DAC1 (double-buffered) with ADC interrupt

1 1 1 0 1 1 Channels A and B to DACs 0 and 1 (sync double-channel) with ADC interrupt

1 1 1 1 0 0 Channels A and B from ADC (double-buffered) with timer interrupt

1 1 1 1 0 1 Channel A to DAC0 and Channel B from ADC

1 1 1 1 1 0 Channel A to DAC1 and Channel B from ADC

1 1 1 1 1 1 Channel A to DAC0 and DAC1 (interleaved) and Channel B from ADC

ADCREQ

DMACHB

DAC1REQ

DAC0REQ

5 DAC1REQ DAC 1 Request Enable Ð This bit controls DMA requesting and interrupt

generation from D/A updates. If this bit is set, an interrupt or DMA request is generated when the DAC is ready to receive data. If this bit is cleared, no DMA request or interrupt is generated. To select a specific mode, refer to Table 4-3 for available modes and associated bit patterns.

4 DAC0REQ DAC 0 Request Enable Ð This bit controls DMA requesting and interrupt

3 DRVAIS Drive Analog Input Sense Ð This signal controls the AI SENSE signal at

the I/O connector. AI SENSE is always used as an input in the NRSE input configuration mode irrespective of DRVAIS. If DRVAIS is set , then AI SENSE is connected to board ground unless the board is configured in the NRSE mode, in which case AI SENSE is used as an input. If DRVAIS is cleared, AI SENSE is used as an input in the NRSE input configuration, and is not driven otherwise.

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Chapter 4 Register Map and Descriptions

Bit Name Description (continued)

2-0 INTCHB<2..0> Interrupt Channel Select Ð These bits select the interrupt channel

available for use by the AT-MIO-64F-5. See Table 4-4.

Table 4-4. Interrupt Level Selection

Bit Pattern Effect

Interrupt Level Enabled

INTCHB1

INTCHB2

INTCHB0

0 0 0 Level 3

0 0 1 Level 4

0 1 0 Level 5

0 1 1 Level 7

1 0 0 Level 10

1 0 1 Level 11

1 1 0 Level 12

1 1 1 Level 15

Page 100

Command Register 4

Command Register 4 contains 16 bits that control the AT-MIO-64F-5 board clock selection, serial DAC link over the RTSI bus, DAC mode selection, and miscellaneous configuration bits. Bits 8-15 of this register are cleared upon power up or following a reset condition. Bits 0-7 of this register are undefined upon power up and are not cleared after a reset condition. These bits should be initialized through software.

Address: Base address + 06 (hex)

Type: Write-only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

CLKMODEB1 CLMODEB0 DAC1DSP DAC0DSP DACMB3 DACMB2 DACMB1 DACMB0

MSB

7 6 5 4 3210

DACGATE DB_DIS CYCLICSTOP ADCFIFOREQ SRC3SEL GATE2SEL FIFO/DAC EXTTRIG_DI

LSB

Bit Name Description

15-14 CLKMODEB<1..0> Clock Mode Select Ð These bits control the selection of the board

clock and RTSI bus clock. Upon power up, CLKMODEB1 and CLKMODEB0 are cleared. In this condition, the board is configured for internal, 10 MHz operation. For other available modes see Table 4-5 for bit patterns.

Table 4-5. Board and RTSI Clock Selection

Bit

Effect

Pattern

RTSI Clock Board Clock

CLKMODEB1

CLKMODEB0

X 0 No connection Internal, 10 MHz

0 1 Internal, 10 MHz Internal, 10 MHz

1 1 Driven onto board clock Received from RTSI clock

National Instruments AT-MIO-64F-5 Owners Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Copyright

Trademarks

Warning Regarding Medical and Clinical Use

Preface

Organization of This Manual

Conventions Used in This Manual

Related Documentation

Customer Communication

Contents

Figures

Tables

Chapter 1 Introduction

Board Description

Analog Input

Analog Output

Digital and Timing I/O

Figure 1-1. AT-MIO-64F-5 Board

What Your Kit Should Contain

Optional Software

Optional Equipment

Custom Cables

Figure 1-2. AT-MIO-64F-5 Cable Assembly

Unpacking

Chapter 2 Configuration and Installation

Board Configuration

Figure 2-1. AT-MIO-64F-5 Parts Locator Diagram

AT Bus Interface

Base I/O Address Selection

Figure 2-2. Example Base I/O Address Switch Settings

Table 2-1. Default Settings of National Instruments Products for the PC

Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space

Interrupt and DMA Channel Selection

Analog Input Configuration

Input Mode

Table 2-3. Available Input Configurations for the AT-MIO-64F-5

DIFF Input (32 Channels)

RSE Input (64 Channels)

NRSE Input (64 Channels)

Input Polarity and Input Range

Considerations for Selecting Input Ranges

Table 2-4. Actual Range and Measurement Precision Versus Input Range Selection and Gain

Analog Output Configuration

Analog Output Reference Selection

Analog Output Polarity Selection

Digital I/O Configuration

Board and RTSI Clock Configuration

Hardware Installation

Signal Connections

Figure 2-3. AT-MIO-64F-5 I/O Connector Pin Assignment

MIO Subconnector Pin Assignment

Figure 2-4. 50-Pin MIO Subconnector Pin Assignment

MIO Subconnector Signal Connection Descriptions

Extended Analog Input Subconnector Pin Assignment

Figure 2-5. Extended Analog Input Subconnector Pin Assignment

Extended Analog Input Subconnector Signal Descriptions

Analog Input Signal Connections

Figure 2-6. AT-MIO-64F-5 PGIA

Types of Signal Sources

Floating Signal Sources

Ground-Referenced Signal Sources

Input Configurations

Table 2-5. Recommended Input Configurations for Ground-Referenced

Differential Connection Considerations (DIFF Input Configuration)

Differential Connections for Ground-Referenced Signal Sources

Figure 2-7. Differential Input Connections for Ground-Referenced Signals

Differential Connections for Nonreferenced or Floating Signal Sources

Figure 2-8. Differential Input Connections for Nonreferenced Signals

Single-Ended Connection Considerations

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 2-9. Single-Ended Input Connections for Nonreferenced or Floating Signals

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

Figure 2-10. Single-Ended Input Connections for Ground-Referenced Signals

Common-Mode Signal Rejection Considerations

Analog Output Signal Connections

Figure 2-11. Analog Output Connections

Digital I/O Signal Connections