National Instruments AT-MIO-16F-5 Owners Manual

Download

Page 1

AT-MIO-16F-5

User Manual

Multifunction I/O Board for the PC AT/EISA

February 1994 Edition

Part Number 320266-01

Page 2

National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices:

Australia (03) 879 9422, Austria (0662) 435986, Belgium 02/757.00.20, Canada (Ontario) (519) 622-9310, Canada (Québec) (514) 694-8521, Denmark 45 76 26 00, Finland (90) 527 2321, France (1) 48 14 24 24, Germany 089/741 31 30, Italy 02/48301892, Japan (03) 3788-1921, Netherlands 03480-33466, Norway 32-848400, Spain (91) 640 0085, Sweden 08-730 49 70, Switzerland 056/20 51 51, U.K. 0635 523545

Page 3

Limited Warranty

The AT-MIO-16F-5 is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OF

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation, or maintenance instructions; owner's modification of the product; owner's abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

. CUSTOMER'S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

. This limitation of the liability of National Instruments will apply regardless of the form of action,

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

LabVIEW®, NI-DAQ®, and RTSI® are trademarks of National Instruments Corporation. Product and company names listed are trademarks or trade names of their respective companies.

Page 4

Warning Regarding Medical and Clinical Use

of National Instruments Products

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

Page 5

Contents

About This Manual

Organization of This Manual ........................................................................................ xi

Conventions Used in This Manual ................................................................................ xii

Related Documentation ................................................................................................. xii

Customer Communication............................................................................................. xii

Chapter 1 Introduction

AT-MIO-16F-5 Versus AT-MIO-16............................................................................. 1-2

What Your Kit Should Contain..................................................................................... 1-3

Optional Software.......................................................................................................... 1-3

Optional Equipment ...................................................................................................... 1-4

Unpacking ..................................................................................................................... 1-5

Chapter 2 Configuration and Installation

Board Configuration...................................................................................................... 2-1

Analog Input Configuration .......................................................................................... 2-9

Analog Output Configuration........................................................................................ 2-12

Hardware Installation .................................................................................................... 2-17

Signal Connections........................................................................................................ 2-17

.......................................................................................................................... 1-1

AT-MIO-16F-5 Hardware Changes from the AT-MIO-16............................... 1-2

AT Bus Interface ............................................................................................... 2-1

Base I/O Address Selection............................................................................... 2-3

DMA Channel Selection ................................................................................... 2-6

Interrupt Selection ............................................................................................. 2-7

Analog I/O Jumper Settings .............................................................................. 2-8

Input Mode ........................................................................................................ 2-9

DIFF Input (8 Channels) ....................................................................... 2-9

RSE Input (16 Channels)....................................................................... 2-10

NRSE Input (16 Channels).................................................................... 2-10

Input Polarity and Input Range ......................................................................... 2-11

Considerations for Selecting Input Ranges ........................................... 2-11

Internal and External Reference........................................................................ 2-12

External Reference Selection ................................................................ 2-12

Internal Reference Selection (Factory Setting) ..................................... 2-13

Bipolar Output Selection (Factory Setting)........................................... 2-14

Straight Binary Mode ................................................................ 2-14

Two's Complement Mode (Factory Setting) ............................. 2-15

Unipolar Output Selection..................................................................... 2-15

RTSI Bus Clock Selection................................................................................. 2-15

Signal Connection Descriptions ........................................................................ 2-18

Analog Input Signal Connections...................................................................... 2-21

...................................................................................... 2-1

Page 6

Contents

Types of Signal Sources.................................................................................... 2-22

Floating Signal Sources......................................................................... 2-22

Input Configurations.......................................................................................... 2-23

Differential Connection Considerations (DIFF Configuration) ............ 2-23

Differential Connections for Ground-Referenced Signal Sources........ 2-24

Differential Connections for Non-Referenced or Floating Signal

Sources .................................................................................................. 2-25

Single-Ended Connection Considerations............................................. 2-27

Single-Ended Connections for Floating Signal Sources

(RSE Configuration).............................................................................. 2-27

Single-Ended Connections for Grounded Signal Sources

(NRSE Configuration)........................................................................... 2-28

Common Mode Signal Rejection Considerations ................................. 2-29

Analog Output Signal Connections................................................................... 2-30

Digital I/O Signal Connections ......................................................................... 2-31

Power Connections............................................................................................ 2-33

Timing Connections .......................................................................................... 2-34

Data Acquisition and Analog Output Timing Connections .................. 2-34

General-Purpose Timing Signal Connections ....................................... 2-37

Field Wiring Considerations ............................................................................. 2-42

Cabling Considerations ..................................................................................... 2-43

Chapter 3 Theory of Operation

Functional Overview ..................................................................................................... 3-1

PC I/O Channel Interface Circuitry............................................................................... 3-2

Analog Input and Data Acquisition Circuitry ............................................................... 3-4

Analog Input Circuitry ...................................................................................... 3-6

Data Acquisition Timing Circuitry.................................................................... 3-8

Single-Channel Data Acquisition.......................................................... 3-9

Multiple-Channel (Scanned) Data Acquisition ..................................... 3-9

Data Acquisition Rates.......................................................................... 3-10

Analog Output Circuitry................................................................................................ 3-10

Digital I/O Circuitry ...................................................................................................... 3-12

Timing I/O Circuitry ..................................................................................................... 3-14

RTSI Bus Interface Circuitry ........................................................................................ 3-17

Chapter 4 Programming

Register Map ................................................................................................................. 4-1

Register Description...................................................................................................... 4-2

....................................................................................................................... 4-1

Configuration and Status Register Group ......................................................... 4-3

Command Register 1............................................................................. 4-4

Command Register 2............................................................................. 4-7

Status Register....................................................................................... 4-11

.......................................................................................................... 3-1

AT-MIO-16F-5 User Manual vi © National Instruments Corporation

Page 7

Contents

The Event Strobe Register Group ..................................................................... 4-14

Start Convert Register ........................................................................... 4-14

Start DAQ Register ............................................................................... 4-15

A/D Clear Register ................................................................................ 4-15

External Strobe Register........................................................................ 4-16

DMA TC INT Clear Register................................................................ 4-17

Analog Output Register Group.......................................................................... 4-17

DAC0 Register ...................................................................................... 4-17

DAC1 Register ...................................................................................... 4-18

DAC Update INT Clear Register .......................................................... 4-19

DAC Update Register............................................................................ 4-19

Analog Input Register Group ............................................................................ 4-20

MUXMEMLD Register ........................................................................ 4-20

MUXMEMCLR Register...................................................................... 4-20

MUXMEM Register.............................................................................. 4-21

A/D FIFO Register ................................................................................ 4-24

Am9513A Counter/Timer Register Group........................................................ 4-26

Am9513A Data Register ....................................................................... 4-26

Am9513A Command Register .............................................................. 4-28

Am9513A Status Register..................................................................... 4-28

Digital I/O Register Group................................................................................ 4-30

Digital Input Register ............................................................................ 4-30

Digital Output Register ......................................................................... 4-31

The RTSI Switch Register Group ..................................................................... 4-32

RTSI Switch Shift Register ................................................................... 4-32

RTSI Switch Strobe Register ................................................................ 4-33

Programming Considerations........................................................................................ 4-34

Initializing the AT-MIO-16F-5 Board .............................................................. 4-34

Initializing the Am9513A...................................................................... 4-35

Initializing the Analog Output Circuitry ............................................... 4-36

Programming the Analog Input Circuitry ......................................................... 4-36

Single Conversions using the SCONVERT or EXTCONV* Signal .... 4-36

A/D FIFO Output Binary Formats ........................................................ 4-37

Clearing the Analog Input Circuitry...................................................... 4-39

Posttrigger Data Acquisition Sequence............................................................. 4-40

Controlling Posttrigger Acquisition Sequences with the EXTCONV*

Signal..................................................................................................... 4-44

Pretrigger Data Acquisition Sequence .............................................................. 4-44

Controlling Pretrigger Data Acquisition Sequences

|with the EXTCONV* Signal................................................................ 4-49

Programming Data Acquisition Sequences with Channel Scanning................. 4-49

Posttrigger Data Acquisition with Continuous Channel Scanning ....... 4-50

Controlling Posttrigger Channel Scanning

with the EXTCONV* Signal................................................................. 4-56

Page 8

Contents

Pretrigger Data Acquisition with Continuous Channel Scanning..................... 4-56

Controlling Pretrigger Channel Scanning

with the EXTCONV* Signal................................................................. 4-61

Posttrigger Data Acquisition with Interval Channel Scanning ......................... 4-62

Controlling Posttrigger Interval Channel Scanning

with the EXTCONV* Signal............................................................................. 4-68

Pretrigger Data Acquisition with Interval Channel Scanning........................... 4-69

Controlling Pretrigger Interval Channel Scanning

with the EXTCONV* Signal................................................................. 4-76

Resetting the Hardware after a Data Acquisition Operation............................. 4-76

Resetting Counter 2............................................................................... 4-76

Resetting Counter 3............................................................................... 4-77

Resetting Counter 4............................................................................... 4-77

Programming the Analog Output Circuitry....................................................... 4-78

External DAC Updating .................................................................................... 4-81

Internal DAC Updating ..................................................................................... 4-82

Programming the Digital I/O Circuitry ......................................................................... 4-85

Programming the Am9513A Counter/Timer ................................................................ 4-85

RTSI Bus Trigger Line Programming Considerations.................................................. 4-87

AT-MIO-16F-5 RTSI Signal Connection Considerations ............................................ 4-88

Programming the RTSI Switch ..................................................................................... 4-88

Programming DMA Operations ........................................................................ 4-90

Interrupt Programming...................................................................................... 4-91

Chapter 5 Calibration Procedures

Calibration Equipment Requirements ........................................................................... 5-2

Reference Calibration.................................................................................................... 5-3

Input Calibration............................................................................................................ 5-4

Output Calibration......................................................................................................... 5-4

Appendix A Specifications

Analog Input.................................................................................................................. A-1

Analog Data Acquisition Rates ..................................................................................... A-3

Analog Output ............................................................................................................... A-4

Digital I/O...................................................................................................................... A-5

Timing I/O..................................................................................................................... A-5

Power Requirement (from PC I/O Channel) ................................................................. A-6

Physical ......................................................................................................................... A-6

Operating Environment ................................................................................................. A-6

Storage Environment..................................................................................................... A-6

........................................................................................................................ A-1

Explanation of Analog Input Specifications ..................................................... A-2

Single-Channel Acquisition Rates..................................................................... A-3

Multiple-Channel Scanning Acquisition Rates ................................................. A-4

Explanation of Analog Output Specifications................................................... A-5

.................................................................................................... 5-1

AT-MIO-16F-5 User Manual viii © National Instruments Corporation

Page 9

Contents

Appendix B I/O Connector

...................................................................................................................... B-1

Signal Connection Descriptions ........................................................................ B-2

Appendix C AMD Data Sheet

................................................................................................................. C-1

Appendix D Customer Communication

.............................................................................................. D-1

Index ................................................................................................................................ Index-1

Glossary ...................................................................................................................... Glossary-1

Figures

Figure 2-1. AT-MIO-16F-5 Parts Locator Diagram ............................................................ 2-2

Figure 2-2. Example Base I/O Address Switch Settings...................................................... 2-3

Figure 2-3. DMA Jumper Settings for DMA Channels 6 and 7 (Factory Setting) .............. 2-6

Figure 2-4. Interrupt Jumper Setting IRQ10 (Factory Setting)............................................ 2-7

Figure 2-5. External Reference Configuration..................................................................... 2-13

Figure 2-6. Internal Reference Configuration (Factory Setting).......................................... 2-13

Figure 2-7. Bipolar Output Configuration (Factory Setting) ............................................... 2-14

Figure 2-8. Straight Binary Mode ........................................................................................ 2-14

Figure 2-9. Two's Complement Mode (Factory Setting) ..................................................... 2-15

Figure 2-10. Unipolar Output Configuration ......................................................................... 2-15

Figure 2-11. Disconnected from RTSI Bus Clock................................................................. 2-16

Figure 2-12. Receives RTSI Clock Signal ............................................................................. 2-16

Figure 2-13. Drives RTSI Bus Clock Signal with Onboard Oscillator.................................. 2-17

Figure 2-14. AT-MIO-16F-5 I/O Connector.......................................................................... 2-18

Figure 2-15. AT-MIO-16F-5 Instrumentation Amplifier....................................................... 2-22

Figure 2-16. Differential Input Connections for Ground-Referenced Signals....................... 2-25

Figure 2-17. Differential Input Connections for Non-Referenced Signals............................ 2-26

Figure 2-18. Single-Ended Input Connections for Non-Referenced or Floating Signals ...... 2-28

Figure 2-19. Single-Ended Input Connections for Ground-Referenced Signals.................... 2-29

Figure 2-20. Analog Output Connections .............................................................................. 2-31

Figure 2-21. Digital I/O Connections..................................................................................... 2-33

Figure 2-22. EXTSTROBE* Signal Timing.......................................................................... 2-34

Figure 2-23. EXTCONV* Signal Timing.............................................................................. 2-35

Figure 2-24. EXTTRIG* Signal Timing................................................................................ 2-36

Figure 2-25. EXTDACUPDATE* Signal Timing................................................................. 2-37

Figure 2-26. Event-Counting Application with External Switch Gating............................... 2-38

Figure 2-27. Frequency Measurement Application ............................................................... 2-39

Figure 2-28. General-Purpose Timing Signals....................................................................... 2-41

Figure 3-1. AT-MIO-16F-5 Block Diagram ........................................................................ 3-1

Figure 3-2. PC I/O Channel Interface Circuitry Block Diagram ......................................... 3-3

Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram.......................... 3-5

Page 10

Contents

Figure 3-4. Analog Output Circuitry Block Diagram .......................................................... 3-11

Figure 3-5. Digital I/O Circuitry Block Diagram................................................................. 3-13

Figure 3-6. Timing I/O Circuitry Block Diagram................................................................ 3-14

Figure 3-7. Counter Block Diagram..................................................................................... 3-15

Figure 4-1. RTSI Switch Control Pattern............................................................................. 4-89

Figure 5-1. EEPROM Map .................................................................................................. 5-1

Figure B-1. AT-MIO-16F-5 I/O Connector.......................................................................... B-1

Tables

Table 1-1. AT-MIO-16F-5 Hardware Differences from the AT-MIO-16.......................... 1-2

Table 2-1. AT Bus Interface Factory Settings .................................................................... 2-1

Table 2-2. Default Settings of National Instruments Products for the PC.......................... 2-4

Table 2-3. Switch Settings with Corresponding Base I/O Address

and Base I/O Address Space ............................................................................. 2-5

Table 2-4. DMA Channels for the AT-MIO-16F-5............................................................ 2-6

Table 2-5. Analog I/O Jumper Settings .............................................................................. 2-8

Table 2-6. Input Configurations Available for the AT-MIO-16F-5 ................................... 2-9

Table 2-7. Actual Range and Measurement Precision Versus

Input Range Selection and Gain........................................................................ 2-11

Table 2-8. Configurations for RTSI Bus Clock Selection.................................................. 2-16

Table 2-9. Recommended Input Configurations for Ground-Referenced .......................... 2-23

Table 4-1. AT-MIO-16F-5 Register Map........................................................................... 4-1

Table 4-2. Input Configuration ........................................................................................... 4-6

Table 4-3. DMA and Interrupt Modes................................................................................ 4-10

Table 4-4. Straight Binary Mode A/D Conversion Values................................................. 4-38

Table 4-5. Two's Complement Mode A/D Conversion Values.......................................... 4-39

Table 4-6. Analog Output Voltage Versus Digital Code (Unipolar Mode)........................ 4-80

Table 4-7. Analog Output Voltage Versus Digital Code (Bipolar Mode).......................... 4-81

Table 4-8. RTSI Switch Signal Connections...................................................................... 4-87

Table 5-1. Calibration DACs.............................................................................................. 5-3

AT-MIO-16F-5 User Manual x © National Instruments Corporation

Page 11

About This Manual

This manual describes the mechanical and electrical aspects of the AT-MIO-16F-5 board and contains information concerning its operation and programming. The AT-MIO-16F-5 is a high-performance, multifunction analog, digital, and timing I/O board for the IBM PC AT and compatibles and EISA personal computers (PCs).

Organization of This Manual

The AT-MIO-16F-5 User Manual is organized as follows:

• Chapter 1, Introduction, describes the AT-MIO-16F-5; lis``ts the contents of your AT-MIO-16F-5 kit, the optional software, and optional equipment; and explains how to unpack the AT-MIO-16F-5.

• Chapter 2, Configuration and Installation, describes the AT-MIO-16F-5 jumper configuration, installation of the AT-MIO-16F-5 in the PC, signal connections to the AT-MIO-16F-5, and cable wiring.

• Chapter 3, Theory of Operation, contains a functional overview of the AT-MIO-16F-5 and explains the operation of each functional unit making up the AT-MIO-16F-5.

• Chapter 4, Programming, describes in detail the address and function of each of the AT-MIO-16F-5 registers. This chapter also includes important information about programming the AT-MIO-16F-5.

• Chapter 5, Calibration Procedures, discusses the calibration procedures for the AT-MIO-16F-5 analog input and analog output circuitry.

• Appendix A, Specifications, lists the specifications for the AT-MIO-16F-5.

• Appendix B, I/O Connector, shows the pinout and signal names for the AT-MIO-16F-5 50-pin I/O connector, including a description of each connection.

• Appendix C, AMD Data Sheet, contains the AMD Am9513A System Timing Controller (Advanced Micro Devices, Inc.) data sheet. This controller is used on the AT-MIO-16F-5.

• Appendix D, Customer Communication, contains forms for you to complete to facilitate communication with National Instruments concerning our products.

• The Index alphabetically lists topics covered in this manual, including the page where the topic can be found.

Page 12

About This Manual

Conventions Used in This Manual

The following conventions are used in this manual: italic Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

PC PC refers to the IBM PC AT and compatibles, and to EISA personal

computers.

Related Documentation

The following document contains information that you may find helpful as you read this manual:

• The IBM Personal Computer AT Technical Reference manual

You may also want to consult the following Advanced Micro Devices manual if you plan to program the Am9513A Counter/Timer used on the AT-MIO-16F-5:

• The Am9513A/Am9513 System Timing Controller technical manual

Customer Communication

We appreciate communicating with the people who use our products. We are also very interested in hearing about the applications you develop using our products. To make it easy for you to communicate with us, this manual contains forms for to you complete. These forms are located in Appendix D, Customer Communication, at the back of this manual.

AT-MIO-16F-5 User Manual xii © National Instruments Corporation

Page 13

Chapter 1 Introduction

This chapter describes the AT-MIO-16F-5; lists the contents of your AT-MIO-16F-5 kit, the optional software, and optional equipment; and explains how to unpack the AT-MIO-16F-5.

The AT-MIO-16F-5 is a high-performance multifunction analog, digital, and timing I/O board for the PC. The AT-MIO-16F-5 has a 5 µsec, 12-bit, sampling ADC; 16 single-ended or 8 differential channels (expandable with AMUX-64T multiplexer board); programmable gains of

0.5, 1, 2, 5, 10, 20, 50 and 100; a guaranteed maximum rate of at least 200 ksamples/sec; a

256-word A/D FIFO buffer to obtain the highest possible data acquisition rate; and internal or external A/D timing. The AT-MIO-16F-5 also has two double-buffered, multiplying, 12-bit DACs; unipolar and bipolar voltage output; an onboard DAC reference voltage of 10 V; internal timer and external signal update capability for waveform generation; onboard I/O hardware auto calibration circuitry; eight digital I/O lines able to sink up to 24 mA of current; three independent 16-bit counter/timers for frequency counting, event counting, and pulse output applications; timer-generated interrupts; high-performance RTSI bus interface; four triggers for system-level timing; and full PC I/O channel DMA capability with both analog input and analog output. If additional analog inputs are required, you can use the AMUX-64T multiplexer board. This four-to-one multiplexer can process 64 single-ended or 32 differential inputs. Up to four AMUX-64Ts can be cascaded to obtain 256 single-ended inputs.

The AT-MIO-16F-5, with its multifunction analog, digital, and timing I/O, can be used in many applications for automation of machine and process control, level monitoring and control, instrumentation, electronic testing, and various other functions. The multichannel analog input can be used for such functions as signal and transient analysis, data logging, and chromatography. The two analog output channels can be used for such functions as machine and process control, analog function generation, 12-bit resolution voltage source, and programmable signal attenuation. The eight TTL-compatible digital I/O lines can be used for machine and process control, intermachine communication, and relay switching control. The three 16-bit counter/timers can be used for such functions as pulse and clock generation, timed control of laboratory equipment, and frequency, event, and pulse-width measurement. With all of these functions on one board, laboratory processes can be automatically monitored and controlled.

The AT-MIO-16F-5 is interfaced to the National Instruments RTSI bus. With this bus, National Instruments AT Series boards can send timing signals to each other. The AT-MIO-16F-5 can send signals from the onboard counter/timer to another board, or another board can control single and multiple A/D conversions on the AT-MIO-16F-5.

Detailed specifications for the AT-MIO-16F-5 are listed in Appendix A.

Page 14

Introduction Chapter 1

AT-MIO-16F-5 Versus AT-MIO-16

As the next step in the National Instruments MIO board line, the AT-MIO-16F-5 incorporates functional improvements and additions to the older AT-MIO-16 boards. Because the AT-MIO-16F-5 is a superset of the AT-MIO-16 line of boards, any function on the AT-MIO-16 is available on the AT-MIO-16F-5. The following is a listing of the additional functions of the AT-MIO-16F-5.

• 200 kHz Throughput • More Gains: 0.5, 1, 2, 5, 10, 20, 50, 100

•5 µsec Settling at all Gains • Software Configurable Analog Input

• 512-Long Channel-Gain Memory • Expanded Timebase Resolution (200 nsec)

• 256-Deep ADC FIFO • Software Pretriggering

• DMA to Analog Output • Software and Hardware Acquisition Gating

• DAC Update Error Signal • Selectable Counter for Waveform Generation

• 0.5 LSB rms Analog Output Noise • 4 µsec Analog Output Settling (DC - 500 kHz)

• Full Acquisition Modes Using the • Dedicated DAC Update Signal at the I/O EXTCONV* Signal at the I/O Connector Connector

• Higher Effective Resolution • Multiple Rate Data Acquisition with Channel (with Dither and Averaging) Scanning

• Software Calibratable Analog Input and • AI SENSE is not grounded in the differential Analog Output with Onboard Voltage analog input configuration. Reference

AT-MIO-16F-5 Hardware Changes from the AT-MIO-16

The hardware changes between the AT-MIO-16F-5 and the AT-MIO-16 are listed in the following table.

Table 1-1. AT-MIO-16F-5 Hardware Differences from the AT-MIO-16

Hardware Differences

AT-MIO-16 AT-MIO-16F-5

I/O Connector

Pin 38 STARTTRIG* EXTTRIG* Pin 39 STOPTRIG EXTGATE* Pin 44 SOURCE2 EXTDACUPDATE*

RTSI Switch

A4RCV STOPTRIG DACUPTRIG*

AT-MIO-16F-5 User Manual 1-2 © National Instruments Corporation

Page 15

Chapter 1 Introduction

What Your Kit Should Contain

The contents of the AT-MIO-16F5 kit (part number 776441-01) are listed as follows.

Kit Component Part Number

AT-MIO-16F5 board

AT-MIO-16F-5 User Manual

NI-DAQ software for DOS/Windows/LabWindows, with manuals

NI-DAQ Software Reference Manual for DOS/Windows/LabWindows NI-DAQ Function Reference Manual for DOS/Windows/LabWindows

If your kit is missing any of the components, contact National Instruments. Your AT-MIO-16F5 is shipped with the NI-DAQ software for DOS/Windows/LabWindows.

NI-DAQ has a library of functions that can be called from your application programming environment. These functions include routines for analog input (A/D conversion), buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion), waveform generation, digital I/O, counter/timer, SCXI, RTSI, and self-calibration. NI-DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code. NI-DAQ comes with language interfaces for Professional BASIC, Turbo Pascal, Turbo C, Turbo C++, Borland C++, and Microsoft C for DOS; and Visual Basic, Turbo Pascal, Microsoft C with SDK, and Borland C++ for Windows. NI-DAQ software is on high-density 5.25 in. and 3.5 in. diskettes.

180985-01 320266-01 776250-01 320498-01 320499-01

Optional Software

This manual contains complete instructions for directly programming the AT-MIO-16F-5. Normally, however, you should not need to read the low-level programming details in the user manual because the NI-DAQ software package for controlling the AT-MIO-16F-5 is included with the board. Using NI-DAQ is quicker and easier than and as flexible as using the low-level programming described in Chapter 4, Programming.

You can use the AT-MIO-16F-5 with LabVIEW for Windows or LabWindows for DOS. LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications. LabVIEW uses graphical programming, whereas LabWindows enhances Microsoft C and QuickBASIC. Both packages include extensive libraries for data acquisition, instrument control, data analysis, and graphical data presentation.

Page 16

Introduction Chapter 1

Part numbers for these software packages are listed in the following table.

Software Part Number

LabVIEW for Windows LabWindows

Standard package Advanced Analysis Library Standard package with the Advanced Analysis Library

Optional Equipment

Equipment Part Number

CB-50 I/O connector block (50 screw terminals)

with 0.5-m type NB1 cable 776164-01 with 1.0-m type NB1 cable 776164-02

AT Series RTSI bus cables for

2 boards 776249-02 3 boards 776249-03 4 boards 776249-04 5 boards 776249-05

AMUX-64T analog multiplexer board

with 0.2-m ribbon cable 776366-02 with 0.5-m ribbon cable 776366-05 with 1.0-m ribbon cable 776366-10 with 2.0-m ribbon cable 776366-20

776670-01 776473-01

776474-01 776475-01

The AT-MIO-16F-5 I/O connector is a 50-pin, male, ribbon cable header. The manufacturer part numbers for this header are as follows:

• Electronic Products Division/3M (part number 3596-5002)

• T&B/Ansley Corporation (part number 609-5007)

AT-MIO-16F-5 User Manual 1-4 © National Instruments Corporation

Page 17

Chapter 1 Introduction

The mating connector for the AT-MIO-16F-5 is a 50-position, ribbon socket connector, polarized, with strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent misconnection to the AT-MIO-16F-5. Recommended manufacturer part numbers for this mating connector are as follows:

• Electronic Products Division/3M (part number 3425-7650)

• T&B/Ansley Corporation (part number 609-5041CE)

Recommended manufacturer part numbers for the standard ribbon cable (50-conductor, 28 AWG, stranded) that can be used with these connectors are:

• Electronic Products Division/3M (part number 3365/50)

• T&B/Ansley Corporation (part number 171-50)

Unpacking

Your AT-MIO-16F-5 board is shipped in an antistatic plastic package to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, take the following precautions:

• Touch the plastic package to a metal part of your PC chassis before removing the board from the package.

• Remove the board from the package and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. Do

not install a damaged board into your computer.

Page 18

Chapter 2 Configuration and Installation

This chapter describes the AT-MIO-16F-5 jumper configuration, installation of the AT-MIO-16F-5 board in the PC, signal connections to the AT-MIO-16F-5 board, and cable wiring.

Board Configuration

The AT-MIO-16F-5 contains 13 jumpers and one DIP switch to configure the AT bus interface and analog output settings. The DIP switch is used to set the base I/O address. Four jumpers are used as interrupt and DMA channel selectors. Six of the remaining nine jumpers are used to configure the analog output circuitry. The jumpers are shown in the parts locator diagram in Figure 2-1. Jumpers W8 through W13 configure the analog output circuitry. Jumpers W1 and W2 select the clock signal used by both the Am9513A Counter/Timer and the clock pin on the RTSI bus. Jumpers W4, W5, W6, and W7 select the DMA channel and the interrupt level. Jumper W3 is used for initial calibration functions and should not be changed, so it is removed from the board before shipping.

AT Bus Interface

The AT-MIO-16F-5 is configured at the factory to a base I/O address of 220 hex, to use DMA Channel 6 and Channel 7, and to use interrupt level 10. These settings (shown in Table 2-1) are suitable for most systems. However, if your system has other hardware at this base I/O address, DMA channel, or interrupt level, you need to change these factory settings on the AT-MIO-16F-5 (as described in the following pages) or on the other hardware.

Table 2-1. AT Bus Interface Factory Settings

Base I/O Address Hex 220

DMA A = DMA Channel 6

DMA Channel

Interrupt Level Interrupt level 10 selected

DMA B = DMA Channel 7 (factory setting)

(factory setting)

(The shaded portion indicates the side of the base address switch that is pressed down.)

W4: R6: A-B A6: A-B W4: R7: B-C A7: B-C W7: no jumpers

W5: Row 10 W6: no jumpers

A9A8A7A6A5

12345

U67

Page 19

Page 20

Chapter 2 Configuration and Installation

Base I/O Address Selection

The base I/O address for the AT-MIO-16F-5 is determined by the switches at position U67 (see Figure 2-1). The switches are set at the factory for the base I/O address 220 hex. This factory setting is used by National Instruments software packages as the default base I/O address value for the AT-MIO-16F-5. The AT-MIO-16F-5 uses the base I/O address space 220 hex through 23F hex with the factory setting.

Note: Verify that this space is not already used by other equipment installed in your computer.

If any equipment in your computer uses this base I/O address space, change the base I/O address of the AT-MIO-16F-5 or of the other device. If you change the AT-MIO-16F-5 base I/O address, make a corresponding change to any software packages you use with the AT-MIO-16F-5. Table 2-2 lists the default settings of other National Instruments products for the PC. For more information about the I/O address of your PC, refer to the technical reference manual for your computer.

Each switch in U67 corresponds to one of the address lines A9 through A5. Press the side marked OFF to select a binary value of 1 for the corresponding address bit . Press the ON side of the switch to select a binary value of 0 for the corresponding address bit. Figure 2-2 shows two possible switch settings. The shaded portion indicates the side of the switch that is pressed down.

12345

This side down for 0 This side down for 1

A. Switches Set to Base I/O Address of Hex 000

This side down for 0 This side down for 1

B. Switches Set to Base I/O Address of Hex 220 (Factory Setting)

O N

O F F

A9A5A7

12345

O N

O F F

U67

Figure 2-2. Example Base I/O Address Switch Settings

The least significant five bits of the address (A4 through A0) are decoded by the AT-MIO-16F-5 to select the appropriate AT-MIO-16F-5 register. To change the base I/O address, remove the plastic cover on U67; press each switch to the desired position; verify that each switch is pressed down all the way; and replace the plastic cover. Make a note of the new AT-MIO-16F-5 base I/O address for use when configuring the AT-MIO-16F-5 software (a form is included for you in Appendix D).

Page 21

Configuration and Installation Chapter 2

Table 2-3 lists the possible switch settings, the corresponding base I/O address, and the base I/O address space used for that setting.

Table 2-2. Default Settings of National Instruments Products for the PC

Board DMA Channel Interrupt Level Base I/O Address

AT-A2150 AT-AO-6/10 AT-DIO-32F AT-DSP2200 AT-GPIB AT-MIO-16 AT-MIO-16D AT-MIO-16F-5 AT-MIO-16X AT-MIO-64F-5 GPIB-PCII GPIB-PCIIA GPIB-PCIII Lab-PC PC-DIO-24 PC-DIO-96 PC-LPM-16 PC-TIO-10

None* Channel 5 Channels 5, 6 None* Channel 5 Channels 6, 7 Channels 6, 7 Channels 6, 7 None* None* Channel 1 Channel 1 Channel 1 Channel 3 None None None None

None* Lines 11, 12 Lines 11, 12 None* Line 11 Line 10 Lines 5, 10 Line 10 None* None* Line 7 Line 7 Line 7 Line 5 Line 5 Line 5 Line 5 Line 5

* These settings are software configurable and are disabled at startup time.

120 hex 1C0 hex 240 hex 120 hex 2C0 hex 220 hex 220 hex 220 hex 220 hex 220 hex 2B8 hex 02E1 hex 280 hex 260 hex 210 hex 180 hex 260 hex 1A0 hex

AT-MIO-16F-5 User Manual 2-4 © National Instruments Corporation

Page 22

Chapter 2 Configuration and Installation

Table 2-3. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space

Switch Setting Base I/O Address Base I/O Address

A9 A8 A7 A6 A5 (hex) Space Used (hex)

0 0 0 0 0 000 000 - 01F 0 0 0 0 1 020 020 - 03F 0 0 0 1 0 040 040 - 05F 0 0 0 1 1 060 060 - 07F 0 0 1 0 0 080 080 - 09F 0 0 1 0 1 0A0 0A0 - 0BF 0 0 1 1 0 0C0 0C0 - 0DF 0 0 1 1 1 0E0 0E0 - 0FF 0 1 0 0 0 100 100 - 11F 0 1 0 0 1 120 120 - 13F 0 1 0 1 0 140 140 - 15F 0 1 0 1 1 160 160 - 17F 0 1 1 0 0 180 180 - 19F 0 1 1 0 1 1A0 1A0 - 1BF 0 1 1 1 0 1C0 1C0 - 1DF 0 1 1 1 1 1E0 1E0 - 1FF 1 0 0 0 0 200 200 - 21F 1 0 0 0 1 220 220 - 23F 1 0 0 1 0 240 240 - 25F 1 0 0 1 1 260 260 - 27F 1 0 1 0 0 280 280 - 29F 1 0 1 0 1 2A0 2A0 - 2BF 1 0 1 1 0 2C0 2C0 - 2DF 1 0 1 1 1 2E0 2E0 - 2FF 1 1 0 0 0 300 300 - 31F 1 1 0 0 1 320 320 - 33F 1 1 0 1 0 340 340 - 35F 1 1 0 1 1 360 360 - 37F 1 1 1 0 0 380 380 - 39F 1 1 1 0 1 3A0 3A0 - 3BF 1 1 1 1 0 3C0 3C0 - 3DF 1 1 1 1 1 3E0 3E0 - 3FF

Note: Base I/O address values 000 through 0FF hex are reserved for

system use. Base I/O address values 100 through 3FF hex are available on the I/O channel.

Page 23

Configuration and Installation Chapter 2

•

DMA Channel Selection

The DMA channels used by the AT-MIO-16F-5 are selected by jumpers on W4 and W7 (see Figure 2-1). The AT-MIO-16F-5 is set at the factory to use DMA Channel 6 and Channel 7 for dual DMA mode. These are the default DMA channels used by the AT-MIO-16F-5 software handler. Verify that these DMA channels are not also used by equipment already installed in your computer. If any device uses DMA Channel 6 and/or Channel 7, change the DMA channel used by either the AT-MIO-16F-5 or the other device. (Unless the appropriate DMA modes have been enabled on the AT-MIO-16F-5 through software, the DMA channels are by default in the high-impedance state at startup.) The DMA channels supported by the AT-MIO-16F-5 hardware are Channel 0 through Channel 3 and Channel 5 through Channel 7. If the AT-MIO-16F-5 is used in an AT-type computer, only DMA Channels 5 through 7 should be used since these are the only 16-bit channels. If the board is used in an EISA computer, all of the channels are 16-bit and can be used. The AT-MIO-16F-5 does not use and cannot be configured to use the 8-bit DMA channels on the PC I/O channel.

Each DMA channel consists of two signal lines as shown in Table 2-4.

Table 2-4. DMA Channels for the AT-MIO-16F-5

DMA DMA DMA

Channel Acknowledge Request

0 DACK0 (A0) DRQ0 (R0) 1 DACK1 (A1) DRQ1 (R1) 2 DACK2 (A2) DRQ2 (R2) 3 DACK3 (A3) DRQ3 (R3) 5 DACK5 (A5) DRQ5 (R5) 6 DACK6 (A6) DRQ6 (R6) 7 DACK7 (A7) DRQ7 (R7)

Two jumpers must be installed to select a single DMA channel. The DMA acknowledge and DMA request lines selected must have the same number suffix for proper operation. When you use dual DMA mode, the lower rows of W6 are used for DMA A and the upper two rows of W6 are used for DMA B. Figure 2-3 displays the jumper positions for selecting DMA Channel 6 and Channel 7. In this setting, DMA A uses DMA Channel 6, and DMA B uses DMA Channel 7.

W4 W7

•

••

R7A7R6

Figure 2-3. DMA Jumper Settings for DMA Channels 6 and 7 (Factory Setting)

AT-MIO-16F-5 User Manual 2-6 © National Instruments Corporation

Page 24

Chapter 2 Configuration and Installation

If you want to use only one DMA channel, programming the DMA mode in Command Register 2 places DMA B in the high-impedance state.

If you do not want to use DMA for AT-MIO-16F-5 transfers, disabling DMAEN in Command Register 2 places DMA Channel A and DMA Channel B in the high-impedance state.

Interrupt Selection

The AT-MIO-16F-5 board can connect to any one of the eleven interrupt lines of the PC I/O channel. The interrupt line is selected by a jumper on one of the double rows of pins located above the I/O slot edge connector on the AT-MIO-16F-5 (refer to Figure 2-1). To use the interrupt capability of the AT-MIO-16F-5, select an interrupt line and place the jumper in the appropriate position to enable that particular interrupt line.

The AT-MIO-16F-5 can share interrupt lines with other devices. (Unless the appropriate interrupt modes have been enabled on the AT-MIO-16F-5 through software, the interrupt line is by default in the high impedance state at startup.) The interrupt lines supported by the AT-MIO-16F-5 hardware are IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15.

Note: Do not use interrupt line 6 or 14. Interrupt line 6 is used by the diskette drive controller,

and interrupt line 14 is used by the hard disk controller on most PCs.

Once you have selected an interrupt level, place the interrupt jumper on the appropriate pins to enable the interrupt line.

The interrupt jumper set is W5 and W6. The default interrupt line is IRQ10, which is selected by placing the jumper on the pins in row 10. Figure 2-4 shows the default interrupt jumper setting IRQ10. To change to another line, remove the jumper from IRQ10 and place it on the new pins.

34567

•

•••••

•

IRQ

•

91011121415

•••••

W5 W6

•

Figure 2-4. Interrupt Jumper Setting IRQ10 (Factory Setting)

If you do not want to use interrupts for AT-MIO-16F-5 transfers, then disabling INTEN, DMATCINTEN, and CMPLINTEN in Command Register 2 places the selected interrupt in the high impedance state.

Page 25

Configuration and Installation Chapter 2

Analog I/O Jumper Settings

The AT-MIO-16F-5 is shipped from the factory with the following configuration:

• ±10 V analog output range with internal reference selected

• Two's complement analog output coding

• AT-MIO-16F-5 clock signal set to 10 MHz

Table 2-5 lists all the available analog I/O jumper configurations for the AT-MIO-16F-5 and notes the factory settings. Other analog I/O configurations are selected through software and are detailed in the following pages.

Table 2-5. Analog I/O Jumper Settings

Configuration Jumper/Switch Settings

Am9513A and AT-MIO-16F-5 clock signal = W1: B-C RTSI Bus 10 MHz (factory setting) W2: B-C Clock Select AT-MIO-16F-5 clock signal = W1: A-B

RTSI clock signal W2: A-B

AT-MIO-16F-5 and RTSI clock W1: A-B

signals both = 10 MHz W2: B-C

DAC0 Internal (factory setting) W11: A-B Reference External W11: B-C

DAC1 Internal (factory setting) W8: A-B Reference External W8: B-C

DAC0 Output Unipolar - straight binary W10: A-B W13: B-C Polarity - Bipolar - two's complement W10: B-C W13: A-B Digital Format (factory setting)

DAC1 Output Unipolar - straight binary W9: A-B W12: B-C

Polarity - Bipolar - two's complement W9: B-C W12: A-B Digital Format (factory setting)

AT-MIO-16F-5 User Manual 2-8 © National Instruments Corporation

Page 26

Chapter 2 Configuration and Installation

Analog Input Configuration

The analog input section of the AT-MIO-16F-5 is fully software-configurable. You can select different analog input configurations by setting the appropriate bits in the command registers as described in Chapter 4, Programming. The following paragraphs describe each of the analog input categories in detail.

Input Mode

The AT-MIO-16F-5 offers three different input modes: non-referenced single-ended (NRSE) input, referenced single-ended (RSE) input, and differential (DIFF) input. The single-ended input configurations use 16 channels. The DIFF input configuration uses 8 channels. These configurations are described in Table 2-6.

Table 2-6. Input Configurations Available for the AT-MIO-16F-5

Configuration Description

DIFF Differential configuration.

Provides 8 differential inputs with the negative (-) input of the instrumentation amplifier tied to the multiplexer output of Channels 8 through 15.

RSE Referenced Single-Ended configuration.

Provides 16 single-ended inputs with the negative (-) input of the instrumentation amplifier referenced to analog ground.

NRSE Non-Referenced Single-Ended configuration.

Provides 16 single-ended inputs with the negative (-) input of the instrumentation amplifier tied to AISENSE and not connected to ground.

While reading the following paragraphs, you may find it helpful to refer to Analog Input Signal Connections later in this chapter, which contains diagrams showing the signal paths for the three configurations.

DIFF Input (8 Channels)

DIFF input means that each input signal has its own reference, and the difference between each signal and its reference is measured. The signal and its reference are assigned an input channel. With this input configuration, the AT-MIO-16F-5 can monitor eight different analog input signals. This configuration is selected via software. (See Command Register 1 and Table 4-2 in Chapter 4.) The results of this configuration are as follows:

• Channels 0 through 7 are tied to the positive (+) input of the instrumentation amplifier.

• Channels 8 through 15 are tied to the negative (-) input of the instrumentation amplifier.

Page 27

Configuration and Installation Chapter 2

• Multiplexer control is configured to control eight input channels.

• AI SENSE is left unconnected. Considerations in using the DIFF input configuration are discussed under Signal Connections

later in this chapter. Figure 2-16 shows a schematic diagram of this configuration.

RSE Input (16 Channels)

RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT-MIO-16F-5 board. The negative (-) input of the differential input amplifier is tied to the analog ground. This configuration is useful when measuring floating signal sources. See Types of Signal Sources later in this chapter for more information. With this input configuration, the AT-MIO-16F-5 can monitor 16 different analog input signals. This configuration is selected via software. (See Command Register 1 and Table 4-2 in Chapter 4.) The results of this configuration are as follows:

• The negative (-) input of the instrumentation amplifier is tied to the instrumentation amplifier signal ground.

• Multiplexer outputs are tied together into the positive (+) input of the instrumentation amplifier.

• Multiplexer control is configured to control 16 input channels.

• AI SENSE is left unconnected.

Considerations in using the RSE configuration are discussed under Signal Connections later in this chapter. Figure 2-18 shows a schematic diagram of this configuration.

NRSE Input (16 Channels)

NRSE input means that all input signals are referenced to the same common mode voltage, but this common mode voltage can float with respect to the analog ground of the AT-MIO-16F-5 board. This common mode voltage is subsequently subtracted out by the input instrumentation amplifier. This configuration is useful when measuring ground-referenced signal sources. See Types of Signal Sources later in this chapter for more information. With this input configuration, the AT-MIO-16F-5 can measure 16 different analog input signals. This configuration is selected via software. (See Command Register 1 and Table 4-2 in Chapter 4.) The results of this configuration are as follows:

• AI SENSE is tied into the negative (-) input of the instrumentation amplifier.

• Multiplexer outputs are tied together into the positive (+) input of the instrumentation

amplifier.

• Multiplexer control is configured to control 16 input channels.

Considerations in using the NRSE configuration are discussed under Signal Connections later in this chapter. Figure 2-19 shows a schematic diagram of this configuration.

AT-MIO-16F-5 User Manual 2-10 © National Instruments Corporation

Page 28

Chapter 2 Configuration and Installation

Input Polarity and Input Range

The AT-MIO-16F-5 has two polarities: unipolar input and bipolar input. Unipolar input means that the input voltage range is between 0 and V Bipolar input means that the input voltage range is between -V AT-MIO-16F-5 has one input range of 10 V. An input range of 20 V is achieved by using the gain of 0.5. Polarity and range settings are selected by writing to registers on the AT-MIO-16F-5.

Considerations for Selecting Input Ranges

Input polarity/range selection depends on the expected input range of the incoming signal. A large input range can accommodate a large signal variation but sacrifices voltage resolution. Choosing a smaller input range increases voltage resolution but can result in the input signal going out of range. For best results, the input range should be matched as closely as possible to the expected range of the input signal. For example, if the input signal is guaranteed never to swing below 0 V, a unipolar input is best. In this configuration, however, if the signal does swing negative, inaccurate readings occur.

Software-programmable gain on the AT-MIO-16F-5 increases overall flexibility by matching input signal ranges to those accommodated by the AT-MIO-16F-5 ADC. The AT-MIO-16F-5 board has gains of 0.5, 1, 2, 5, 10, 20, 50 and 100 and is well suited to a wide variety of signal levels. With the proper gain setting, the full resolution of the ADC can be used to measure the input signal. Table 2-7 shows the overall input range and precision according to the input range configuration and gain used.

where V

ref

is some positive reference voltage.

ref

and +V

ref

. The

Table 2-7. Actual Range and Measurement Precision Versus Input Range Selection and Gain

Range Configuration Gain Actual Input Range Precision*

0 to +10 V 0.5 0 to +20.0 V† 4.88 mV

1.0 0 to +10.0 V 2.44 mV

2.0 0 to +5.0 V 1.22 mV

5.0 0 to +2.0 V 488.00 µV

10.0 0 to +1.0 V 244.00 µV

20.0 0 to +0.5 V 122.00 µV

50.0 0 to +0.2 V 48.80 µV

100.0 0 to 100.0 mV 24.40 µV

(continues)

Page 29

Configuration and Installation Chapter 2

Table 2-7. Actual Range and Measurement Precision Versus Input Range Selection and Gain

(continued)

Range Configuration Gain Actual Input Range Precision*

-5 to +5 V 0.5 -10.00 to +10.00 V 4.88 mV

1.0 -5.00 to +5.00 V 2.44 mV

2.0 -2.50 to +2.50 V 1.22 mV

5.0 -1.00 to +1.00 V 488.00 µV

10.0 -0.50 to +0.50 V 244.00 µV

20.0 -0.25 to +0.25 V 122.00 µV

50.0 -100.00 to 100.00 mV 48.80 µV

100.0 -50.00 to +50.00 mV 24.40 µV

* The value of 1 LSB of the 12-bit ADC, that is, the voltage increment

corresponding to a change of 1 count in the ADC 12-bit count.

† 0 to +20 V is the effective range. Signals greater than +12 V with respect to the

AT-MIO-16F-5 AGND will saturate internal components and result in inaccurate data.

Note: See specifications in Appendix A for absolute maximum ratings.

Analog Output Configuration

You can select different analog output configurations by using the jumper settings shown in Table 2-5. The following paragraphs describe each of the analog output configurations in detail.

Internal and External Reference

Each DAC can be connected to the AT-MIO-16F-5 internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I/O connector. This signal applied to EXTREF must be between -10 V and +10 V. Both channels need not be configured the same way.

External Reference Selection

You select the external reference signal for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W11 B - C External reference signal connected to DAC 0

reference input.

Analog Output Channel 1: W8 B - C External reference signal connected to DAC 1

reference input.

AT-MIO-16F-5 User Manual 2-12 © National Instruments Corporation

Page 30

Chapter 2 Configuration and Installation

This configuration is shown in Figure 2-5.

W11

•

CBACBA

Channel 0 Channel 1

Figure 2-5. External Reference Configuration

Internal Reference Selection (Factory Setting)

You set the onboard 10 V reference for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W11 A - B 10 V onboard reference connected to DAC 0

reference input.

Analog Output Channel 1: W8 A - B 10 V onboard reference connected to DAC 1

reference input.

This configuration is shown in Figure 2-6.

W11

ABC

Channel 0 Channel 1

Figure 2-6. Internal Reference Configuration (Factory Setting)

Analog Output Polarity Selection

Each analog output channel can be configured for either unipolar or bipolar output. A unipolar

••

configuration has a range of 0 to V of -V

to +V

ref

at the analog output. V

ref

analog output circuitry and can either be the 10 V onboard reference or an externally supplied reference between -10 V and +10 V. Both channels need not be configured the same way; however, at the factory, both channels are configured for bipolar output.

at the analog output. A bipolar configuration has a range

ref

is the voltage reference used by the DACs in the

ref

Page 31

Configuration and Installation Chapter 2

Bipolar Output Selection (Factory Setting)

You select the bipolar output configuration for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W10 B - C Analog Output Channel 1: W9 B - C This configuration is shown in Figure 2-7.

W10

•

CBACBA

Channel 0 Channel 1

Figure 2-7. Bipolar Output Configuration (Factory Setting)

When you use the bipolar configuration, you must select whether to write straight binary or two's complement to the DAC. In straight binary mode, data values written to the analog output channel range from 0 to 4095 decimal (0 to 0FFF hex). In two's complement mode, data values written to the the analog output channel range from -2048 to +2047 decimal (F800 to 07FF hex).

Straight Binary Mode The data value written to each analog output channel is interpreted as a straight binary number

when the following jumpers are set: Analog Output Straight Binary for Channel 0: W13 B - C Analog Output Straight Binary for Channel 1: W12 B - C This configuration is shown in Figure 2-8.

•

W13

A B C

W12

•

A B C

Channel 0 Channel 1

Figure 2-8. Straight Binary Mode

AT-MIO-16F-5 User Manual 2-14 © National Instruments Corporation

Page 32

Chapter 2 Configuration and Installation

Two's Complement Mode (Factory Setting) The data value written to each analog output channel is interpreted as a two's complement

number when the following jumpers are set. Analog Output Two's Complement for Channel 0: W13 A - B Analog Output Two's Complement for Channel 1: W12 A - B This configuration is shown in Figure 2-9.

W13

A B C

•

W12

A B C

•

Channel 0 Channel 1

Figure 2-9. Two's Complement Mode (Factory Setting)

Unipolar Output Selection

You select the unipolar output configuration for each analog output channel by setting the following jumpers:

Analog Output Channel 0: W10 A - B Analog Output Channel 1: W9 A - B Notice that the straight binary format should be used when in unipolar output mode. This configuration is shown in Figure 2-10.

••

W10

ABC

Channel 0 Channel 1

Figure 2-10. Unipolar Output Configuration

RTSI Bus Clock Selection

When multiple AT Series boards are connected via the RTSI bus, you may want to have all the boards use the same 10-MHz clock. This arrangement is useful for applications that require counter/timer synchronization between boards. Each AT Series board with a RTSI bus interface has an onboard 10-MHz oscillator. Thus, one board can drive the RTSI bus clock signal, and the other boards can receive this signal or disconnect from it.

Page 33

Configuration and Installation Chapter 2

The configuration for jumpers W1 and W2 control whether a board drives the onboard 10-MHz oscillator onto the RTSI bus, receives the RTSI bus clock, or disconnects from the RTSI bus clock. This clock source, whether local or RTSI signal, is then divided by 10 and used as the Am9513A frequency source.

The jumper selections are as follows:

Table 2-8. Configurations for RTSI Bus Clock Selection

Configuration W1/W2

Disconnect board from RTSI bus clock; use local W1: B-C (factory setting)

oscillator W2: B-C

Receive RTSI bus clock signal W1: A-B

W2: A-B

Drive RTSI bus clock signal with local oscillator W1: A-B

W2: B-C

Figures 2-11, 2-12, and 2-13 show the jumper positions for each of the configurations previously described.

•

B C

•

ABC

Figure 2-11. Disconnected from RTSI Bus Clock; Use Onboard Oscillator (Factory Setting)

•C

ABC

•

Figure 2-12. Receives RTSI Clock Signal

AT-MIO-16F-5 User Manual 2-16 © National Instruments Corporation

Page 34

Chapter 2 Configuration and Installation

A B

•C

•

ABC

Figure 2-13. Drives RTSI Bus Clock Signal with Onboard Oscillator

Hardware Installation

The AT-MIO-16F-5 can be installed in any available 16-bit expansion slot (AT Series) in your computer. The AT-MIO-16F-5 does not work if installed in an 8-bit expansion slot (PC Series). After you have made any necessary changes, verified, and recorded the switches and jumper settings (a form is included in Appendix D), you are ready to install the AT-MIO-16F-5. The following are general installation instructions, but consult the user manual or technical reference manual of your PC for specific instructions and warnings.

1. Turn off your computer.

2. Remove the top cover or access port to the I/O channel.

3. Remove the expansion slot cover on the back panel of the computer.

4. Insert the AT-MIO-16F-5 into a 16-bit slot. Do not force the board into place.

5. Screw the mounting bracket of the AT-MIO-16F-5 to the back panel rail of the computer.

6. Check the installation.

7. Replace the cover.

The AT-MIO-16F-5 board is installed and ready for operation.

Signal Connections

This section describes input and output signal connections to the AT-MIO-16F-5 board via the AT-MIO-16F-5 I/O connector, and includes specifications and connection instructions for the signals given on the AT-MIO-16F-5 I/O connector.

Warning: Connections that exceed any of the maximum ratings of input or output signals on

the AT-MIO-16F-5 can result in damage to the AT-MIO-16F-5 board and to the PC. Maximum input ratings for each signal are given in this chapter under the discussion of that signal. National Instruments is not liable for any damages resulting from such signal connections.

Page 35

Configuration and Installation Chapter 2

Figure 2-14 shows the pin assignments for the AT-MIO-16F-5 I/O connector.

AI GND

ACH0 ACH1

ACH2 ACH3 ACH4

ACH5 ACH6

ACH7

AI SENSE

DAC1 OUT

AO GND

ADIO0 ADIO1 ADIO2 ADIO3

DIG GND

+5 V

EXTSTROBE*

EXTGATE*

SOURCE 1

OUT1

GATE2

SOURCE5

OUT5

2 43 65

87 109 1211 1413 1615 1817

2019 2221 2423 2625 2827 3029 3231 3433 3635 3837 4039 4241 4443 4645

4847 5049

AI GND ACH8 ACH9

ACH10

ACH11

ACH12

ACH13

ACH14 ACH15 DAC0 OUT

EXTREF

DIG GND

BDIO0 BDIO1

BDIO2 BDIO3

+5 V SCANCLK EXTTRIG*

EXTCONV*

GATE1 EXTDACUPDATE*

OUT2

GATE5 FOUT

Figure 2-14. AT-MIO-16F-5 I/O Connector

Signal Connection Descriptions

Pins Signal Names Reference Descriptions

1, 2 AIGND N/A Analog Input Ground – These pins are the

reference point for single-ended measurements and the bias current return point for differential measurements.

(continues)

AT-MIO-16F-5 User Manual 2-18 © National Instruments Corporation

Page 36

Chapter 2 Configuration and Installation

Pins Signal Names Reference Descriptions (continued)

3 to 18 ACH <0..15> AI GND Analog Input Channels 0 through 15 – In

differential mode, the input is configured for 8 channels. In single-ended mode, the input is configured for 16 channels.

19 AI SENSE AI GND Analog Input Sense – This pin serves as the

reference node when the board is in NRSE configuration.

20 DAC0 OUT AO GND Analog Channel 0 Output – This pin

supplies the voltage output of analog output channel 0.

21 DAC1 OUT AO GND Analog Channel 1 Output – This pin

supplies the voltage output of analog output channel 1.

22 EXTREF AO GND External Reference – This is the external

reference input for the analog output circuitry.

23 AOGND N/A Analog Output Ground – The analog output

voltages are referenced to this node.

24,33 DIG GND N/A Digital Ground – This pin supplies the

reference for the digital signals at the I/O

connector as well as the +5 VDC supply. 25, 27, 29, 31 ADIO <0..3> DIG GND Digital I/O port A signals. 26, 28, 30, 32 BDIO <0..3> DIG GND Digital I/O port B signals. 34,35 +5 V DIG GND +5 VDC Source – This pin is fused for up to

1 A of +5 V supply. 36 SCAN CLK DIG GND Scan Clock – This pin pulses once for each

A/D conversion. The low-to-high edge

indicates when the input signal can be

removed from the input or switched to

another signal. 37 EXTSTROBE* DIG GND External Strobe – Writing to the

EXTSTROBE Register results in a 200-500

nsec low pulse on this pin.

(continues)

Page 37

Configuration and Installation Chapter 2

Pins Signal Names Reference Descriptions (continued)

38 EXTTRIG* DIG GND External Trigger – In posttrigger data

acquisition sequences, a high-to-low edge on

EXTTRIG* initiates the sequence. In

pretrigger applications, the first high-to-low

edge of EXTTRIG* initiates conversions

while the second high-to-low edge initiates

the sequence.

39 EXTGATE* DIG GND External Gate – When EXTGATE* is low,

A/D conversions are inhibited. When

EXTGATE* is high, A/D conversions are

enabled. 40 EXTCONV* DIG GND External Convert – A high-to-low edge on

EXTCONV* causes an A/D conversion to

occur. If EXTGATE* or EXTCONV* is

low, or INTGATE in Command Register 1

is high, conversions are inhibited. 41 SOURCE1 DIG GND SOURCE1 – This pin is from the Am9513A

Counter 1 signal. 42 GATE1 DIG GND GATE1 – This pin is from the Am9513A

Counter 1 signal. 43 OUT1 DIG GND OUTPUT1 – This pin is from the Am9513A

Counter 1 signal. 44 EXTDACUPDATE* DIG GND External DAC Update – If selected, a high-

to-low edge on EXTDACUPDATE* results

in the ouput DACS being updated with the

value written to them. 45 GATE2 DIG GND GATE2 – This pin is from the Am9513A

Counter 2 signal. 46 OUT2 DIG GND OUTPUT2 – This pin is from the Am9513A

Counter 2 signal. 47 SOURCE5 DIG GND SOURCE5 – This pin is from the Am9513A

Counter 5 signal. 48 GATE5 DIG GND GATE5 – This pin is from the Am9513A

Counter 5 signal.

(continues)

AT-MIO-16F-5 User Manual 2-20 © National Instruments Corporation

Page 38

Chapter 2 Configuration and Installation

Pins Signal Names Reference Descriptions (continued)

49 OUT5 DIG GND OUT5 – This pin is from the Am9513A

Counter 5 signal. 50 FOUT DIG GND Frequency Output – This pin is from the

Am9513A FOUT signal.

The signals on the connector can be classified as analog input signals, analog output signals, digital I/O signals, digital power connections, or timing I/O signals. Signal connection guidelines for each of these groups are given in the following section.

Analog Input Signal Connections

Pins 1 through 19 of the I/O connector are analog input signal pins. Pins 1 and 2 are AI GND signal pins. AI GND is an analog input common signal that is routed directly to the ground tie point on the AT-MIO-16F-5. These pins can be used for a general analog power ground tie point to the AT-MIO-16F-5 if necessary. Pin 19 is the AI SENSE pin. In NRSE mode, this pin is connected internally to the negative (-) input of the AT-MIO-16F-5 instrumentation amplifier. In the DIFF and RSE modes, this signal is left unconnected.

Pins 3 through 18 are ACH<15:0> signal pins. These pins are tied to the 16 analog input channels of the AT-MIO-16F-5. In single-ended mode, signals connected to ACH<15:0> are routed to the positive (+) input of the AT-MIO-16F-5 instrumentation amplifier. In differential mode, signals connected to ACH<7:0> are routed to the positive (+) input of the AT-MIO-16F-5 instrumentation amplifier, and signals connected to ACH<15:8> are routed to the negative (-) input of the AT-MIO-16F-5 instrumentation amplifier.

Warning: Exceeding the differential and common mode input ranges results in distorted input

signals. Exceeding the maximum input voltage rating can result in damage to the AT-MIO-16F-5 board and to the PC. National Instruments is not liable for any damages resulting from such signal connections.

Connection of analog input signals to the AT-MIO-16F-5 depends on the configuration of the AT-MIO-16F-5 analog input circuitry and the type of input signal source. With the different AT-MIO-16F-5 configurations, the AT-MIO-16F-5 instrumentation amplifier can be used in different ways. Figure 2-15 shows a diagram of the AT-MIO-16F-5 instrumentation amplifier.

Page 39

Configuration and Installation Chapter 2

Programmable

Gain

Gain = 0.5, 1, 2, 5, 10, 20, 50, 100

Figure 2-15. AT-MIO-16F-5 Instrumentation Amplifier

The AT-MIO-16F-5 instrumentation amplifier applies gain and common-mode voltage rejection, and presents high-input impedance to the analog input signals connected to the AT-MIO-16F-5 board. Signals are routed to the positive (+) and negative (-) inputs of the instrumentation amplifier through input multiplexers on the AT-MIO-16F-5. The instrumentation amplifier converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the AT-MIO-16F-5 ground. The AT-MIO-16F-5 ADC measures this output voltage when it performs A/D conversions.

Vm = [

]

GAINV

Measured Voltage

All signals must be referenced to ground, either at the source device or at the AT-MIO-16F-5. If you have a floating source, the AT-MIO-16F-5 should reference the signal to ground by using the RSE mode or the DIFF input configuration with bias resistors. If you have a grounded source, the AT-MIO-16F-5 should not reference the signal to ground. The board avoids this reference by using the DIFF or NRSE configurations.

Types of Signal Sources

When configuring the input mode of the AT-MIO-16F-5 and making signal connections, you must first determine whether the signal source is floating or ground-referenced. These two types of signals are described in the following sections.

Floating Signal Sources

A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolator outputs, and isolation amplifiers. The ground reference of a floating signal must be tied to the

AT-MIO-16F-5 User Manual 2-22 © National Instruments Corporation

Page 40

Chapter 2 Configuration and Installation

AT-MIO-16F-5 analog input ground in order to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies or appears to float. An instrument or device that provides an isolated output falls into the floating signal source category.

Ground-Referenced Signal Sources

A ground-referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the AT-MIO-16F-5 board, assuming that the PC AT is plugged into the same power system. Non-isolated outputs of instruments and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected. If grounded signal source is measured improperly, this difference may show up as an error in the measurement. The connection instructions for grounded signal sources below are designed to eliminate this ground potential difference from the measured signal.

Input Configurations

The AT-MIO-16F-5 can be configured for one of three input modes: NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements, and considerations for measuring both floating and ground-referenced signal sources. Table 2-9 summarizes the recommended input configuration for both types of signal sources.

Table 2-9. Recommended Input Configurations for Ground-Referenced

and Floating Signal Sources

Type of Signal Recommended Input Configuration

Ground-Referenced

(non-isolated outputs,

DIFF NRSE

plug-in instruments)

Floating

(batteries,

DIFF with bias resistors RSE

thermocouples,

isolated outputs)

Differential Connection Considerations (DIFF Configuration)

Differential connections are those in which each AT-MIO-16F-5 analog input signal has its own reference signal or signal return path. These connections are available when the AT-MIO-16F-5 is configured in the DIFF mode. Each input signal is tied to the positive (+) input of the instrumentation amplifier; and its reference signal, or return, is tied to the negative (-) input of the instrumentation amplifier.

When the AT-MIO-16F-5 is configured for differential input, each signal uses two multiplexer inputs–one for the signal and one for its reference signal. Therefore, with a differential

Page 41

Configuration and Installation Chapter 2

configuration, only eight analog input channels are available. Differential input connections should be used when any of the following conditions are present:

• Input signals are low-level (less than 1 V).

• Leads connecting the signals to the AT-MIO-16F-5 are greater than 15 ft.

• Any of the input signals require a separate ground reference point or return signal.

• The signal leads travel through noisy environments. Differential signal connections reduce picked-up noise and increase common mode signal and

noise rejection. With these connections, input signals can float within the common mode limits of the input instrumentation amplifier.

Differential Connections for Ground-Referenced Signal Sources

Figure 2-16 shows how to connect a ground-referenced signal source to an AT-MIO-16F-5 board configured for DIFF input. The AT-MIO-16F-5 analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Programming.

AT-MIO-16F-5 User Manual 2-24 © National Instruments Corporation

Page 42

Chapter 2 Configuration and Installation



ACH<0..7>

GroundReferenced Signal Source

Common Mode Noise, Ground Potential, Etc.

I/O Connector

5 7

Instrumentation

Amplifier

Gain

Measured Voltage

ACH<8..15>

Input Multiplexers

AI SENSE

1,2

AI GND

AT-MIO-16F-5 Board in DIFF Configuration

Figure 2-16. Differential Input Connections for Ground-Referenced Signals

With this type of connection, the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT-MIO-16F-5 ground (shown as Vcm in Figure 2-16).

Differential Connections for Non-Referenced or Floating Signal Sources

Figure 2-17 shows how to connect a floating signal source to an AT-MIO-16F-5 board configured for DIFF input. The AT-MIO-16F-5 analog input circuitry must be configured for DIFF input to make these types of connections. Configuration instructions are included in Chapter 4, Programming.

Page 43

Configuration and Installation Chapter 2

Floating Signal Source

Bias Current Return Paths

100 kΩ

3 5

4 6

1,2

ACH<0..7>

ACH<8..15>

Input Multiplexers

AI SENSE

AI GND

Instrumentation

Amplifier

Gain

Measured Voltage

I/O Connector

AT-MIO-16F-5 Board in DIFF Configuration

Figure 2-17. Differential Input Connections for Non-Referenced Signals

The 100 kΩ resistors shown in Figure 2-17 create a return path to ground for the bias currents of the instrumentation amplifier. If a return path is not supplied, the instrumentation amplifier bias currents charge up stray capacitances, resulting in uncontrollable drift and possible saturation in the amplifier. Typically, values from 100 kΩ to 1 MΩ are used.

A resistor from each input to ground, as shown in Figure 2-17, supplies bias current return paths for an AC-coupled input signal. This solution, although necessary for AC-coupled signals, lowers the input impedance of the analog input channel. In addition, the input offset current of the instrumentation amplifier contributes a DC offset voltage at the input. The amplifier has a maximum input offset current of ±100 pA and a negligible offset current drift. Multiplied by the 100 kΩ resistor, this current contributes a maximum offset voltage of 10 µV, which is insignificant in most applications. However, the use of larger-valued bias resistors could result in significant offset error.

AT-MIO-16F-5 User Manual 2-26 © National Instruments Corporation

Page 44

Chapter 2 Configuration and Installation

If the input signal is DC-coupled, then only the resistor connecting the negative (-) signal input to ground is needed. This connection does not lower the input impedance of the analog input channel.

Single-Ended Connection Considerations

Single-ended connections are those in which all AT-MIO-16F-5 analog input signals are referenced to one common ground. The input signals are tied to the positive (+) input of the instrumentation amplifier, and their common ground point is tied to the negative (-) input of the instrumentation amplifier.

When the AT-MIO-16F-5 is configured for single-ended input, 16 analog input channels are available. Single-ended input connections can be used when all input signals meet the following criteria:

• Input signals are high-level (greater than 1 V).

• Leads connecting the signals to the AT-MIO-16F-5 are less than 15 ft.

• All input signals share a common reference signal (at the source). If any of the preceding criteria are not met, using differential input connections is recommended

for greater signal integrity. The AT-MIO-16F-5 can be software-configured for two different types of single-ended

connections: RSE configuration and NRSE configuration. The RSE configuration is used for floating signal sources; in this case, the AT-MIO-16F-5 provides the reference ground point for the external signal. The NRSE configuration is used for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the AT-MIO-16F-5 should not supply one.

Single-Ended Connections for Floating Signal Sources (RSE Configuration)

Figure 2-18 shows how to connect a floating signal source to an AT-MIO-16F-5 board configured for single-ended input. The AT-MIO-16F-5 analog input circuitry must be configured for RSE input to make these types of connections. Configuration instructions are included in Chapter 4, Programming.

Page 45

Configuration and Installation Chapter 2

ACH<0..15>

Input Multiplexer

AI SENSE

AI GND

Instrumentation

Amplifier

Gain

- V

Measured Voltage

Non-

Referenced

or Floating

Signal

Source

3 5

1,2

AT-MIO-16F-5 Board in RSE Configuration

I/O Connector

Figure 2-18. Single-Ended Input Connections for Non-Referenced or Floating Signals

Single-Ended Connections for Grounded Signal Sources (NRSE Configuration)

If a grounded signal source is to be measured with a single-ended configuration, then the AT-MIO-16F-5 must be configured in the NRSE input configuration. The signal is connected to the positive (+) input of the AT-MIO-16F-5 instrumentation amplifier and the signal local ground reference is connected to the negative (-) input of the AT-MIO-16F-5 instrumentation amplifier. The ground pont of the signal should therefore be connected to the AISENSE pin. Any potential difference between the AT-MIO-16F-5 ground and the signal ground appears as a common mode signal at both the positive (+) and negative (-) inputs of the instrumentation amplifier and this difference is rejected by the amplifier. On the other hand, if the input circuitry of the AT-MIO-16F-5 is referenced to ground, such as in the RSE configuration, this difference in ground potentials appears as an error in the measured voltage.

Figure 2-19 shows how to connect a grounded signal source to an AT-MIO-16F-5 board configured for single-ended input. The AT-MIO-16F-5 analog input circuitry must be configured for NRSE configuration to make these types of signals. Configuration instructions are included in Chapter 4, Programming.

AT-MIO-16F-5 User Manual 2-28 © National Instruments Corporation

Page 46

Chapter 2 Configuration and Installation

ACH<0..15>

Input Multiplexer

AI SENSE

AI GND

AT-MIO-16F-5 Board in NRSE Configuration

Ground-

Referenced

Signal

Source

Common

Mode Noise

I/O Connector

3 5

1,2

Figure 2-19. Single-Ended Input Connections for Ground-Referenced Signals

Common Mode Signal Rejection Considerations

Instrumentation

- V

Amplifier

Measured Voltage

Figures 2-16 and 2-19, located earlier in this chapter, show connections for signal sources that are already referenced to some ground point with respect to the AT-MIO-16F-5. In these cases, the instrumentation amplifier can reject any voltage caused by ground potential differences between the signal source and the AT-MIO-16F-5. In addition, with differential input connections, the instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the AT-MIO-16F-5.

The common mode input range of the AT-MIO-16F-5 instrumentation amplifier is defined as the magnitude of the greatest common mode signal that can be rejected. The instrumentation

amplifier can reject common mode signals as long as V

and V

are both in the range ±12 V.

Thus the common mode input range for the AT-MIO-16F-5 depends on the size of the differential input signal (V

diff

= V

- V

). The exact formula for the permissible common

mode input range is as follows:

cm-max

= ± (12 V - Vdiff)

Page 47

Configuration and Installation Chapter 2

Thus, with a differential voltage of 10 V, the maximum possible common mode voltage would be +7 V. The common mode voltage is measured with respect to the AT-MIO-16F-5 ground and can be calculated by the following formula:

cm-actual

where V

= (V

is the signal at the positive (+) input of the instrumentation amplifier and V

signal at the negative (-) input of the instrumentation amplifier. Both V

+ V

-in

)/2

and V

is the

are

measured with respect to AIGND.

Analog Output Signal Connections

Pins 20 through 23 of the I/O connector are analog output signal pins. Pins 20 and 21 are the DAC0 OUT and DAC1 OUT signal pins. DAC0 OUT is the voltage

output signal for analog output Channel 0. DAC1 OUT is the voltage output signal for analog output Channel 1.

Pin 22, EXTREF, is the external reference input for both analog output channels. Each analog output channel must be configured individually for external reference selection in order for the signal applied at the external reference input to be used by that channel. Analog output configuration instructions are included under the Analog Output Configuration section earlier in this chapter.

The following ranges and ratings apply to the EXTREF input:

Useful input voltage range: ±10 V peak with respect to AO GND Absolute maximum ratings: ±25 V peak with respect to AO GND

Pin 23, AO GND, is the ground reference point for both analog output channels and for the external reference signal.

Figure 2-20 shows how to make analog output connections and the external reference input connection to the AT-MIO-16F-5 board.

AT-MIO-16F-5 User Manual 2-30 © National Instruments Corporation

Page 48

Chapter 2 Configuration and Installation

EXTREF

DAC0 OUT

External Reference Signal (Optional)

ref

VOUT 0

Channel 0

Load

AO GND

Load

VOUT 1

DAC1 OUT

Channel 1

Analog Output Channels

AT-MIO-16F-5 Board

Figure 2-20. Analog Output Connections

The external reference signal can be either a DC or an AC signal. This reference signal is multiplied by the DAC code to generate the output voltage.

Digital I/O Signal Connections

Pins 24 through 32 of the I/O connector are digital I/O signal pins. Pins 25, 27, 29, and 31 are connected to the digital lines ADIO<3..0> for digital I/O port A. Pins

26, 28, 30, and 32 are connected to the digital lines BDIO<3..0> for digital I/O port B. Pin 24, DIG GND, is the digital ground pin for both digital I/O ports. Ports A and B can be programmed individually to be inputs or outputs.

The following specifications and ratings apply to the digital I/O lines.

Absolute maximum voltage

Input rating 5.5 V with respect to DIG GND

Page 49

Configuration and Installation Chapter 2

Digital input specifications (referenced to DIG GND):

VIH input logic high voltage 2 V minimum V

input logic low voltage 0.8 V maximum

input current load,

logic high input voltage 40 µA maximum

input current load,

logic low input voltage -120 µA maximum

Digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

output logic low voltage 0.5 V maximum

output source current,

logic high 2.6 mA maximum

output sink current,

logic low 24 mA maximum

With these specifications, each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads.

Figure 2-21 depicts signal connections for three typical digital I/O applications.

AT-MIO-16F-5 User Manual 2-32 © National Instruments Corporation

Page 50

Chapter 2 Configuration and Installation

+5 V

LED

31 29

Port A

27 25

ADIO<3..0>

+5 V

Switch

TTL Signal

30 28 26

Port B BDIO<3..0>

DIG GND

I/O Connector

AT-MIO-16F-5 Board

Figure 2-21. Digital I/O Connections

In Figure 2-21, port A is configured for digital output, and port B is configured for digital input. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2-21. Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2-21.

Power Connections

Pins 34 and 35 of the I/O connector provide +5 V from the PC power supply. These pins are referenced to DIG GND and can be used to power external digital circuitry.

Power Rating 1.0 A at +5 V ± 10%, fused

Warning: Under no circumstances should these +5 V power pins be connected directly to

analog or digital ground or to any other voltage source on the AT-MIO-16F-5 or any other device. Doing so can damage the AT-MIO-16F-5 and the PC. National Instruments is not liable for damage resulting from such a connection.

Page 51

Configuration and Installation Chapter 2

Timing Connections

Pins 36 through 50 of the I/O connector are connections for timing I/O signals. Pins 36 through 40 and pin 44 carry signals used for data acquisition timing and analog output triggering. These signals are explained in Data Acquisition Timing Connections later in this chapter. Pins 41 through 50 carry general-purpose timing signals and analog output provided by the onboard Am9513A Counter/Timer. These signals are explained in General-Purpose Timing Signal Connections later in this chapter.

Data Acquisition and Analog Output Timing Connections

The data acquisition and analog output timing signals are SCANCLK, EXTSTROBE*, EXTTRIG*, EXTGATE*, EXTCONV*, and EXTDACUPDATE*.

SCANCLK Signal SCANCLK is an output signal that generates a low-to-high edge whenever an A/D conversion

begins. SCANCLK pulses only when scanning is enabled on the AT-MIO-16F-5. SCANCLK is normally low and pulses high for approximately 4 µsecs after the A/D conversion begins. The low-to-high edge can be used to clock external analog input multiplexers. The SCANCLK signal is driven by one CMOS TTL gate.

EXTSTROBE Signal A low pulse is generated on the EXTSTROBE* pin when the External Strobe Register is loaded

(see External Strobe Register in Chapter 4, Programming). Figure 2-22 shows the timing for the EXTSTROBE* signal.

w 100 - 500 nsec

Figure 2-22. EXTSTROBE* Signal Timing

The pulse is typically between 200 nsec and 500 nsec in width. The EXTSTROBE* signal can be used by an external device to latch signals or trigger events. The EXTSTROBE* signal is an HCT signal.

AT-MIO-16F-5 User Manual 2-34 © National Instruments Corporation

Page 52

Chapter 2 Configuration and Installation

EXTCONV Signal A/D conversions can be externally triggered with the EXTCONV* pin. Applying an active low

pulse to the EXTCONV* signal initiates an A/D conversion. Figure 2-23 shows the timing requirements for the EXTCONV* signal.

w 50 nsec Minimum

ADC Switches to Hold Mode within 100 nsec from This Point

Figure 2-23. EXTCONV* Signal Timing

The minimum allowed pulse width is 50 nsec. The ADC switches to hold mode within 100 nsec of the high-to-low edge. This hold mode delay time is a function of temperature and does not vary from conversion to consecutive conversion. There is no maximum pulse width limitation. EXTCONV* should be high for at least one conversion period before going low. The EXTCONV* signal is one HCT load and is pulled up to +5 V through a 10 kΩ resistor.

Note: EXTCONV* is also driven by the output of Counter 3 of the Am9513A Counter/Timer.

This counter is also referred to as the sample-interval counter. The output of Counter 3 must be disabled to a high-impedance state if A/D conversions are to be controlled by pulses applied to the EXTCONV* pin. If Counter 3 is used to control A/D conversions, its output signal can be monitored at the EXTCONV* pin.

Page 53

Configuration and Installation Chapter 2

EXTTRIG* Signal Any data acquisition sequence can be initiated by an external trigger applied to the EXTTRIG*

pin. Applying a falling edge to the EXTTRIG* pin starts the sample and sample-interval counters, thereby initiating a data acquisition sequence. Figure 2-24 shows the timing requirements for the EXTTRIG* signal.

w 50 nsec Minimum

First A/D Conversion Starts within 1 Sample Interval from This Point

Figure 2-24. EXTTRIG* Signal Timing

The EXTTRIG* pin is also used during AT-MIO-16F-5 pretriggered data acquisition operations. In pretriggered mode, data is acquired but no sample counting occurs until a falling edge is applied to the EXTTRIG* pin. A second falling edge causes the sample counter to then start counting conversions. The acquisition then completes when the sample counter decrements to zero. This mode acquires data both before and after a hardware trigger is received.

The minimum pulse width allowed is 50 nsec. The first A/D conversion starts within one sample interval from the high-to-low edge. The sample interval is controlled by Counter 3 or EXTCONV*.

There is no maximum pulse width limitation; however, EXTTRIG* should be high for at least 50 nsec before going low. The EXTTRIG* signal is one HCT load and is pulled up to +5 V through a 10 kΩ resistor.

Note: The EXTTRIG* signal is logically ANDed with the internal DAQSTART signal. If a

data acquisition sequence is to be initated with an internal trigger, EXTTRIG* must be high at both the I/O connector and the RTSI switch. If EXTTRIG* is low, the sequence will not be triggered.

EXTGATE Signal EXTGATE* is an input signal used for hardware gating. EXTGATE* controls A/D conversion

pulses. If EXTGATE* is low, no A/D conversion pulses occur. If EXTGATE* is high, conversions take place if programmed and otherwise enabled.

AT-MIO-16F-5 User Manual 2-36 © National Instruments Corporation

Page 54

Chapter 2 Configuration and Installation

EXTDACUPDATE* Signal The analog output DACs on the AT-MIO-16F-5 can be updated using either internal or external

signals. The DACs can be updated externally by using the EXTDACUPDATE* signal from the I/O connector. This signal updates the DACs when the WGEN bit in Command Register 2 is set and A4RCV is disabled.

The analog output DACs are updated by the high-to-low edge of the applied pulse. Figure 2-25 shows the timing requirements for the EXTDACUPDATE* signal.

w 50 nsec Minimum

DACs Update 100 nsec from This Point

Figure 2-25. EXTDACUPDATE* Signal Timing

The minimum pulse width allowed is 50 nsec. The DACs are updated within 100 nsec of the high-to-low edge. There is no maximum pulse width limitation. EXTDACUPDATE* should be high for at least 50 nsec before going low. The EXTDACUPDATE* signal is one HCT load and is pulled up to +5V through a 10 kΩ resistor.

General-Purpose Timing Signal Connections

The general-purpose timing signals include the GATE and OUT signals for the Am9513A Counters 1, 2, and 5, SOURCE signals for Counters 1 and 5, and the FOUT signal generated by the Am9513A. Counters 1, 2, and 5 of the Am9513A Counter/Timer can be used for general-purpose applications, such as pulse and square wave generation, event counting, pulse-width, time-lapse, and frequency measurements. For these applications, SOURCE and GATE signals can be directly applied to the counters from the I/O connector. The counters are programmed for various operations.

The Am9513A Counter/Timer is described briefly in Chapter 3, Theory of Operation. For detailed programming information, consult the Am9513A data sheet in Appendix C. For detailed applications information, consult the technical manual The Am9513A/Am9513 System Timing Controller published by Advanced Micro Devices, Inc.

Pulses and square waves can be produced by programming Counter 1, 2, or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count.

Page 55

Configuration and Installation Chapter 2

For event counting, one of the counters is programmed to count rising or falling edges applied to any of the Am9513A SOURCE inputs. The counter value can then be read to determine the number of edges that have occurred. Counter operation can be gated on and off during event counting.

Figure 2-26 shows connections for a typical event-counting operation where a switch is used to gate the counter on and off.

+5 V

4.7 kΩ

SOURCE

OUT

GATE

Switch

Signal

Counter

Source

DIG GND

I/O Connector

AT-MIO-16F-5 Board

Figure 2-26. Event-Counting Application with External Switch Gating

To perform pulse-width measurement, a counter is programmed to be level-gated. The pulse to be measured is applied to the counter GATE input. The counter is programmed to count while the signal at the GATE input is either high or low. If the counter is programmed to count an internal timebase, then the pulse width is equal to the counter value multiplied by the timebase period.

For time-lapse measurement, a counter is programmed to be edge-gated. An edge is applied to the counter GATE input to start the counter. The counter can be programmed to start counting after receiving either a high-to-low edge or a low-to-high edge. If the counter is programmed to count an internal timebase, then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period.

To measure frequency, a counter is programmed to be level-gated and the rising or falling edges are counted in a signal applied to a SOURCE input. The gate signal applied to the counter GATE input is of some known duration. In this case, the counter is programmed to count either

AT-MIO-16F-5 User Manual 2-38 © National Instruments Corporation

Page 56

Chapter 2 Configuration and Installation

rising or falling edges at the SOURCE input while the gate is applied. The frequency of the input signal is then the count value divided by the known gate period. Figure 2-27 shows the connections for a frequency measurement application. A second counter can also be used to generate the gate signal in this application.

+5 V

4.7 kΩ

SOURCE

OUT

GATE

Signal

Source

Gate

Source

Counter

DIG GND

I/O Connector

AT-MIO-16F-5 Board

Figure 2-27. Frequency Measurement Application

Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter. The counters can then be treated as one 32-bit or 48-bit counter for most counting applications.

Page 57

Configuration and Installation Chapter 2

The signals for Counters 1, 2, and 5, and the FOUT output signal are tied directly from the Am9513A input and output pins to the I/O connector. In addition, the GATE, SOURCE, and OUT1 pins are pulled up to +5 V through a 4.7 kΩ resistor. The input and output ratings and timing specifications for the Am9513A signals are given as follows:

Absolute maximum voltage

input rating -0.5 V to +7.0 V with respect to DIG GND

Am9513A digital input specifications (referenced to DIG GND):

input logic high voltage 2.2 V minimum

VIL input logic low voltage 0.8 V maximum Input load current ±10 µA maximum

Am9513A digital output specifications (referenced to DIG GND):

output logic high voltage 2.4 V minimum

VOL output logic low voltage 0.4 V maximum IOH output source current,

at V

200 µA maximum

IOL output sink current,

at V

3.2 mA maximum

Output current, high-impedance

state ±25 µA maximum

AT-MIO-16F-5 User Manual 2-40 © National Instruments Corporation

Page 58

Chapter 2 Configuration and Installation

Figure 2-28 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A.

SOURCE

GATE

OUT

I L

I H

I L

I H

t t

t t t t

gsu

out

145 nsec Minimum

sc sp

gsu gh gw out

70 nsec Minimum

100 nsec Minimum

10 nsec Minimum 145 nsec Minimum 300 nsec Maximum

ttt

sp sp

Figure 2-28. General-Purpose Timing Signals

The GATE and OUT signal transitions in Figure 2-28 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, with the source signal inverted and referenced to the falling edge of the source signal, applies to the case in which the counter is programmed to count falling edges.

The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter/timers and by the Am9513A frequency division output FOUT. The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of the Am9513A. The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins.

In addition to the signals applied to the SOURCE and GATE inputs, the Am9513A generates five internal timebase clocks from the clock signal supplied by the AT-MIO-16F-5. This clock signal is selected by the W5 jumper and then divided by 10. The factory default value is 1 MHz into the Am9513A (10-MHz clock signal on the AT-MIO-16F-5). The five internal timebase clocks can be used as counting sources, and these clocks have a maximum skew of 75 nsec

between them. The SOURCE signal shown in Figure 2-28 represents any of the signals applied at the SOURCE inputs, GATE inputs, or internal timebase clocks. See the Am9513A data sheet in Appendix C for further details.

Page 59

Configuration and Installation Chapter 2

Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals. Figure 2-28 shows the GATE signal referenced to the rising edge of a source signal. The gate must be valid (either high or low) at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge (as shown by t at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge. The gate high or low period must be at least 145 nsec in duration. If an internal timebase clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.

Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals. Figure 2-28 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 300 nsec after the source signal rising or falling edge.

and tgh in Figure 2-28). Similarly, the gate signal must be held for

gsu

Field Wiring Considerations

Accuracy of measurements made with the AT-MIO-16F-5 can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT-MIO-16F-5 board. The following recommendations apply mainly to analog input signal routing to the AT-MIO-16F-5 board, though they are applicable for signal routing in general.

Noise pickup can be minimized and measurement accuracy maximized by doing the following:

• Use individually shielded, twisted-pair wires to connect analog input signals to the AT-MIO-16F-5. With this type of wire, the signals attached to the CH+ and CH- inputs are twisted together and then covered with a shield. This shield is then connected only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.

• Use differential analog input connections to reject common mode noise.

The following recommendations apply for all signal connections to the AT-MIO-16F-5:

• Separate AT-MIO-16F-5 signal lines from high-current or high-voltage lines. These lines are capable of inducing currents in or voltages on the AT-MIO-16F-5 signal lines if they run in parallel paths at a close distance. Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel, or by running the lines at right angles to each other.

AT-MIO-16F-5 User Manual 2-42 © National Instruments Corporation

Page 60

Chapter 2 Configuration and Installation

• Do not run AT-MIO-16F-5 signal lines through conduits that also contain power lines.

• Protect AT-MIO-16F-5 signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running the AT-MIO-16F-5 signal lines through special metal conduits.

Cabling Considerations

National Instruments has a cable termination accessory, the CB-50, for use with the AT-MIO-16F-5 board. This kit includes a terminated 50-conductor flat ribbon cable and a connector block. Signal I/O leads can be attached to screw terminals on the connector block and thereby connected to the AT-MIO-16F-5 I/O connector.

The CB-50 can be used for prototyping an application or in situations where AT-MIO-16F-5 interconnections are frequently changed. However, once a final field wiring scheme has been developed, you may want to develop your own cable. This section contains information and guidelines for design of such a cable.

In making your own cabling, you may decide to shield your cables. The following guidelines can help:

• For the analog input signals, shielded twisted-pair wires for each analog input pair yield the best results, assuming that differential inputs are used. Tie the shield for each signal pair to the ground reference at the source.

• The analog lines, pins 1 through 23, should be routed separately from the digital lines, pins 24 through 50.

• When using a cable shield, use separate shields for the analog and digital halves of the cable. Failure to do so results in noise from switching digital signals coupling into the analog signals.

Page 61

Chapter 3 Theory of Operation

This chapter contains a functional overview of the AT-MIO-16F-5 board and explains the operation of each functional unit making up the AT-MIO-16F-5.

Functional Overview

The block diagram in Figure 3-1 is a functional overview of the AT-MIO-16F-5 board.

Analog

Muxes

Timing

DAC0

I/O Connector

DAC1

Digital

Output

Digital

Input

Voltage

Ref

Ground

Ref

Mux Mode

Selection

Switches

DAC

Timing/

Control

Calibration

DACs

Dither

Generator

Calibration

DACs

+ Pro-

grammable Gain

Amplifier

5-Channel

Counter/Timer

Data/Control

RTSI Bus

Interface

RTSI Bus

12-Bit

Sampling

A/D

Conversion

Data Acquisition

Conversion Control

Timer Interrupt

ADC FIFO

and

Sign

Exten sion

ADC

Interrupt

PC/AT

Bus

Interface

Circuitry

DMA

Interface

Interrupt

Interface

PC/AT I/O Channel

Figure 3-1. AT-MIO-16F-5 Block Diagram

Page 62

Theory of Operation Chapter 3

The following are the major components making up the AT-MIO-16F-5 board:

• PC I/O channel interface circuitry

• Analog input and data acquisition circuitry

• Analog output circuitry

• Digital I/O circuitry

• Timing I/O circuitry

• RTSI bus interface circuitry

The internal data and control buses interconnect the components. The theory of operation of each of these components is explained in the remainder of this chapter.

PC I/O Channel Interface Circuitry

The AT-MIO-16F-5 board is a full-size, 16-bit PC I/O channel adapter. The PC I/O channel consists of a 24-bit address bus, a 16-bit data bus, a DMA arbitration bus, interrupt lines, and several control and support signals. The components making up the AT-MIO-16F-5 PC I/O channel interface circuitry are shown in Figure 3-2.

AT-MIO-16F-5 User Manual 3-2 © National Instruments Corporation

Page 63

Chapter 3 Theory of Operation

Address

Bus

I/O Channel

Control Lines

Data Bus

PC I/O Channel

DMA Request

DMA

Acknowledge

IRQ

Address

Latches

PC I/O

Channel

Timing

Interface

Data

Buffers

DMA

Control

Circuitry

Interrupt

Control

Circuitry

Address

Decoder

Read and Write Signals

Internal Data Bus

AT-MIO-16F-5 DMA Request

AT-MIO-16F-5 DMA Acknowledge and Terminal Count

AT-MIO-16F-5 Interrupt Request

Figure 3-2. PC I/O Channel Interface Circuitry Block Diagram

The PC I/O channel interface circuitry consists of address latches, address decoder circuitry, data buffers, PC I/O channel interface timing signals, interrupt circuitry, and DMA arbitration circuitry. The PC I/O channel interface circuitry generates the signals necessary to control and monitor the operation of the AT-MIO-16F-5 multiple function circuitry.

The PC I/O channel has 24 address lines; the AT-MIO-16F-5 uses 10 of these lines to decode the board address. Therefore, the board address range is 000 to 3FF hex. SA5 through SA9 are used to generate the board enable signal. SA0 through SA4 are used to select onboard registers. These address lines are latched by the address latches at the beginning of an I/O transfer. The latched address lines send the same address to the address-decoding circuitry during the entire I/O transfer cycle. The address-decoding circuitry generates the register select signals that identify which AT-MIO-16F-5 register is being accessed. The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write.

Page 64

Theory of Operation Chapter 3

The PC I/O channel interface timing signals are used to generate read and write signals and to define the transfer cycle. A transfer cycle can be either an 8-bit or a 16-bit data I/O operation. The AT-MIO-16F-5 returns signals to the PC I/O channel to indicate when the board has been accessed, when the board is ready for another transfer, and the data bit size of the current I/O transfer.

The interrupt control circuitry routes any enabled interrupt requests to the selected interrupt request line. The AT-MIO-16F-5 board can share the interrupt line with other devices because the interrupt requests are tri-state output signals. Eleven interrupt request lines are available for use by the AT-MIO-16F-5: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. Five different interrupts can be generated by the AT-MIO-16F-5 in the following cases:

• When a single A/D conversion can be read from the A/D FIFO memory.

• When the A/D FIFO is half-full.

• When a data acquisition operation completes, including when either an OVERFLOW or an OVERRUN error occurs.

• When a DMA terminal count pulse is received.

• When a falling edge signal is detected on the DAC update signal.

Each one of these interrupts is individually enabled and cleared. See Chapter 4, Programming, for more information about programming with interrupts.

The DMA control circuitry generates DMA requests whenever an A/D measurement is available from the FIFO and when the DACs are updated using one of the methods described previously, if the DMA transfer is enabled. The DMA circuitry supports full PC I/O channel 16-bit DMA transfers. DMA Channels 5, 6, and 7 of the PC I/O channel are available for such transfers. With the DMA circuitry, either single-channel transfer mode or dual-channel transfer mode can be selected for DMA transfer.

Analog Input and Data Acquisition Circuitry

The AT-MIO-16F-5 handles 16 channels of analog input with software-programmable gain and 12-bit A/D conversion. In addition, the AT-MIO-16F-5 contains data acquisition circuitry for automatic timing of multiple A/D conversions and includes advanced options such as external triggering, gating, and clocking. Figure 3-3 shows a block diagram of the analog input and data acquisition circuitry.

AT-MIO-16F-5 User Manual 3-4 © National Instruments Corporation

Page 65

Chapter 3 Theory of Operation

EEPROM

Calibration

Constants

Gain

Dither

Generator

Data

Sign

Exten-

sion

Dither

A/D

ADC

Bipolar

Unipolar/

A/D

FIFO

Data

Selection

A/D RD

Convert

Channel

PC I/O

CONV AVAIL

Data

MUXGAIN WR

Multi-

plexer/

Channel

Gain

Memory

LASTCH

Signals

Counter/Timer

MUX CLK

Data

Timing

Acquisition

DAC

Calibration

Reference

SE/DIFF

In Off

AIS/AIG

Calibration

Out Off

MUX0OUT

Gain

grammable

Pro-

Selection

Mux Mode

MUX0EN

MUX

Amplifier

–

Switches

GAIN1

GAIN0

GAIN2

MUX1EN

MUX1OUT

MUX

MA3

MA2

MA1

I/O Connector

MA0

SCAN CLK

External Trigger

External Convert

ACH0

AISENSE

ACH9

ACH8

ACH11

ACH10

ACH13

ACH12

ACH14

EXT TRIG

SCAN CLK

EXTCONV

ACH7

ACH6

ACH5

ACH4

ACH3

ACH2

ACH1

Figure 3-3. Analog Input and Data Acquisition Circuitry Block Diagram

Page 66

Theory of Operation Chapter 3

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, multiplexer mode selection switches, a software-programmable gain instrumentation amplifier, calibration hardware, a 12-bit sampling ADC, and a 16-bit, 256-word deep FIFO with a 16-bit sign extension option.

The input multiplexer consists of two CMOS analog input multiplexers and has 16 analog input channels. Multiplexer MUX0 is connected to analog input Channel 0 through Channel 7. Multiplexer MUX1 is connected to analog input Channel 8 through Channel 15. Analog input overvoltage protection is ±25 V powered on and ±15 V powered off.

The multiplexer mode selection switches are controlled through Command Register 1 and configure the analog input channels as 16 single-ended inputs or 8 differential inputs. When single-ended mode is selected, the outputs of the two multiplexers are tied together and routed to the positive (+) input of the instrumentation amplifier. The negative (-) input of the instrumentation amplifier is tied to the AT-MIO-16F-5 ground for measuring non-referenced single-ended input signals or to the analog return of the input signals via the AI SENSE input on the I/O connector for measuring ground-referenced single-ended input signals. When differential mode is selected, the output of MUX0 is routed to the positive (+) input of the instrumentation amplifier, and the output of MUX1 is routed to the negative (-) input of the instrumentation amplifier. See Table 4-2 in Chapter 4, Programming, for more information on input configuration.

The instrumentation amplifier fulfills two purposes on the AT-MIO-16F-5 board. It converts a differential input signal into a single-ended signal with respect to the AT-MIO-16F-5 ground for input common-mode signal rejection as described in Appendix A, Specifications. With this conversion the input analog signal can be extracted from any common mode voltage or noise before being sampled and converted. The instrumentation amplifier also applies gain to the input signal, amplifying an input analog signal before sampling and conversion to increase measurement resolution and accuracy. Software selectable gains of 0.5, 1, 2, 5, 10, 20, 50 and 100 are available through the AT-MIO-16F-5 instrumentation amplifier.

The dither circuitry, when enabled, adds approximately 0.5 LSB rms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of the AT-MIO-16F-5 to more than 12 bits, as in calibration. In such applications, which are often lower frequency in nature, noise modulation is decreased and differential linearity is improved by the addition of the dither. For high-speed 12-bit applications not involving averaging, dither should be disabled because it only adds noise. Enabling and disabling of the dither circuitry is accomplished through software (see Chapter 4, Programming).

When taking DC measurements, such as when calibrating the board, enable dither (see Chapter 4, Programming) and average about 1,000 points to take a single reading. This process removes the effects of 12-bit quantization and reduces measurement noise, resulting in improved resolution. Dither, or additive white noise, has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of input. For more information on the effects of dither, see "Dither in Digital Audio" by John Vanderkooy and Stanley P. Lipshitz, Journal of the Audio Engineering Society, Vol. 35, No. 12, Dec. 1987.

Measurement reliability is assured through the use of the onboard calibration circuitry of the AT-MIO-16F-5. This circuitry uses an internal, stable, 5 V reference that is measured at the factory against a higher accuracy reference; then its value is stored in the EEPROM on the AT-MIO-16F-5. A storage map of the EEPROM can be found in Chapter 5, Calibration

AT-MIO-16F-5 User Manual 3-6 © National Instruments Corporation

Page 67

Chapter 3 Theory of Operation

Procedures. With this stored reference value, the AT-MIO-16F-5 board can be recalibrated at

any time under any number of different environmental conditions in order to remove errors caused by time and temperature drift. The EEPROM stores calibration constants that can be read and then written to calibration DACs that adjust input offset, output offset, and gain errors associated with the analog input section. When the AT-MIO-16F-5 leaves the factory, locations 52 through 63 of the EEPROM are protected and cannot be overwritten. Locations 0 through 51 are unprotected and can be used to store alternate calibration constants for the differing conditions under which the board is used.

Selection of the analog input channel and gain settings is controlled by the mux-channel-gain memory. With the mux-channel-gain memory, four channel-address bits are available to the input multiplexers and multiplexer mode selection circuitry that selects the analog input channels, and three gain control bits are available to the instrumentation amplifier. Each set of four-channel bits has its own corresponding three gain-selection bits. Operation of the mux-channel-gain memory is explained in more detail in Data Acquisition Timing Circuitry later in this chapter.

The ADC is a 12-bit, sampling, successive approximation ADC. With the 12-bit resolution, the converter can resolve its input range into 4,096 different steps. This resolution also generates a 12-bit digital word that represents the value of the input voltage level with respect to the converter input range. The ADC has two input ranges that are software selectable on the AT-MIO-16F-5 board: -5 V to +5 V, or 0 V to +10 V. The ADC on the AT-MIO-16F-5 is guaranteed to convert at a rate of at least 200 ksamples/sec.

When an A/D conversion is complete, the ADC clocks the result into the FIFO. The FIFO is 16 bits wide and 256 words deep. This FIFO serves as a buffer to the ADC and is beneficial for two reasons. Any time an A/D conversion is complete, the value is saved in the FIFO for later reading, and the ADC is free to start a new conversion. Secondly, the FIFO can collect up to 256 A/D conversion values before any information is lost; thus software or DMA has extra time (256 times the sample interval) to catch up with the hardware. If more than 256 values are stored in the FIFO without the FIFO being read from, an error condition called FIFO overflow occurs and A/D conversion information is lost.

The FIFO generates a signal that indicates when it contains a single A/D conversion value. The FIFO also generates a signal that indicates when it is half-filled with A/D conversion data. These signals can be used to generate a DMA or interrupt request signal. Sign-extension circuitry at the FIFO output adds four most significant bits (bits 15 through 12) to the 12-bit ADC output (bits 11 through 0) to produce a 16-bit result. This 16-bit word is then shifted into the A/D FIFO. The sign-extension circuitry is software-programmable to generate either straight binary numbers or two's complement numbers. In straight binary mode, bits 15 through 12 are always 0 and result in a range of 0 to 4095. In two's complement mode, the most significant bit of the 12-bit ADC result, bit 11, is extended to bits 15 through 12, resulting in a range of -2048 to +2047.

Page 68

Theory of Operation Chapter 3

Data Acquisition Timing Circuitry

A data acquisition operation refers to the process of taking a sequence of A/D conversions with the sample interval (the time between successive A/D conversions) carefully timed. The data acquisition timing circuitry consists of various clocks and timing signals. Three types of data acquisition are available with the AT-MIO-16F-5 board: single-channel data acquisition, multiple-channel data acquisition with continuous scanning, and multiple-channel data acquisition with interval scanning. All data acquisition operations work with pretrigger and posttrigger modes. Pretriggering acquires data after a software or hardware trigger is applied. When a second trigger is applied, the normal data acquisition sequence is initiated. Posttriggering is a normal data acquisition sequence that can be initiated by a software or hardware trigger.

Scanned data acquisition uses the mux-channel-gain memory to automatically switch between analog input channels and gains during data acquisition. Continuous scanning cycles through the mux-channel-gain memory without any delays between cycles. Interval scanning assigns a time between the starts of consecutive scan sequences. If only one scan sequence is in the mux-channel-gain memory, the circuitry stops at the end of the sequence and waits the necessary interval time before starting the scan sequence again. If multiple scan sequences are in the mux-channel-gain memory, the circuitry stops at the end of each scan sequence and waits the necessary interval time before starting the next scan sequence in memory. When the end of the scan list is reached, the circuitry stops and waits the necessary interval time before sequencing through the channel-gain list again.

Data acquisition timing consists of signals that initiate a data acquisition operation, initiate individual A/D conversions, gate the data acquisition operation, and generate scanning clocks. The sources for these signals can be supplied by timers on the AT-MIO-16F-5 board, by signals connected to the AT-MIO-16F-5 I/O connector, or by signals from other AT Series boards connected to the RTSI bus.

Single A/D conversions can be initiated by applying an active-low pulse to the EXTCONV* input on the I/O connector or by writing to the Start Convert Register on the AT-MIO-16F-5 board. During data acquisition, the onboard sample-interval counter (Counter 3 of the Am9513A Counter/Timer) generates active-low pulses that initiate A/D conversions. External control of the sample interval is possible by applying a stream of pulses at the EXTCONV* input. In this case, you have complete external control over the sample interval and the number of A/D conversions performed. All data acquisition operations are functional with external signals to control conversions.

The sample-interval timer is a 16-bit down counter that can be used with the six internal timebases of the Am9513A to generate sample intervals from 0.4 µsec to 6 sec (see Timing I/O Circuitry later in this chapter). The sample-interval timer can also use any of the external clock inputs to the Am9513A as a timebase. During data acquisition, the sample interval counts down at the rate given by the internal timebase or external clock. Each time the sample-interval timer reaches zero, it generates an active low pulse and reloads with the programmed sample-interval count. This operation continues until data acquisition halts.

Data acquisition can be controlled by the onboard sample counter. This counter is loaded with the number of samples to be taken during a data acquisition operation. The sample counter can

be 16-bit for counts up to 65,535 or 32-bit for counts up to (2

- 1). If a 16-bit counter is needed, Counter 4 of the Am9513A Counter/Timer is used. If more than 16 bits are needed, Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32-bit counter. The sample counter decrements its count each time the sample-interval counter generates an A/D conversion pulse, and the sample counter stops the data acquisition process when it counts down to 0.

AT-MIO-16F-5 User Manual 3-8 © National Instruments Corporation

Page 69

Chapter 3 Theory of Operation

The data acquisition process can be initiated via software or by applying an active low pulse to the EXTTRIG* input on the AT-MIO-16F-5 I/O connector. These triggers start the sample-interval and sample counters. The sample-interval counter then manages the data acquisition process until the sample counter reaches zero.

The sample counter can be triggered in the same way as the data acquisition sequence; externally with the EXTTRIG* input on the AT-MIO-16F-5 I/O connector or internally via software. The counter can also be programmed so that is does not begin counting the A/D conversion pulses until a second falling edge signal occurs on EXTTRIG*. With pretriggering, A/D conversion samples can be collected both before and after a hardware or software trigger is received.

Single-Channel Data Acquisition

During single-channel data acquisition, the mux-channel-gain memory is set up to select the analog input channel and gain before data acquisition is initiated. These channel and gain settings remain constant during the entire data acquisition process; therefore, all A/D conversion data is read from a single channel.

Multiple-Channel (Scanned) Data Acquisition

Multiple-channel data acquisition is performed by enabling scanning during data acquisition. Multiple-channel scanning is controlled by the mux-channel-gain memory.

The mux-channel-gain memory consists of 512 words of memory. Each word of memory contains a multiplexer address (4 bits) for input analog channel selection, a gain setting (3 bits), a bit for synchronizing scanning sequences of different rates, and a bit indicating if the entry is the last in the scan sequence. (In interval scanning, a scan list can consist of any number of scan sequences.) Whenever a mux-channel-gain memory location is selected, the channel and gain control bits contained in that memory location are applied to the analog input circuitry. For scanning operations, the mux counter steps through successive locations in the mux-channel-gain memory at a rate determined by the scan clock. With the mux-channel-gain memory, therefore, an arbitrary sequence of channels with a separate gain setting for each channel can be clocked through during a scanning operation.

A SCANCLK signal is generated from the sample-interval counter. This signal pulses once at the beginning of each A/D conversion and is supplied at the I/O connector. During multiple-channel scanning, the mux-channel-gain memory location pointer is incremented repeatedly, thereby sequencing through the mux-channel-gain memory and automatically selecting new channel and gain settings during data acquisition. The MUXMEMCLK signal is generated from the SCANCLK and generates the pulses that increment the location pointer. In single-channel acquisition mode MUXMEMCLK is disabled and in multiple-channel acquisition mode MUXMEMCLK is enabled. MUXMEMCLK can be identical to SCANCLK, incrementing the mux counter once after every A/D conversion, or it can also be generated by dividing SCANCLK by Counter 1 of the Am9513A Counter/Timer. With this method, the location pointer can be incremented once every N A/D conversions so that N conversions can be performed on a single channel and gain selection before switching to the next channel and gain selection.

Page 70

Theory of Operation Chapter 3

Data Acquisition Rates

The acquisition and channel selection hardware function so that in the channel scanning mode, the next channel in the mux-channel-gain memory is selected immediately after the conversion process has begun on the previous channel. With this method, the input multiplexers and the instrumentation amplifier can settle to the new value within the specified conversion time of the AT-MIO-16F-5, which is 5 µsec maximum.

Analog Output Circuitry

The AT-MIO-16F-5 has two channels of 12-bit D/A output. Unipolar or bipolar output and internal or external reference voltage selection are available with each analog output channel. Figure 3-4 shows a block diagram of the analog output circuitry.

AT-MIO-16F-5 User Manual 3-10 © National Instruments Corporation

Page 71

Chapter 3 Theory of Operation

+5 V INT REF

From Gain DAC1

DAC1WR

DATA / 12

PC I/O Channel

DAC0WR

REF Selection

Internal

REF

DAC1 + op-amps

Bipolar/ Unipolar Selection

(W7)

DAC0 + op-amps

(W6)

(W4)

REF

From Offset DAC1

From Offset DAC0

REF

DAC1 OUT

AO GND

I/O Connector

DAC0 OUT

EXTREF

Internal

+5 V INT REF

From Gain DAC 0

REF

(W5)

REF Selection

Figure 3-4. Analog Output Circuitry Block Diagram

Each analog output channel contains a 12-bit DAC, output operational amplifiers (op-amps), reference selection jumpers, unipolar/bipolar output selection jumpers, and output data coding jumpers.

The DAC in each analog output channel generates a current proportional to the input voltage reference (V

) multiplied by the digital code loaded into the DAC. Each DAC can be loaded

ref

with a 12-bit digital code by writing to registers on the AT-MIO-16F-5 board. The output op-amps convert the DAC current output to a voltage output on the AT-MIO-16F-5 I/O connector DAC0 OUT and DAC1 OUT pins.

Page 72

Theory of Operation Chapter 3

The analog output of the DACs is updated to reflect the loaded 12-bit digital code in one of the following three ways:

• Immediately when the 12-bit code is written to the DACs.

• When an active low pulse is detected on the DACUPTRIG* signal with the WGEN bit set in

Command Register 2.

• When the Update Register is strobed with the WGEN bit set in Command Register 2. The AT-MIO-16F-5 incorporates onboard calibration circuitry to individually adjust the gain and

offset for each analog output channel. The startup calibration process is accomplished through means of retrieving constants stored in EEPROM on the AT-MIO-16F-5 and writing them to the calibration DAC. The board is calibrated at the factory and these calibration values are stored in unmodifiable locations in the EEPROM (see Figure 5-1). The board can also be recalibrated at the user's discretion and these new calibration constants can be stored in one of five user slots in the EEPROM. The EEPROM constants written to the calibration DAC can either be factory-calibrated values, or user-defined values to accommodate differing testing situations. A map of the EEPROM locations can be found in Chapter 5, Calibration Procedures.

The DAC output op-amps can be jumper-configured to generate either a unipolar voltage output or a bipolar voltage output range. A unipolar output has an output voltage range of 0 to +V

- 1 LSB V. A bipolar output has an output voltage range of -V

ref

to +V

-1 LSB V.

ref

For unipolar output, 0 V output corresponds to a digital code word of 0. For bipolar output, the form of the digital code input is software-selectable from Command Register 2. If straight binary form is selected, 0 V output corresponds to a digital code word of 2048. If two's complement form is selected, 0 V output corresponds to a digital code word of 0. One LSB is the voltage increment corresponding to an LSB change in the digital code word. For unipolar output, 1 LSB = (V

)/4096. For bipolar output, 1 LSB = (V

ref

)/2048.

ref

The voltage reference source for each DAC is jumper-selectable and can be supplied either externally at the EXTREF input or internally. The external reference can be either a DC or an AC signal. If an AC reference is applied, the analog output channel acts as a signal attenuator, and the AC signal appears at the output attenuated by the digital code divided by 4096 (unipolar output) or 2048 (bipolar output). The internal reference is an amplified version of the internal 5 V signal supplied in the input offset section. Using the internal reference supplies an output voltage range of 0 V to 9.9976 V in steps of 2.44 mV for unipolar output and an output voltage range of -10 V to +9.9951 V in steps of 4.88 mV for bipolar output. Gain calibration for the DACs applies only to the internal reference, not the external reference. Offset calibration can be applied to both references.

Note: Each DAC presents an impedance of 11 kΩ (unipolar mode) or 7 kΩ (bipolar mode) to

ground at the EXTREF input when the external reference option is selected.

Digital I/O Circuitry

The AT-MIO-16F-5 has eight digital I/O lines. These lines are divided into two ports of four lines each and are located at pins ADIO<3..0> and BDIO<3..0> on the I/O connector. Figure 3-5 shows a block diagram of the digital I/O circuitry.

Page 73

Chapter 3 Theory of Operation

ADIO <3..0>

BDIO <3..0>

EXTSTROBE

I/O Connector

EXT STROBE WR

DOUT0

Digital Output

DOUT1

Digital Output

Digital

Input

DATA <3..0>

DOUT0 ENABLE

DO REG WR

DATA <7..4>

DOUT1 ENABLE

DATA <7..0>

DIREG RD

PC I/O Channel

Figure 3-5. Digital I/O Circuitry Block Diagram

The digital I/O lines are controlled by the Digital Output Register and monitored by the Digital Input Register. The Digital Output Register is an 8-bit register that contains the digital output values for both ports 0 and 1. When port 0 is enabled, bits <3..0> in the Digital Output Register are driven onto digital output lines ADIO<3..0>. When port 1 is enabled, bits <7..4> in the Digital Output Register are driven onto digital output lines BDIO<3..0>.

Reading the Digital Input Register returns the state of the digital I/O lines. Digital I/O lines ADIO<3..0> are connected to bits <3..0> of the Digital Input Register. Digital I/O lines BDIO<3..0> are connected to bits <7..4> of the Digital Input Register. When a port is enabled, the Digital Input Register serves as a read-back register, returning the digital output value of the port. When a port is not enabled, reading the Digital Input Register returns the state of the digital I/O lines driven by an external device.

Both the digital input and output registers are TTL-compatible. The digital output ports, when enabled, are capable of sinking 24 mA of current and sourcing 2.6 mA of current on each digital I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs.

The external strobe signal EXTSTROBE*, shown in Figure 3-5, is a general-purpose strobe signal. Writing to an address location on the AT-MIO-16F-5 board generates an active low

Page 74

Theory of Operation Chapter 3

200 nsec pulse on this output pin. EXTSTROBE* is not necessarily part of the digital I/O circuitry but is shown here because it can be used to latch digital output from the AT-MIO-16F-5 into an external device.

Timing I/O Circuitry

The AT-MIO-16F-5 uses an Am9513A Counter/Timer for data acquisition timing and for general-purpose timing I/O functions. An onboard oscillator is used to generate the 10-MHz clock. Figure 3-6 shows a block diagram of the timing I/O circuitry.

FOUT

GATE2

OUT2

GATE1

SOURCE1

OUT1

GATE5

SOURCE5

OUT5

EXTTRIG

I/O Connector

Flip

Flop

5 MHz

÷5

Data

Acquisition

Timing

÷2

DATA<15..0>

/ 16

Am9513A RD/WR

/ 2

Am9513A

Counter/

GATE4

Channel

Timer

SOURCE4 SOURCE3

GATE3

1 MHz

SOURCE2

OUT1 OUT2 OUT3 OUT4 OUT5

Figure 3-6. Timing I/O Circuitry Block Diagram

BRDCLK (10 MHz)

RTSI Bus

CONVERT

SCANCLK

MUXMEMCLK

PC I/O Channel

The Am9513A contains five, independent, 16-bit counter/timers, a 4-bit frequency output channel, and five internally-generated timebases. The five counter/timers can be programmed to operate in several useful timing modes. The programming and operation of the Am9513A are presented in detail in Appendix C, AMD Data Sheet.

The Am9513A clock input is one-tenth the BRDCLK frequency selected by the W1 and W2 jumpers. The factory default for BRDCLK is 10 MHz, which generates a 1-MHz clock input to the Am9513A. The Am9513A uses this clock input plus a BRDCLK divided-by-two input at Source 2 to generate six internal timebases. These timebases can be used as clocks by the counter/timers and by the frequency output channel. When BRDCLK is 10 MHz, the six internal timebases normally used for AT-MIO-16F-5 timing functions are 5 MHz, 1 MHz, 100 kHz,

Page 75

Chapter 3 Theory of Operation

10 kHz, 1 kHz, and 100 Hz. The 16-bit counters in the Am9513A can be diagrammed as shown in Figure 3-7.

SOURCE

COUNTER

OUT

GATE

Figure 3-7. Counter Block Diagram

Each counter has a SOURCE input pin, a GATE input pin, and an output pin labeled OUT. The Am9513A counters are numbered 1 through 5, and their GATE, SOURCE, and OUT pins are labeled GATE N, SOURCE N, and OUT N, where N is the counter number.

For counting operations, the counters can be programmed to use any of the five internal timebases, any of the five GATE and five SOURCE inputs to the Am9513A, and the output of the previous counter (Counter 4 uses Counter 3 output, and so on). A counter can be configured to count either falling or rising edges of the selected input.

With the counter GATE input, counter operation can be gated. Once a counter is configured for an operation through software, a signal at the GATE input can be used to start and stop counter operation. The five gating modes available with the Am9513A are as follows:

• No gating

• Level gating active high

• Level gating active low

Page 76

Theory of Operation Chapter 3

• Low-to-high edge gating

• High-to-low edge gating A counter can also be active high level gated by a signal at GATE N+1 and GATE N-1, where N

is the counter number. The counter generates timing signals at its OUT output pin. The OUT output pin can also be set

to a high-impedance state or a grounded output state. The counters generate two types of output signals during counter operation: terminal count pulse output and terminal count toggle output. Terminal count is often referred to as TC. A counter reaches TC when it counts up or down and rolls over. In many counter applications, the counter reloads from an internal register when it reaches TC. In TC pulse output mode, the counter generates a pulse during the cycle that it reaches TC and reloads. In TC toggle output mode, the counter output changes state after it reaches TC and reloads. In addition, the counters can be configured for positive logic output or negative (inverted) logic output for a total of four possible output signals generated for one timing mode.

The GATE and OUT pins for Counters 1, 2, and 5 and SOURCE pins for Counters 1 and 5 of the onboard Am9513A are located on the AT-MIO-16F-5 I/O connector. A falling edge signal on the EXTTRIG* pin of the I/O connector or writing to the STARTDAQ register sets the flip-flop output signal connected to the GATE4 input of the Am9513A and can be used as an additional gate input. This mode is also used in the pretrigger data acquisition mode. The flip-flop output connected to GATE4 is cleared when the sample counter reaches TC, when an overflow or overrun occurs, or when the A/D Clear Register is written to. An overrun is defined as an error generated when the ADC cannot keep up with the conversion speed it was programmed for.

The Am9513A SOURCE5 pin is connected to the AT-MIO-16F-5 RTSI switch, which means that a signal from the RTSI trigger bus can be used as a counting source for the Am9513A counters.

The Am9513A OUT1, OUT2, and OUT5 pins can be used in several different ways. If waveform generation is enabled, an active low pulse on the output of the counter selected through the RTSI switch updates the analog output on the two DACs. The counter outputs can also be used to trigger interrupt and DMA requests. If the proper mode is selected in Command Register 2, an interrupt or DMA request occurs when a falling edge signal is detected on the selected DAC update signal.

Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing, and therefore are not available for general-purpose timing applications. Signals generated at OUT3 and OUT4 are sent to the data acquisition timing circuitry. GATE3 is controlled by the data acquisition timing circuitry. OUT3 is internally connected to EXTCONV* so that when internal data acquisition sequences (OUT3) are used, EXTCONV* should be disconnected or tri-stated. For the same reason, if external data acquisition sequences (EXTCONV*) are used, OUT3 should be programmed to the high-impedance state.

Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32-bit sample counter. The SCANCLK signal is connected to the SOURCE3 input of the Am9513A, and OUT1 is sent to the data acquisition timing circuitry. This allows Counter 1 to be used to divide the SCANCLK signal for generating the MUXMEMCLK signal (see Data Acquisition Timing Circuitry earlier in this chapter).

Page 77

Chapter 3 Theory of Operation

Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the mux-channel-gain memory. This mode is called interval channel scanning. See Multiple-Channel (Scanned) Data Acquisition earlier in this chapter.

The Am9513A 4-bit programmable frequency output channel is located at the I/O connector FOUT pin. Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source. The frequency output channel divides the selected source by its 4-bit programmed value and makes the divided down signal available at the FOUT pin.

RTSI Bus Interface Circuitry

The AT-MIO-16F-5 is interfaced to the National Instrument RTSI bus. The RTSI bus has seven trigger lines and a system clock line. All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC and share these signals. A block diagram of the RTSI bus interface circuitry is shown in Figure 3-8.

Page 78

Theory of Operation Chapter 3

OUT2

GATE1

DACUPTRIG

OUT5

DRV

Drivers

DRV

Drivers

RCV

EXTCONV

FOUT

SOURCE5

OUT1

EXTTRIG

RTSI SEL

Internal

Data Bus

BRDCLK

A0 A1 A2 A3

A4 A5 A6

/SEL DATA

RTSI

Switch

W1 and W2

B0 B1 B2 B3 B4

B5 B6

10-MHz Oscillator

RTSICLK

Trigger

RTSI Bus Connector

Figure 3-8. RTSI Bus Interface Circuitry Block Diagram

The RTSICLK line can be used to source a 10-MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus. BRDCLK is the system clock used by the AT-MIO-16F-5. The W1 and W2 jumpers select how these clock signals are routed.

The RTSI switch is a National Instruments custom-integrated circuit that acts as a 7x7 crossbar switch. Pins B<6..0> are connected to the seven RTSI bus trigger lines. Pins A<6..0> are connected to seven signals on the board. The RTSI switch can drive any of the signals at pins A<6..0> onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A<6..0>. With this capability, a signal interconnection scheme is completely flexible for any AT Series board sharing the RTSI bus. The RTSI switch is programmed via its chip select and data inputs.

On the AT-MIO-16F-5 board, nine signals are connected to pins A<6..0> of the RTSI switch with the aid of additional drivers. The signals GATE1, OUT1, OUT2, SOURCE5, OUT5, and FOUT are shared with the AT-MIO-16F-5 I/O connector and Am9513A Counter/Timer. The EXTCONV* and EXTTRIG* signals are shared with the I/O connector and the data acquisition timing circuitry. The DACUPTRIG* signal is used to update the two DACs on the AT-MIO-16F-5. With these onboard interconnections, AT-MIO-16F-5 general-purpose and data acquisition timing can be controlled over the RTSI bus as well as externally, and the AT-MIO-16F-5 and the I/O connector can send timing signals to other AT boards connected to the RTSI bus.

Page 79

Chapter 4 Programming

This chapter describes in detail the address and function of each of the AT-MIO-16F-5 registers. This chapter also includes important information about programming the AT-MIO-16F-5.

Note: If you plan to use a programming software package such as NI-DAQ or LabWindows 2.0

with your AT-MIO-16F-5 board, you do not need to read this chapter.

The register map for the AT-MIO-16F-5 is shown in Table 4-1. This table gives the register name, the register address, the type of the register (read only, write only, or read and write) and the size of the register in bits.

Table 4-1. AT-MIO-16F-5 Register Map

(Hex)

Configuration and Status Register Group:

Command Register 1 Base address + 0 Write only 16-bit Command Register 2 Base address + 2 Write only 16-bit Status Register Base address + 0 Read only 16-bit

Event Strobe Register Group:

Start Convert Register Base address + 8 Write only 8-bit Start DAQ Register Base address + A Write only 8-bit A/D Clear Register Base address + C Write only 8-bit External Strobe Register Base address + E Write only 8-bit DMA TC INT Clear Register Base address + 16 Write only 16-bit

Analog Output Register Group:

DAC0 Register Base address + 10 Write only 16-bit DAC1 Register Base address + 12 Write only 16-bit DAC Update INT Clear Register Base address + 14 Write only 8-bit DAC Update Register Base Address + E Read only 8-bit

(continues)

Page 80

Programming Chapter 4

Table 4-1. AT-MIO-16F-5 Register Map (continued)

(Hex)

Analog Input Register Group:

MUXMEMLD Register Base address + 4 Write only 8-bit MUXMEMCLR Register Base address + 5 Write only 8-bit MUXMEM Register Base address + 6 Write only 16-bit A/D FIFO Register Base address + 16 Read only 16-bit

Counter/Timer (Am9513A) Register Group:

Am9513A Data Register Base address + 18 Read and write 16-bit Am9513A Command Register Base address + 1A Write only 16-bit Am9513A Status Register Base address + 1A Read only 16-bit

Digital I/O Register Group:

Digital Input Register Base address + 1C Read only 16-bit Digital Output Register Base address + 1C Write only 16-bit

RTSI Switch Register Group:

RTSI Switch Shift Register Base address + 1E Write only 8-bit RTSI Switch Strobe Register Base address + 1F Write only 8-bit

Two different transfer sizes for read and write operations are available on the PC: byte (8-bit) and word (16-bit). Table 4-1 shows the size of each AT-MIO-16F-5 register. For example, reading the A/D FIFO Register requires a 16-bit (word) read operation at the selected address, whereas writing to the RTSI Strobe Register requires an 8-bit (byte) write operation at the selected address.

Table 4-1 divides the AT-MIO-16F-5 registers into seven different register groups. A bit description of each of the registers making up these groups is included later in this chapter.

The Configuration and Status Register Group controls the overall operation of the AT-MIO-16F-5 hardware. The Event Strobe Register Group is a group of registers that, when written to, generate some event on the AT-MIO-16F-5 board. The registers in the Analog Output Register Group access the AT-MIO-16F-5 DACs. With the Analog Input Register Group, ADC output can be read. The Counter/Timer Register Group consists of the three registers of the onboard Am9513A Counter/Timer chip. The registers in the Digital I/O Register Group access the onboard digital input and output lines. The registers in the RTSI Switch Register Group control the onboard RTSI switch.

Page 81

Chapter 4 Programming

The remainder of this register description chapter discusses each of the AT-MIO-16F-5 registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.

The register bit map shows a diagram of the register with the MSB (bit 15 for a 16-bit register, bit 7 for an 8-bit register) shown on the left, and the LSB (bit 0) shown on the right. A square is used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after the bit name indicates that the bit is inverted (negative logic).

In many of the registers, several bits are labeled with an X, indicating don't care bits. When a register is read, these bits may appear set or cleared but should be ignored because they have no significance.

The bit map field for some write-only registers states not applicable, no bits used. Writing to these registers generates a strobe in the AT-MIO-16F-5. These strobes are used to cause some onboard event to occur. For example, they can be used to clear the analog input circuitry or to start a data acquisition operation. The data is ignored when writing to these registers; therefore, any bit pattern suffices.

Configuration and Status Register Group

General control and monitoring of the AT-MIO-16F-5 hardware is accomplished through use of three registers making up the Configuration and Status Register Group. Command Registers 1 and 2 contain bits that control operation of several different pieces of the AT-MIO-16F-5 hardware. The Status Register can be used to read the state of different pieces of the AT-MIO-16F-5 hardware.

Bit descriptions of the three registers making up the Configuration and Status Group are given on the following pages.

Page 82

Programming Chapter 4

Command Register 1

Command Register 1 contains 16 bits that control AT-MIO-16F-5 serial device access, data acquisition mode selection, and analog input configuration.

Address: Base address + 0 (hex) Type: Write only Word Size: 16-bit Bit Map:

15 14 13 12 11 10 9 8

EEPROMCS SDATA SCLK CALDACLD 0 DITHER INTGATE CAL

7 6 5 4 3 2 1 0

DAQEN SCANEN SCN2 SCANDIV 16*/32CNT AIS/AIG SE/DIFF UNIP/BIP

Bit Name Description

15 EEPROMCS EEPROM Chip Select – This bit enables and disables the chip

select of the on-board EEPROM used to store calibration constants. When EEPROMCS is set, the chip select signal to the EEPROM is enabled. Before EEPROMCS is brought high, SCLK should first be pulsed high to initialize the EEPROM circuitry.

14 SDATA Serial Data – This bit is used to transmit a single bit to both the

EEPROM and the calibration DAC.

13 SCLK Serial Clock – A low-to-high transition of this bit clocks data into

the EEPROM (when EEPROMCS is set) and the calibration DAC. If EEPROMCS is cleared, toggling SCLK does not affect the EEPROM.

12 CALDACLD Calibration DAC Load – Pulsing CALDACLD high loads the

calibration DAC with the bits clocked in by SCLK. 11 0 Reserved Bit – This bit must always be set to zero. 10 DITHER Dither – When this bit is set, 0.5 LSB of White Gaussian Noise is

added to the selected analog input signal. By enabling DITHER

and using averaging, greater input resolution can be achieved.

9 INTGATE Internal Gate – When this bit is set, no A/D conversions take place.

INTGATE can be used as a software gating tool, or to inhibit

random conversions during setup operations.

Page 83

Chapter 4 Programming

Bit Name Description

8 CAL Calibration – This bit controls the analog input configuration

switches. CAL is used to disconnect the input multiplexers from

the instrumentation amplifier during a calibration procedure so that

known internal reference signals can be routed to the amplifier.

See Table 4-2.

7 DAQEN Data Acquisition Enable – This bit enables and disables a data

acquisition operation that is controlled by the onboard sample-

interval and sample counters. If DAQEN is set, a software

(STARTDAQ) or hardware (EXTTRIG*) trigger starts the

counters (assuming that the counters are programmed and

enabled), thereby initiating a data acquisition operation. If

DAQEN is cleared, software and hardware triggers are ignored.

6 SCANEN Scan Enable – This bit enables and disables multiple-channel

scanning during data acquisition. If SCANEN is set, alternate

analog input channels are sampled during data acquisition under

control of the mux-channel-gain memory. If SCANEN is cleared,

a single analog input channel is sampled during the entire data

acquisition operation.

5 SCN2 Scan Mode 2 – This bit selects the data acquisition scanning mode

used when scanning multiple A/D channels. If SCN2 is cleared

and SCANEN is set, continuous channel scanning is used. In this

mode, scan sequences are repeated with no delays between cycles.

If SCN2 is set and SCANEN is set, interval channel scanning is

used. In this mode, scan sequences occur during a programmed

time interval, called a scan interval. One cycle of the scan

sequence occurs during each scan interval.

4 SCANDIV Scan Divide – This bit enables and disables division of the

Mux-Counter Clock during data acquisition. The Mux-Counter

Clock controls sequencing of the mux-channel-gain memory. If

SCANDIV is set, the Mux-Counter Clock is controlled by Counter

1 of the Am9513A Counter/Timer. If SCANDIV is cleared, the

Mux-Counter Clock generates one pulse per conversion.

3 16*/32CNT 16 or 32 bit sample count – This bit selects the count resolution for

the number of A/D conversions to be performed in a data

acquisition operation. If 16*/32CNT is cleared, a 16-bit count

mode is selected and Counter 4 of the Am9513A Counter/Timer

controls conversion counting. If 16*/32CNT is set, a 32-bit count

mode is selected and Counter 4 is concatenated with Counter 5 to

control conversion counting. A 16-bit count mode can be used if

the number of A/D sample conversions to be performed is less than

65,537. A 32-bit count mode should be used if the number of A/D

sample conversions to be performed is greater than or equal to

65,537.

Page 84

Programming Chapter 4

Bit Name Description

2 AIS/AIG Analog Input Sense/Analog Input Ground – This bit configures the

analog input section for RSE or NRSE mode when CAL is

disabled. When CAL is enabled, this bit controls the reference

signal connected to the positive(+) side of the instrumentation

amplifier. See Table 4-2.

1 SE/DIFF Single-Ended/Differential – This bit configures the analog input

section for single-ended or differential mode. See Table 4-2.

0 UNIP/BIP Unipolar/Bipolar – This bit configures the ADC for unipolar or

bipolar mode. In unipolar mode, values read from the A/D FIFO

are in straight binary format. For bipolar mode, the FIFO values

are automatically sign extended.

Table 4-2. Input Configuration

Input Mode Bit Map Effect

CAL

Inst Amp(+) Inst Amp(-)

AIS/AIG

SE/DIFF

DIFF 0 0 X Channels 0 to 7 Channels 8 to 15 RSE 0 1 0 Channels 0 to 15 AIGND NRSE 0 1 1 Channels 0 to 15 AISENSE

Offset Calibration 1 0 0 AIGND AIGND Gain Calibration 1 0 1 Internal +5 V Ref. AIGND DAC Offset

11 0 AIGND Channels 8 to 15

Calibration DAC Gain

11 1 Internal +5 V Ref. Channels 8 to 15

Calibration

Note: X indicates a don't care bit.

Page 85

Chapter 4 Programming

Command Register 2

Command Register 2 contains 16 bits that control AT-MIO-16F-5 interrupt and DMA modes, digital output drivers, and waveform generation modes.

Address: Base address + 2 (hex) Type: Write only Word Size: 16-bit Bit Map:

15 14 13 12 11 10 9 8

DIOPBEN DIOPAEN WGEN INTEN DMAEN DMATCINTEN CMPLINTEN DMAINTB2

76 543210

DMAINTB1 DMAINTB0 ADCFIFOREQ RETRIG A4RCV A4DRV A2RCV A2DRV

Bit Name Description

15 DIOPBEN Digital I/O Port B Enable – This bit enables and disables driving of

the 4-bit digital output port B by the Digital Output Register. If

DIOPBEN is set, the Digital Output Register drives the digital

lines. If DIOPBEN is cleared, the Digital Output Register drivers

are set to a high-impedance state; therefore an external device can

drive the digital lines. 14 DIOPAEN Digital I/O Port A Enable – This bit enables and disables driving of

the 4-bit digital output port A by the Digital Output Register. If

DIOPAEN is set, the Digital Output Register drives the digital

lines. If DIOPAEN is cleared, the Digital Output Register drivers

are set to a high-impedance state; therefore an external device can

drive the digital lines. 13 WGEN Waveform Generation Enable – This bit selects the update method

for the DAC outputs. When WGEN is cleared, both DAC0 and

DAC1 are updated when either DAC is written to. If WGEN is set,

both DACs are updated when an active low pulse is detected on the

DACUPTRIG* or when the DAC Update Register is strobed.

With the DACUPTRIG* method, the DACs can be updated by any

choice of OUT1, OUT2, OUT5 from the Am9513A counter/timer

chip, any other signal from another board connected to the RTSI

switch, or the EXTDACUPDATE* signal at the I/O connector.

Page 86

Programming Chapter 4

Bit Name Description

12 INTEN Interrupt Enable – This bit, along with the appropriate mode bits,

enables and disables interrupts generated from the AT-MIO-16F-5

board. To generate a specific interrupt, INTEN or a specific

interrupt enable bit must be set. See Table 4-3 and Interrupt

Programming later in this chapter. 11 DMAEN DMA Enable – This bit enables and disables the generation of

DMA requests. DMA requests can be generated from A/D

conversions as well as from DAC updates. If DMAEN is cleared,

no DMA requests are generated from the AT-MIO-16F-5 board.

To generate a specific DMA transfer, DMAEN and a specific

DMA enable bit must be set. See Table 4-3 and Programming

DMA Operations later in this chapter. 10 DMATCINTEN DMA Terminal Count Interrupt Enable – This bit enables and

disables generation of an interrupt when a DMA terminal count

pulse is received from the DMA controller in the PC AT. If

DMATCINTEN is set, an interrupt request is generated when the

DMA controller transfer count register decrements from zero to

FFFF (hex). The interrupt request is serviced by writing to the

DMA TC INT Clear Register. When DMATCINTEN is cleared,

no DMA terminal count interrupts are generated. See also

Programming DMA Operations later in this chapter.

9 CMPLINTEN DAQ Complete Interrupt Enable – This bit enables and disables

generation of an interrupt when a data acquisition sequence

completes. If CMPLINTEN is set, an interrupt request is

generated when the data acquisition operation completes. The

interrupt request is serviced by writing to the ADCLEAR Register.

When CMPLINTEN is cleared, completion of a data acquisition

sequence does not generate an interrupt. A data acquisition

sequence ends by running its course or when an error condition

occurs such as OVERRUN or OVERFLOW.

8 DMAINTB2 DMA Interrupt Bit 2 – see Table 4-3 for mode descriptions. Also

see Programming DMA Operations, and Interrupt Programming

later in this chapter.

7 DMAINTB1 DMA Interrupt Bit 1 – see Table 4-3 for mode descriptions. Also

see Programming DMA Operations, and Interrupt Programming

later in this chapter.

6 DMAINTB0 DMA Interrupt Bit 0 – see Table 4-3 for mode descriptions. Also

see Programming DMA Operations, and Interrupt Programming

later in this chapter.

Page 87

Chapter 4 Programming

Bit Name Description

5 ADCFIFOREQ ADC FIFO Request – This bit controls the ADC FIFO Interrupt

and DMA Request mode when enabled. When ADCFIFOREQ is

cleared, ADC interrupt/DMA requests are generated when a single

conversion is in the FIFO. When ADCFIFOREQ is set, ADC

interrupt/DMA requests are generated when the ADC FIFO is

half-full. In both cases, the request is removed when the ADC

FIFO is less than half-full.

4 RETRIG Retrigger – This bit controls the retrigger method of the acquisition

circuitry. When RETRIG is set, the data acquisition circuitry will

not retrigger until the DAQCOMP bit in the Status Register is

cleared by strobing the ADCLEAR Register. When RETRIG is

clear, retriggering may occur at any time after the previous

sequence has ended.

3 A4RCV A4 Receive – This bit controls a driver that allows the

DACUPTRIG*(DAC Update Trigger) signal to be driven from pin

A4 of the RTSI switch. If A4RCV is set, pin A4 of the RTSI

switch drives the DACUPTRIG* signal. If A4RCV is cleared, the

DACUPTRIG* signal is driven by the EXTDACUPDATE* signal.

2 A4DRV A4 Drive – This bit controls a driver that allows the OUT5 signal

to drive pin A4 of the RTSI switch. If A4DRV is set, pin A4 of the

RTSI switch is driven by OUT5. If A4DRV is cleared, pin A4 is

not driven.

1 A2RCV A2 Receive – This bit controls a driver that allows the GATE1

signal to be driven from pin A2 of the RTSI switch. If A2RCV is

set, pin A2 of the RTSI switch drives the GATE1 signal. If

A2RCV is cleared, the GATE1 signal is not driven by the RTSI

switch.

0 A2DRV A2 Drive – This bit controls a driver that allows the OUT2 signal

to drive pin A2 of the RTSI switch. If A2DRV is set, pin A2 of the

RTSI switch is driven by OUT2. If A2DRV is cleared, pin A2 is

not driven.

Page 88

Programming Chapter 4

Table 4-3. DMA and Interrupt Modes

Interface Mode

INTEN

DMAEN

DMAINTB2

DMAINTB1

DMAINTB0

00XXX No interrupts or DMA

0 1000 Analog input DMA (Channel A) 0 1001 Analog output DMA (Channel A to DAC 0) 0 1010 Analog output DMA (Channel A to DAC 1) 0 1011 Analog output DMA (Channel A to DACs 0/1) 0 1100 Analog input DMA (Channels A/B) 0 1101 Analog I/O DMA (Channel A in and Channel B to DAC 0) 0 1110 Analog I/O DMA (Channel A in and Channel B to DAC 1) 0 1111 Analog I/O DMA (Channel A in and Channel B to DACs 0/1)

1 0000 No interrupts or DMA 1 0001 ADCFIFO interrupt 1 0010 DACUP interrupt 1 0011 ADCFIFO and DACUP interrupts 1 0100 No interrupts or DMA 1 0101 No interrupts or DMA 1 0110 No interrupts or DMA 1 0111 No interrupts or DMA

Mode Description

1 1000 Analog input DMA (Channel A) with DACUP INT 1 1001 Analog output DMA (Channel A to DAC 0) with ADCFIFOINT 1 1010 Analog output DMA (Channel A to DAC 1) with ADCFIFOINT 1 1011 Analog output DMA (Channel A to DACs 0/1) with ADCFIFOINT 1 1100 Analog input DMA (Channels A/B) with DACUP INT 1 1101 No interrupts or DMA 1 1110 Analog output DMA (Channels A/B to DACs 0/1)* 1 1111 Analog output DMA (Channels A/B to DACs 0/1) with ADCFIFOINT*

Note: X indicates a don't care bit. * In this analog output mode, the channels are defined to be synchronous, that is, they must

operate concurrently. If one channel stops, the other channel also stops.

Page 89

Chapter 4 Programming

Status Register

The Status Register contains 16 bits of AT-MIO-16F-5 hardware status information, including interrupt, analog input status, and data acquisition progress.

Address: Base address + 0 (hex) Type: Read only Word Size: 16-bit Bit Map:

15 14 13 12 11 10 9 8

DAQCOMP DAQPROG FIFOHF* FIFOEF* DMATC DMATCA DMATCB OVERFLOW*

7 6 5 4 3 2 1 0

OVERRUN* DACUP DACUPERR FACTCAL* PROMOUT EEPROMCD* MUXMEMFF* MUXMEMEF*

Bit Name Description

15 DAQCOMP Data Acquisition Complete – This bit reflects the status of the data

acquisition termination interrupt. If DAQCOMP is set and either

OVERFLOW* or OVERRUN* is clear, the current interrupt is due

to an error condition. If DAQCOMP is set and neither

OVERFLOW* nor OVERRUN* is clear, the data acquisition

operation has completed without error. When DAQCOMP

becomes set, if ADCFIFOREQ in Command Register 2 is also set,

enabled interrupt or DMA requests are generated until the ADC

FIFO is empty. DAQCOMP is cleared by writing to the A/D Clear

acquisition operation is in progress. If DAQPROG is set, a data

acquisition operation is in progress. If DAQPROG is cleared, the

data acquisition operation has completed. 13 FIFOHF* FIFO Half-Full Flag – This bit reflects the state of the A/D FIFO.

If the appropriate conversion interrupts are enabled (see Table 4-3)

and FIFOHF* is clear, the current interrupt indicates at least 128

A/D conversions are available in the A/D FIFO. To clear the

interrupt, read the A/D FIFO until FIFOHF* becomes set. If

FIFOHF* is set, less than 128 A/D conversions are available in the

A/D FIFO.

Page 90

Programming Chapter 4

Bit Name Description

12 FIFOEF* FIFO Empty Flag – This bit reflects the state of the A/D FIFO. If

FIFOEF* is set, one or more A/D conversion results can be read

from the A/D FIFO. If the appropriate conversion interrupts are

enabled (see Table 4-3) and FIFOEF* is set, the current interrupt

indicates that A/D conversion data is available in the A/D FIFO.

To clear the interrupt, the FIFO must be read until it is empty. If

FIFOEF* is cleared, the A/D FIFO is empty and no conversion

interrupt request is asserted. 11 DMATC DMA Terminal Count – This bit is high if either DMATCA,

DMATCB, or both are high. 10 DMATCA DMA Terminal Count Channel A – DMATCA reflects the status

of the DMA process on the selected DMA Channel A. When the

DMA operation is finished, DMATCA goes high and remains high

until cleared using the DMA TC INT Clear Event Strobe Register.

If DMATCINTEN is set, an interrupt is generated when DMATCA

goes high.

9 DMATCB DMA Terminal Count Channel B – DMATCB reflects the status

of the DMA process on the selected DMA Channel B. When the

DMA operation is finished, DMATCB goes high and remains high

until cleared using the DMA TC INT Clear Event Strobe Register.

If DMATCINTEN is set, an interrupt is generated when DMATCB

goes high.

8 OVERFLOW* Overflow – This bit indicates whether the A/D FIFO has

overflowed during a sample run. OVERFLOW* is an error

condition that occurs if the FIFO fills up with A/D conversion data

and A/D conversions continue. If OVERFLOW* is clear, A/D

conversion data has been lost because of FIFO overflow. If

OVERFLOW* is set, no overflow has occurred. If OVERFLOW*

occurs during a data acquisition operation, the data acquisition is

terminated immediately. This bit can be reset by writing to the

A/D Clear Register.

7 OVERRUN* Overrun – This bit indicates whether an A/D conversion was

initiated before the previous A/D conversion was complete.

OVERRUN* is an error condition that can occur if the data

acquisition sample interval is too small (sample rate is too high). If

OVERRUN* is clear, one or more conversions were skipped. If

OVERRUN* is set, no overrun condition has occurred. If

OVERRUN* occurs during a data acquisition operation, the data

acquisition is terminated immediately. This bit can be reset by

writing to the A/D Clear Register.

Page 91

Chapter 4 Programming

Bit Name Description

6 DACUP DAC Update – This bit reflects the status of the DAC update.

DACUP is cleared by writing to the DAC Update INT Clear

DACUPTRIG* at the RTSI switch is detected. This condition

generates an interrupt or DMA request only if the proper interrupt

mode is selected in Command Register 1 according to Table 4-3. 5 DACUPERR DAC Update Error – This bit reflects an error condition during

DAC waveform generation operations to the analog output

circuitry (WGEN set in Command Register 2). If an update

(DACUPTRIG*) occurs before a new value can be written to the

DAC, DACUPERR is set indicating a value being updated to the

DAC twice.

4 FACTCAL* Factory Calibration – When this bit is set, the board has been

factory-calibrated and the calibration constants have been written

to the upper 11 locations in the EEPROM. Any further attempt to

modify these locations has no effect. If FACTCAL* is low, then

all locations of the EEPROM may be written to. (This mode is not

recommended, as locations 0 through 51 are available with

FACTCAL* set.)

3 PROMOUT EEPROM Output – This bit reflects the value of the data shifted

out of the EEPROM using SCLK with EEPROMCS enabled.

2 EEPROMCD* EEPROM Chip Deselect – This reflects the status of the EEPROM

chip select pin. Because protection circuitry surrounds the

EEPROM, having EEPROMCS enabled in Command Register 1

does not necessarily result in the EEPROM being enabled. If

EEPROMCD* is low after a mode has been shifted into the

EEPROM, then an error occurred in shifting in an unsupported

mode. To initialize EEPROMCD*, EEPROMCS must be brought

low while SCLK is pulsed high.

1 X Don't care bits.

0 MUXMEMEF* MUX Memory Empty Flag – If this bit is clear, the mux-channel-

gain memory is empty and can be written to. If MUXMEMEF* is

set, the mux-channel-gain memory is not empty.

Page 92

Programming Chapter 4

The Event Strobe Register Group

The Event Strobe Register Group consists of five registers that, when written to, cause the occurrence of certain events on the AT-MIO-16F-5 board, such as clearing flags and starting A/D conversions.

Bit descriptions of the five registers making up the Event Strobe Register Group are given on the following pages.

Start Convert Register

Writing to the Start Convert Register location initiates an A/D conversion. Address: Base address + 8 (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used

Note: A/D conversions can be initiated in one of two ways: by writing to the Start Convert

Register or by detecting an active-low signal on the EXTCONV* signal. The EXTCONV* signal is connected to pin 40 on the I/O connector, to OUT3 of the Am9513A, and to the A0 pin of the RTSI bus switch. If EXTCONV* is driven low by any one of these sources, it prevents the Start Convert Register from initiating an A/D conversion. If the Start Convert Register is to initiate A/D conversions, the OUT3 signal should be initialized to a high-impedance state, any signal connected to pin 40 of the I/O connector should be in a high-impedance or high state, and the A0 pin of the RTSI bus switch should be configured as an input pin.

Page 93

Chapter 4 Programming

Start DAQ Register

Writing to the Start DAQ Register location initiates a multiple A/D conversion data acquisition operation.

Note: Several other pieces of AT-MIO-16F-5 circuitry must be set up before a data acquisition

run can occur. See Programming Considerations later in this chapter. Address: Base address + A (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used

Note: Multiple A/D conversion data acquisition operations can be initiated in one of two ways:

by writing to the Start DAQ Register or by detecting an active-low signal on the

EXTTRIG* signal. The EXTTRIG* signal is connected to pin 38 on the I/O connector

and to the A6 pin of the RTSI bus switch. If EXTTRIG* is driven low by either of these

sources, it prevents the Start DAQ Register from initiating a multiple A/D conversion

data acquisition operation. If the Start DAQ Register is to initiate multiple A/D

conversions, any signal connected to pin 38 of the I/O connector should be in a high-

impedance or high state and the A6 pin of the RTSI bus switch should not be driven low.

Page 94

Programming Chapter 4

A/D Clear Register

Writing to the A/D Clear Register location clears the data acquisition circuitry. Writing to the A/D Clear Register initiates the following events:

• Any data acquisition operation in progress is canceled.

• The A/D FIFO is emptied.

• The overrun flag is cleared.

• The overflow flag is cleared.

• Any pending FIFOEF* interrupt is cleared.

• The DAQCOMP bit in the Status Register is cleared.

• The mux-channel-gain memory is reset to start at the beginning of the list. Address: Base address + C (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used Note: If the mux-channel-gain memory already contains valid information and no new values

are to be added before restarting the data acquisition sequence, the MUXMEMLD

External Strobe Register

Writing to the External Strobe Register location generates an active low, approximately 200 to 500 nsec strobe pulse at the EXTSTROBE output at the I/O connector. This pulse can be useful for several applications, including generating external general-purpose triggers and latching data into external devices (for example, from the digital output port).

Address: Base address + E (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used

DMA TC INT Clear Register

Writing to the DMA TC INT Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected. DMA TC INT Clear also clears both DMATCA and DMATCB in the Status Register.

Address: Base address + 16 (hex) Type: Write only Word Size: 16-bit Bit Map: Not applicable, no bits used

Page 95

Chapter 4 Programming

Analog Output Register Group

The registers making up the Analog Output Register Group load the two analog output channels. DAC0 controls analog output Channel 0. DAC1 controls analog output Channel 1. These DACs are written to individually, and the analog output can be updated immediately or each time an active low pulse is detected on the DACUPTRIG* signal or the DAC Update Register is strobed with the WGEN bit set in Command Register 2.

Bit descriptions of the four registers making up the Analog Output Register Group are given on the following pages.

DAC0 Register

Writing to DAC0 loads the corresponding analog output channel DAC. The voltages generated by the analog output channels are updated either immediately or when an active low pulse occurs on DACUPTRIG* or the DAC Update Register is strobed. The update method is selected by the WGEN bit in Command Register 2.

Address: Base address + 10 (hex) loads DAC0 Type: Write only Word Size: 16-bit Bit Map:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XXXXD11D10D9D8D7D6D5D4D3D2 D1D0

MSB LSB

Bit Name Description

15 - 12 X Don't care bits. 11 - 0 D<11..0> These twelve bits are loaded into the DAC and update the voltage

generated by the analog output channel in one of three ways, immediately, upon a DACUPTRIG* pulse, or with a strobe of the DAC Update Register. See Table 4-6 and Table 4-7, both of which map digital values to output voltage.

Page 96

Programming Chapter 4

DAC1 Register

Writing to DAC1 loads the corresponding analog output channel DAC. The voltages generated by the analog output channels are updated either immediately or when an active low pulse occurs on DACUPTRIG* or the DAC Update Register is strobed. The update method is selected by the WGEN bit in Command Register 2.

Address: Base address + 12 (hex) loads DAC1 Type: Write only Word Size: 16-bit Bit Map:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

XXXXD11D10D9D8D7D6D5D4D3D2 D1D0

MSB LSB

Bit Name Description

15 - 12 X Don't care bits. 11 - 0 D<11..0> These twelve bits are loaded into the DAC and update the voltage

Page 97

Chapter 4 Programming

DAC Update INT Clear Register

Writing to the DAC Update INT Clear Register clears the DACUP and DACUPERR bits after a DACUPTRIG* pulse is detected. Clearing DACUP when interrupt or DMA mode is enabled clears the respective interrupt or DMA request.

Address: Base address + 14 (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used The analog output DACs can be updated internally and externally in the waveform generation

mode (WGEN set in Command Register 2) through the control of A4RCV. If A4RCV is enabled, internal updating is selected and any signal from the RTSI switch controls the updating interval. If OUT2 is to be used for updating the DACs, then A2DRV must also be enabled. If OUT5 is to be used, then A4DRV must be enabled as well. If A4RCV is disabled, then external updating is selected and the EXTDACUPDATE* signal from pin 44 of the I/O connector is used for updating.

In both cases, a falling edge on the selected signal triggers the updating mechanism. This trigger also sets the DACUP bit in the Status Register and generates an interrupt or DMA request if so enabled.

DAC Update Register

Reading from the DAC Update Register with waveform generation enabled updates both DAC0 and DAC1 simultaneously with the previously written values.

Address: Base address + E (hex) Type: Read only Word Size: 8-bit Bit Map: Not applicable, no bits used.

Page 98

Programming Chapter 4

Analog Input Register Group

The four registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the A/D FIFO.

Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages.

MUXMEMLD Register

Writing to the MUXMEMLD Register loads the mux-channel-gain memory. Address: Base address + 4 (hex) Type: Write only Word Size: 8-bit Bit Map: Not applicable, no bits used. Writing to the MUXMEMLD Register loads the mux-channel-gain memory values and applies

the first channel-gain value to the analog input circuitry. After the final write to the muxchannel-gain memory, writing to the MUXMEMLD Register loads the first channel-gain value. Writing to the MUXMEMLD Register again loads the second channel-gain value, and so on.

Strobing the ADCLEAR Register resets the mux-channel-gain memory to the first value, but does not load the value. It does not clear the memory of any values written to it prior to the ADCLEAR strobe. After an ADCLEAR strobe, the MUXMEMLD Register should be strobed to load the first value. Using this method, a scanned data acquisition can be initiated from any location in the mux-channel-gain memory.

MUXMEMCLR Register

Writing to the MUXMEMCLR Register clears all information in the mux-channel-gain memory. Address: Base address + 5 (hex) Type: Write only Word Size: 8-bit Bit map: Not applicable, no bits used. Before the mux-channel-gain memory is written to, it must be cleared of its information and reset

to its initialized state. Writing to the MUXMEMCLR Register accomplishes this. Once this operation occurs, old channel-gain values are cleared and not recoverable. At this point, the mux-channel-gain memory is ready to be filled with valid information.

Page 99

Chapter 4 Programming

MUXMEM Register

The MUXMEM Register controls the multiplexer and gain settings, and can contain up to 512 channel and gain settings for use in scanning sequences.

Address: Base address + 6 (hex)

Type: Write only

Word Size: 16-bit

Bit Map:

15 14 13 12 11 10 9 8

0 0 0 0 0 0 0 GHOST_CONV

76543210

MA3 MA2 MA1 MA0 GAIN2 GAIN1 GAIN0 LASTONE

Bit Name Description

15 - 9 0 These bits should be left clear for proper board operation.

8 GHOST_CONV This bit is used to synchronize conversions in time for multiple rate

channel scanning. When this bit is set with any channel/gain value, the conversion occurs on the selected channel, but the value is not saved in the A/D FIFO. In addition, if the sample counter is programmed to count samples from Source 4, conversions with the GHOST_CONV bit set are not counted. When the GHOST_CONV bit is clear, conversions occur normally and are saved in the A/D FIFO.

7 - 4 MA<3..0> This 4-bit field controls the multiplexer address setting of the input

multiplexers, thereby allowing the analog input channel to be selected. In single-ended mode, only one analog input channel is selected. In differential mode, two analog input channels are selected. The following table shows the analog input channel selected for either mode.

Page 100

Programming Chapter 4

MA<3..0> Selected Analog Input Channels

Single-Ended Differential

(+) (-)

0000 0 0 and 8 0001 1 1 and 9 0010 2 2 and 10 0011 3 3 and 11 0100 4 4 and 12 0101 5 5 and 13 0110 6 6 and 14 0111 7 7 and 15 1000 8 0 and 8 1001 9 1 and 9 1010 10 2 and 10 1011 11 3 and 11 1100 12 4 and 12 1101 13 5 and 13 1110 14 6 and 14 1111 15 7 and 15

3 - 1 GAIN<2..0> This 3-bit field controls the gain setting of the input

instrumentation amplifier. The following gains can be selected on the AT-MIO-16F-5 board:

GAIN<2..0> Actual Gain

000 0.5 001 1 010 2 011 5 100 10 101 20 110 50 111 100

0 LASTONE This bit should be set in the last entry of the scan sequence loaded

into the mux-channel-gain memory. More than one occurrence of the LASTONE bit is possible in the mux-channel-gain memory list for the interval scanning mode. In other words, there can be multiple scan sequences in one memory list.

National Instruments AT-MIO-16F-5 Owners Manual

Specifications and Main Features

Frequently Asked Questions

User Manual